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2016-11-23drm/amdgpu: remove amdgpu_irq_get_delayedChristian König2-12/+0
Not used any more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-23amdgpu: Wrap dev_err() calls on vm faults with printk_ratelimit()Edward O'Callaghan3-21/+27
It can be the case that upon GPU page faults we start trashing the logs, and so let us ratelimit here to avoid that. V2. Fix issue where calling dev_err_ratelimited separately for each line means that some lines corresponding to a single VM fault may or may not appear depending on the rate. - Michel Dänzer. Reviewed-by: Christian König <[email protected]> (v1) Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-23amdgpu: Use dev_err() over vanilla printk() in vm_decode_fault()Edward O'Callaghan2-2/+2
Reviewed-by: Christian König <[email protected]> Signed-off-by: Edward O'Callaghan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-23drm/amd/amdgpu: port of DCE v6 to new headers (v3)Tom St Denis3-247/+350
Port of SI DCE v6 over to new AMDGPU headers. Tested on a Tahiti with GNOME through various hot plugs/rotations/sizes/fullscreen/windowed and staging drm/xf86-video-amdgpu. (v2) Re-factored to remove formatting changes to si_enums.h as well rename various defines. (v3) Rebase on upstream Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-23drm/amdgpu: cleanup unused iterator members for sdma v2.4Huang Rui1-1/+1
Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-23drm/amdgpu: cleanup unused iterator members for sdma v3Huang Rui1-1/+1
Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-23drm/amdgpu:impl vgt_flush for VI(V5)Monk Liu3-25/+60
when shadowing enabled, tesselation app will trigger vm fault because below three tesselation registers: VGT_TF_RING_SIZE__CI__VI, VGT_HS_OFFCHIP_PARAM__CI__VI, VGT_TF_MEMORY_BASE__CI__VI, need to be programed after vgt-flush. Tesselation picture vm fault disappeared after vgt-flush introduced. v2:implement vgt-flush for CI & SI. v3:move vgt flush inside of cntx_cntrl v4:count vgt flush in frame_size v5:squash in typo fix Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-23drm/amdgpu: enable uvd mgcg for Fiji.Rex Zhu1-1/+2
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-23drm/amdgpu: refine cz uvd clock gate logic.Rex Zhu2-6/+4
sw clockgate was used on uvd6.0. when uvd is idle, we gate the uvd clock. when decode, we ungate the uvd clock. Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-23drm/amdgpu: fix power state when port pm is unavailablePeter Wu1-1/+8
When PCIe port PM is not enabled (system BIOS is pre-2015 or the pcie_port_pm=off parameter is set), legacy ATPX PM should still be marked as supported. Otherwise the GPU can fail to power on after runtime suspend. This affected a Dell Inspiron 5548. Ideally the BIOS date in the PCI core is lowered to 2013 (the first year where hybrid graphics platforms using power resources was introduced), but that seems more risky at this point and would not solve the pcie_port_pm=off issue. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=98505 Reported-and-tested-by: Nayan Deshmukh <[email protected]> Signed-off-by: Peter Wu <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: <[email protected]> # 4.8+ Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
2016-11-16drm/amd/powerplay: avoid out of bounds access on array ps.Rex Zhu1-6/+6
check array index first and then visit the array. Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-15drm/irq: Unexport drm_vblank_on/offDaniel Vetter1-2/+2
Only remaining use was in amdgpu, and trivial to convert over to drm_crtc_vblank_* variants. Cc: Alex Deucher <[email protected]> Cc: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2016-11-15drm/amdgpu: Use drm_crtc_vblank_on/off for dce6Daniel Vetter1-2/+2
This old code pattern was reintroduced in Author: Ken Wang <[email protected]> Date: Tue Jan 19 14:03:24 2016 +0800 drm/amdgpu: add display controller implementation for si v10 Realign it with later display code. Tsk, tsk for massive copypasting ;-) Cc: Christian König <[email protected]> Cc: Ken Wang <[email protected]> Cc: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> for the whole series. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2016-11-15drm/amdgpu:fix vpost_needed routineMonk Liu1-20/+7
1,cleanup description/comments 2,for FIJI & passthrough, force post when smc fw version below 22.15 3,for other cases, follow regular rules Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-15drm/amdgpu/powerplay: drop a redundant NULL checkAlex Deucher1-2/+0
Left over from an earlier rev of the patch. Acked-by: Colin Ian King <[email protected]> Cc: Dan Carpenter <[email protected]> Cc: Colin King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-15drm/amdgpu: change log level to KERN_INFO in ci_dpm.cRex Zhu1-1/+1
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-15drm/amdgpu: always un-gate UVD REGS path.Rex Zhu1-0/+2
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-15drm/amdgpu/sdma: fix typo in packet setupAlex Deucher2-2/+2
Use the correct define. No functional change as both defines are equivalent. Reviewed-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-14drm/amdgpu: use DRM_FB_HELPER_DEFAULT_OPS for fb_opsStefan Christ1-7/+1
Cc: Alex Deucher <[email protected]> Cc: Christian König <[email protected]> Signed-off-by: Stefan Christ <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2016-11-12drm: move allocation out of drm_get_format_name()Eric Engestrom4-13/+11
The function's behaviour was changed in 90844f00049e, without changing its signature, causing people to keep using it the old way without realising they were now leaking memory. Rob Clark also noticed it was also allocating GFP_KERNEL memory in atomic contexts, breaking them. Instead of having to allocate GFP_ATOMIC memory and fixing the callers to make them cleanup the memory afterwards, let's change the function's signature by having the caller take care of the memory and passing it to the function. The new parameter is a single-field struct in order to enforce the size of its buffer and help callers to correctly manage their memory. Fixes: 90844f00049e ("drm: make drm_get_format_name thread-safe") Cc: Rob Clark <[email protected]> Cc: Christian König <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Rob Clark <[email protected]> Acked-by: Sinclair Yeh <[email protected]> (vmwgfx) Reviewed-by: Jani Nikula <[email protected]> Suggested-by: Ville Syrjälä <[email protected]> Signed-off-by: Eric Engestrom <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Link: http://patchwork.freedesktop.org/patch/msgid/[email protected]
2016-11-11drm/amd/amdgpu: Port GMC v6 driver to new SI headers (v2)Tom St Denis2-147/+184
Port the GMC v6 driver over to the new SI headers. Tested with a Tahiti SI ASIC. (v2) Fixed a couple of typos (in commented code) and moved defines to si_enums.h Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amd/powerplay: add mask bit for fan control mode.Rex Zhu2-2/+4
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amdgpu: remove extra placement for AMDGPU_GEM_CREATE_NO_CPU_ACCESSChristian König1-11/+0
This only has the effect of scanning the invisible range twice since the topdown flag is given anyway. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: JimQu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amdgpu: disable the VRAM manager on special placements v2Christian König1-1/+1
This disables the VRAM manager when a special placement is requested, otherwise we play ping/pong with the buffers on every command submission. v2: only check lpfn Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: JimQu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amdgpu: refine uvd 5.0 clock gate feature.Rex Zhu1-23/+83
1. fix uvd cg status not correct. 2. fix uvd pg can't work on tonga. 3. enable uvd mgcg. Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Tom St Denis <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amd/powerplay: partial revert commit 01b0e7fb1.Rex Zhu1-2/+2
when uvd is idle, we gate uvd clock. and uvd is busy, we ungate uvd clock. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amdgpu: not set bypass mode for uvd5.0/uvd6.0Rex Zhu2-31/+2
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amd/amdgpu: add wave reader to gfx v6Tom St Denis1-0/+36
Add support for the debugfs wave reader. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amd/amdgpu: port gfx6 over to new si headers (v2)Tom St Denis1-343/+336
This changes the gfx v6 driver to use the new AMDGPU style SI headers. Also fixes a variety of coding style issues, white space issues, and uses WREG32_FIELD in a few places where appropriate. Tested with a Tahiti 0x679A. v2: Squash in typo fix patch Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amd/amdgpu: add SI defines/registersTom St Denis3-0/+213
Add missing gca MMIO registers and defines necessary for the next patch which re-works a lot of gfx v6 to use the new SI headers. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amd/amdgpu: Introduction of SI registers (v2)Tom St Denis16-0/+54087
This introduces the SI registers in the amdgpu driver style. v2: squash duplicates fix Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amd/amdgpu : Fix NULL pointer comparisonRavikant B Sharma3-4/+3
Replace direct comparisons to NULL i.e. 'x == NULL' with '!x'. As per coding standard. Reviewed-by: Christian König <[email protected]> Signed-off-by: Ravikant B Sharma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amd/amdgpu: Clean up wave gfx8 helperTom St Denis1-1/+5
De-numberify indirect register access for gfx v8. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amd/amdgpu: Clean up wave gfx7 helperTom St Denis1-1/+5
De-numberify indirect register access for gfx v7. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amdgpu: fix logic error for checking amdgpu_vram_page_splitjimqu1-2/+2
Reviewed-by: Christian König <[email protected]> Signed-off-by: JimQu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amd/powerplay:Tonga not to start SMC if SRIOVTrigger Huang1-1/+2
This patch is used for virtualization support. In virtualization case, Tonga SMC should not be started and SMU firmware should not be loaded if in SRIOV environment. The same operation will be applied on FIJI in other patch. Signed-off-by: Monk Liu <[email protected]> Signed-off-by: Trigger Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amdgpu: refine uvd_4.2 clock gate sequence.Rex Zhu2-39/+9
1. partial revert commit 91db308d6e96. not set uvd bypass mode. 2. enable uvd cg before initialize uvd. 3. set uvd clock to default value 100MHz. Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amd/powerplay: delete duplicate code in smu7_hwmgr.cRex Zhu1-7/+0
Voltage Controller have been enabled (SMC message) before ULV enablement. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amd/powerplay: enable voltage control by default for dgpu.Rex Zhu1-6/+3
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amd/powerplay: fix code styleRex Zhu1-2/+3
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amdgpu: delete duplicate module parameter.Rex Zhu2-9/+9
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amdgpu: use mask bit for deep sleep feature on dpm.Rex Zhu4-3/+5
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amd/powerplay: use mask bit for deepsleep/power tune feature.Rex Zhu2-4/+2
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amdgpu/powerplay: pp module only enable smu when dpm disabled.Rex Zhu3-15/+44
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amdgpu:bypass avfs event manager for sriovTrigger Huang1-1/+5
This patch is used for virtualization support. In virtualization case, the initialization sequences are not totally the same as non-Virtualization's. The avfs event manager should be bypassed if in SRIOV virtualization case. At the same, this patch will also bypass starting SMC within SRIOV in FIJI, so the SMU firmware loading will be avoid, which is required in SRIOV. Signed-off-by: Frank Min <[email protected]> Signed-off-by: Xiangliang Yu <[email protected]> Signed-off-by: Trigger Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amdgpu:no gpu scheduler for KIQTrigger Huang1-18/+21
KIQ is used for interaction between driver and CP, and not exposed to outside client, as such it doesn't need to be handled by GPU scheduler. Signed-off-by: Monk Liu <[email protected]> Signed-off-by: Xiangliang Yu <[email protected]> Signed-off-by: Trigger Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amdgpu: Add a ring type KIQ definitionTrigger Huang1-1/+2
Add a new ring type definition for KIQ. KIQ is used for interaction between driver and CP. Signed-off-by: Xiangliang Yu <[email protected]> Signed-off-by: Trigger Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amdgpu: enable UVD clockgating in Polaris-10/11Maruthi Srinivas Bayyavarapu1-2/+2
UVD clocks are set to be disabled, when not in use. Signed-off-by: Maruthi Bayyavarapu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Tom StDenis <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amd/amdgpu: expose fan rpm though hwmonGrazvydas Ignotas2-0/+26
Only for cards that are supported by powerplay. Signed-off-by: Grazvydas Ignotas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amd/powerplay: export a function to read fan rpmGrazvydas Ignotas2-0/+19
Powerplay hwmgr already has an implementation, all we need to do is to call it. Signed-off-by: Grazvydas Ignotas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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