aboutsummaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd
AgeCommit message (Collapse)AuthorFilesLines
2021-10-13drm/amdkfd: handle svm partial migration cpages 0Philip Yang1-34/+52
migrate_vma_setup may return cpages 0, means 0 page can be migrated, treat this as error case to skip the rest of vma migration steps. Change svm_migrate_vma_to_vram and svm_migrate_vma_to_ram to return the number of pages migrated successfully or error code. The caller add up all the successful migration pages and update prange->actual_loc only if the total migrated pages is not 0. This also removes the warning message "VRAM BO missing during validation" if migration cpages is 0. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-13drm/amdkfd: ratelimited svm debug messagesPhilip Yang2-21/+30
No function change, use pr_debug_ratelimited to avoid per page debug message overflowing dmesg buf and console log. use dev_err to show error message from unexpected situation, to provide clue to help debug without enabling dynamic debug log. Define dev_fmt to output function name in error message. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-13drm/amd/pm: Fix incorrect power limit readback in smu11 if POWER_SOURCE_DCDarren Powell1-4/+5
when smu->adev->pm.ac_power == 0, message parameter with bit 16 set is saved to smu->current_power_limit. Fixes: 0cb4c62125a9 ("drm/amd/pm: correct power limit setting for SMU V11)" Signed-off-by: Darren Powell <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-13amdgpu/pm: (v2) add limit_type to (pptable_funcs)->set_power_limit signatureDarren Powell8-19/+39
v2 add check for SMU_DEFAULT_PPT_LIMIT v1 modify (pptable_funcs)->set_power_limit signature modify smu11 set_power_limit signature (arcturus, navi10, sienna_cichlid) modify smu13 set_power_limit signature (aldabaran) modify vangogh_set_power_limit signature (vangogh) === Test === sudo bash AMDGPU_PCI_ADDR=`lspci -nn | grep "VGA\|Display" | cut -d " " -f 1` AMDGPU_HWMON=`ls -la /sys/class/hwmon | grep $AMDGPU_PCI_ADDR | awk '{print $9}'` HWMON_DIR=/sys/class/hwmon/${AMDGPU_HWMON} LOGFILE=pp_show_power_cap.log cp $LOGFILE{,.old} lspci -nn | grep "VGA\|Display" > $LOGFILE FILES=" power1_cap power2_cap" for f in $FILES do if test -f "$HWMON_DIR/$f"; then echo === $f === >> $LOGFILE cat $HWMON_DIR/$f >> $LOGFILE RESTORE_VALUE=`cat $HWMON_DIR/$f` 2>&1 >> $LOGFILE echo RESTORE_VALUE $RESTORE_VALUE >> $LOGFILE echo 120000000 > $HWMON_DIR/$f sleep 3 cat $HWMON_DIR/$f >> $LOGFILE echo $RESTORE_VALUE > $HWMON_DIR/$f sleep 3 cat $HWMON_DIR/$f >> $LOGFILE else echo === $f === >> $LOGFILE echo File Not Found >> $LOGFILE fi done cat $LOGFILE Signed-off-by: Darren Powell <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-13drm/amdgpu: Fix RAS page retirement with mode2 reset on AldebaranMukul Joshi1-12/+21
During mode2 reset, the GPU is temporarily removed from the mgpu_info list. As a result, page retirement fails because it cannot find the GPU in the GPU list. To fix this, create our own list of GPUs that support MCE notifier based page retirement and use that list to check if the UMC error occurred on a GPU that supports MCE notifier based page retirement. Signed-off-by: Mukul Joshi <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-13drm/amdgpu: Enable RAS error injection after mode2 reset on AldebaranMukul Joshi1-0/+2
Add the missing call to re-enable RAS error injections on the Aldebaran mode2 reset code path. Signed-off-by: Mukul Joshi <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-13drm/amd/display: fix null pointer deref when plugging in displayAurabindo Pillai1-1/+2
[Why&How] When system boots in headless mode, connecting a 4k display creates a null pointer dereference due to hubp for a certain plane being null. Add a condition to check for null hubp before dereferencing it. Signed-off-by: Aurabindo Pillai <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-13drm/amd/display: Fix surface optimization regression on CarrizoNicholas Kazlauskas1-2/+13
[Why] DCE legacy optimization path isn't well tested under new DC optimization flow which can result in underflow occuring when initializing X11 on Carrizo. [How] Retain the legacy optimization flow for DCE and keep the new one for DCN to satisfy optimizations being correctly applied for ASIC that can support it. Fixes: 34316c1e561db0 ("drm/amd/display: Optimize bandwidth on following fast update") Reported-by: Tom St Denis <[email protected]> Tested-by: Tom St Denis <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-13drm/amd/display: Enable PSR by default on newer DCNNicholas Kazlauskas2-3/+19
[Why] For optimal power savings on panels that can support it. This was previously left disabled by default because of issues with compositors that do not pageflip and scan out directly to the frontbuffer. For these compositors we now have detection methods that wait for x number of pageflips after a full update - triggered by a buffer or format change typically. This may introduce bugs or new cases not tested by users so this is only currently targeting newer DCN. [How] Add code in DM to set PSR state by default for newer DCN while falling back to the feature mask for older. Add a global debug flag that can be set to disable it for either. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-13drm/amdgpu: enable display for cyan skillfishLang Yu1-2/+1
Display support for cyan skillfish is ready now. Enable it! Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-13amd/display: check cursor plane matches underlying planeSimon Ser1-15/+34
The current logic checks whether the cursor plane blending properties match the primary plane's. However that's wrong, because the cursor is painted on all planes underneath. If the cursor is over the primary plane and the overlay plane, it's painted on both pipes. Iterate over the CRTC planes and check their scaling match the cursor's. v4: fix typo in commit message (Harry) Signed-off-by: Simon Ser <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Harry Wentland <[email protected]> Cc: Nicholas Kazlauskas <[email protected]> Cc: Bas Nieuwenhuizen <[email protected]> Cc: Rodrigo Siqueira <[email protected]> Cc: Sean Paul <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-13amd/amdkfd: remove svms declaration to avoid werrorAlex Sierra1-6/+5
svm_range_list svms declaration removed to avoid werror when CONFIG_HSA_AMD_SVM is not enabled. Signed-off-by: Alex Sierra <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-13drm/amdkfd: fix KFDSVMRangeTest.PartialUnmapSysMemTest failsYifan Zhang1-0/+5
[ RUN ] KFDSVMRangeTest.PartialUnmapSysMemTest /home/yifan/brahma/libhsakmt/tests/kfdtest/src/KFDTestUtil.cpp:245: Failure Value of: (hsaKmtAllocMemory(m_Node, m_Size, m_Flags, &m_pBuf)) Actual: 1 Expected: HSAKMT_STATUS_SUCCESS Which is: 0 /home/yifan/brahma/libhsakmt/tests/kfdtest/src/KFDTestUtil.cpp:248: Failure Value of: (hsaKmtMapMemoryToGPUNodes(m_pBuf, m_Size, __null, mapFlags, 1, &m_Node)) Actual: 1 Expected: HSAKMT_STATUS_SUCCESS Which is: 0 /home/yifan/brahma/libhsakmt/tests/kfdtest/src/KFDTestUtil.cpp:306: Failure Expected: ((void *)__null) != (ptr), actual: NULL vs NULL Segmentation fault (core dumped) [ ] Profile: Full Test [ ] HW capabilities: 0x9 kernel log: [ 102.029150] ret_from_fork+0x22/0x30 [ 102.029158] ---[ end trace 15c34e782714f9a3 ]--- [ 3613.603598] amdgpu: Address: 0x7f7149ccc000 already allocated by SVM [ 3613.610620] show_signal_msg: 27 callbacks suppressed These is race with deferred actions from previous memory map changes (e.g. munmap).Flush pending deffered work to avoid such case. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-13drm/amdkfd: export svm_range_list_lock_and_flush_workYifan Zhang2-1/+2
export svm_range_list_lock_and_flush_work to make other kfd parts be able to sync svm_range_list. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-13drm/amdkfd: avoid conflicting address mappingsAlex Sierra2-17/+75
[Why] Avoid conflict with address ranges mapped by SVM mechanism that try to be allocated again through ioctl_alloc in the same process. And viceversa. [How] For ioctl_alloc_memory_of_gpu allocations Check if the address range passed into ioctl memory alloc does not exist already in the kfd_process svms->objects interval tree. For SVM allocations Look for the address range into the interval tree VA from the VM inside of each pdds used in a kfd_process. Signed-off-by: Alex Sierra <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-13drm/amdgpu/nbio2.3: don't use GPU_HDP_FLUSH bit 12Alex Deucher3-1/+36
It's used internally by firmware. Using it in the driver could conflict with firmware. v2: squash in fix for navi1x (Alex) Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-11drm/amdgpu/nbio7.4: don't use GPU_HDP_FLUSH bit 12Alex Deucher1-9/+12
It's used internally by firmware. Using it in the driver could conflict with firmware. Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-11drm/amdgpu: query default sclk from smu for cyan_skillfishLang Yu1-5/+12
Query default sclk instead of hard code. Signed-off-by: Lang Yu <[email protected]> Acked-by: Huang Rui <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-11Merge tag 'drm-misc-next-2021-10-06' of ↵Dave Airlie1-6/+19
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for v5.16: UAPI Changes: - Allow empty drm leases for creating separate GEM namespaces. Cross-subsystem Changes: - Slightly rework dma_buf_poll. - Add dma_resv_for_each_fence_unlocked to iterate, and use it inside the lockless dma-resv functions. Core Changes: - Allow devm_drm_of_get_bridge to build without CONFIG_OF for compile testing. - Add more DP2 headers. - fix CONFIG_FB dependency in fb_helper. - Add DRM_FORMAT_R8 to drm_format_info, and helpers for RGB332 and RGB888. - Fix crash on a 0 or invalid EDID. Driver Changes: - Apply and revert DRM_MODESET_LOCK_ALL_BEGIN. - Add mode_valid to ti-sn65dsi86 bridge. - Support multiple syncobjs in v3d. - Add R8, RGB332 and RGB888 pixel formats to GUD. - Use devm_add_action_or_reset in dw-hdmi-cec. Signed-off-by: Dave Airlie <[email protected]> # gpg: Signature made Wed 06 Oct 2021 20:48:12 AEST # gpg: using RSA key B97BD6A80CAC4981091AE547FE558C72A67013C3 # gpg: Good signature from "Maarten Lankhorst <[email protected]>" [expired] # gpg: aka "Maarten Lankhorst <[email protected]>" [expired] # gpg: aka "Maarten Lankhorst <[email protected]>" [expired] # gpg: Note: This key has expired! # Primary key fingerprint: B97B D6A8 0CAC 4981 091A E547 FE55 8C72 A670 13C3 From: Maarten Lankhorst <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-10-08drm/amd/display: fix duplicated inclusionkernel test robot1-1/+0
Generated by: scripts/checkincludes.pl Reported-by: kernel test robot <[email protected]> Signed-off-by: kernel test robot <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-08drm/amd/display: remove duplicate include in dcn201_clk_mgr.cLv Ruyi1-3/+1
Remove all but the first include of reg_helper.h and core_types.h from dcn201_clk_mgr.c. Reported-by: Zeal Robot <[email protected]> Signed-off-by: Lv Ruyi <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-08drm/amdgpu: use adev_to_drm for consistency when accessing drm_deviceGuchun Chen15-24/+24
adev_to_drm is used everywhere, so improve recent changes when accessing drm_device pointer from amdgpu_device. Signed-off-by: Guchun Chen <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-08drm/amdkfd: rm BO resv on validation to avoid deadlockAlex Sierra1-6/+1
This fix the deadlock with the BO reservations during SVM_BO evictions while allocations in VRAM are concurrently performed. More specific, while the ttm waits for the fence to be signaled (ttm_bo_wait), it already has the BO reserved. In parallel, the restore worker might be running, prefetching memory to VRAM. This also requires to reserve the BO, but blocks the mmap semaphore first. The deadlock happens when the SVM_BO eviction worker kicks in and waits for the mmap semaphore held in restore worker. Preventing signal the fence back, causing the deadlock until the ttm times out. We don't need to hold the BO reservation anymore during validation and mapping. Now the physical addresses are taken from hmm_range_fault. We also take migrate_mutex to prevent range migration while validate_and_map update GPU page table. Signed-off-by: Alex Sierra <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Philip Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-08drm/amd/display: Fix Werror when buildingWayne Lin1-0/+1
[Why & How] Got Werror when building with Clang-13: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dpia.c:195:2: error: variable 'ts' is used uninitialized whenever switch default is taken [-Werror,-Wsometimes-uninitialized] default: ^~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dpia.c:200:9: note: uninitialized use occurs here return ts; ^~ drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_dpia.c:180:2: note: variable 'ts' is declared here enum dpia_set_config_ts ts; ^ 1 error generated. Fix it. Reported-by: Mike Lothian <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-08drm/amdgpu: add missing case for HDP for renoirAlex Deucher1-0/+1
Missing 4.1.2. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-08drm/amd/display: Remove redundant initialization of variable resultColin Ian King1-1/+1
The variable result is being initialized with a value that is never read, it is being updated immediately afterwards in both branches of an if statement. The assignment is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-08drm/amdgpu/discovery: add missing case for SMU 11.0.5Alex Deucher1-0/+1
Was missed when converting the driver over to IP based initialization. Tested-by: Harry Wentland <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-07drm/amdgpu: unify BO evicting method in amdgpu_ttmNirmoy Das6-35/+58
Unify BO evicting functionality for possible memory types in amdgpu_ttm.c. Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-06drm/amd/display: Fix detection of 4 lane for DPALTHansen2-1/+35
[Why] DPALT detection for B0 PHY has its own set of RDPCSPIPE registers [How] Use RDPCSPIPE registers to detect if DPALT lane is 4 lane Reviewed-by: Charlene Liu <[email protected]> Acked-by: Solomon Chiu <[email protected]> Signed-off-by: Hansen <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2021-10-06drm/amd/display: Limit display scaling to up to 4k for DCN 3.1Nikola Cornij1-1/+1
[why] The existing limit was mistakenly bigger than 4k for DCN 3.1 Reviewed-by: Zhan Liu <[email protected]> Acked-by: Solomon Chiu <[email protected]> Signed-off-by: Nikola Cornij <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2021-10-06drm/amd/display: Skip override for preferred link settings during link trainingGeorge Shen1-6/+0
[Why] Overriding link setting inside override_training_settings result in fallback link settings being ignored. This can potentially cause link training to always fail and consequently result in an infinite loop of link training to occur in dp_verify_link_cap during detection. [How] Since preferred link settings are already considered inside decide_link_settings, skip the check in override_training_settings to avoid infinite link training loops. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Solomon Chiu <[email protected]> Signed-off-by: George Shen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-06drm/amd/display: Add 120Hz support for freesync video modeSolomon Chiu1-11/+11
[Why] For those video format with 60 fps, the user space player could ask for 120Hz for playback. [How] Add 120 in the table of common rates. Signed-off-by: Solomon Chiu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-06drm/amdgpu: Register MCE notifier for Aldebaran RASMukul Joshi1-0/+141
On Aldebaran, GPU driver will handle bad page retirement for GPU memory even though UMC is host managed. As a result, register a bad page retirement handler on the mce notifier chain to retire bad pages on Aldebaran. Signed-off-by: Mukul Joshi <[email protected]> Reviewed-by: Yazen Ghannam <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-06drm/amdgpu: return early if debugfs is not initializedNirmoy Das1-0/+3
Check first if debugfs is initialized before creating amdgpu debugfs files. References: https://gitlab.freedesktop.org/drm/amd/-/issues/1686 Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-06drm/amd/display: USB4 bring up set correct addressJude Shih1-1/+1
[Why] YELLOW_CARP_B0 address was not correct [How] Set YELLOW_CARP_B0 to 0x1A. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Wayne Lin <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Jude Shih <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-06drm/amd/display: Fix USB4 Aux via DMUB terminate unexpectedlyJude Shih1-1/+2
[Why] Condition variable sometimes terminated unexpectedly [How] Use wait_for_completion_timeout to avoid unexpected termination of CV Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Wayne Lin <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Jude Shih <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-06drm/amd/display: Deadlock/HPD Status/Crash Bug FixJude Shih1-26/+44
[why] 1. HPD callback function has deadlock problem 2. HPD status is not assigned 3. There is crash due to null pointer 4. link_enc is NULL in DPIA case [How] 1. Fix deadlock problem by moving it out of the drm_modeset_lock 2. Assign HPD status from the notify of outbox from dmub FW 3. Fix the crash by checking if pin or enc exists 4. Use link_enc_cfg_get_link_enc_used_by_link to dynamically assign Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Wayne Lin <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Jude Shih <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-06drm/amd/display: Fix for access for ddc pin and aux engine.Meenakshikumar Somasundaram4-10/+10
[Why & How] 1. Remove unnecessary dummy interrupt source for USB4 HPD & HPD RX 2. Adjust parameter for DPCD writing of link training process of DPIA link 3. Adjust specific AUX defer delay for DPIA link Reviewed-by: Jimmy Kizito <[email protected]> Acked-by: Wayne Lin <[email protected]> Acked-by: Nicholas Kazlauskas <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Meenakshikumar Somasundaram <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-06drm/amd/display: Add debug flags for USB4 DP link training.Jimmy Kizito4-1/+18
[Why & How] Additional debug flags that can be useful for testing USB4 DP link training. Add flags: - 0x2 : Forces USB4 DP link to non-LTTPR mode - 0x4 : Extends status read intervals to about 60s. Reviewed-by: Meenakshikumar Somasundaram <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Wayne Lin <[email protected]> Acked-by: Nicholas Kazlauskas <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Jimmy Kizito <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-06drm/amd/display: Fix DIG_HPD_SELECT for USB4 display endpoints.Jimmy Kizito1-3/+9
[Why] DIB_BE_CNTL<i>.DIG_HPD_SELECT selects the HPD block being used by the display endpoint assigned to DIG<i>. In the case of USB4 display endpoints, no physical HPD block is assigned. [How] Setting DIB_BE_CNTL<i>.DIG_HPD_SELECT to 5 indicates that no HPD is assigned to a display endpoint. Firmware decrements the HPD_SELECT value by 1 before writing it to the register. Reviewed-by: Meenakshikumar Somasundaram <[email protected]> Acked-by: Wayne Lin <[email protected]> Acked-by: Nicholas Kazlauskas <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Jimmy Kizito <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-06drm/amd/display: Support for SET_CONFIG processing with DMUBJude Shih5-20/+94
[Why] To process SET_CONFIG transactions with DMUB using inbox1 and outbox1 mail boxes. [How] 1) DMUB posts SET_CONFIG reply as an Outbox1 message of type DMUB_OUT_CMD__SET_CONFIG_REPLY. 2) The dmub async to sync mechanism for AUX is modified to accommodate SET_CONFIG commands for both command issue and reply code paths. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Wayne Lin <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Jude Shih <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-06drm/amd/display: Add dpia debug optionsMeenakshikumar Somasundaram5-3/+14
[Why & How] To add support for dpia debug options. Reviewed-by: Jimmy Kizito <[email protected]> Acked-by: Wayne Lin <[email protected]> Acked-by: Nicholas Kazlauskas <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Meenakshikumar Somasundaram <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-06drm/amd/display: Read USB4 DP tunneling data from DPCD.Jimmy Kizito4-2/+67
[Why] We requires information from DPCD in order to identify USB4 DP tunneling targets. [How] Add USB4 DP tunneling fields to DPCD struct and populate these fields during sink detection. Reviewed-by: Jun Lei <[email protected]> Acked-by: Wayne Lin <[email protected]> Acked-by: Nicholas Kazlauskas <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Jimmy Kizito <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-06drm/amd/display: Support for SET_CONFIG processing with DMUBMeenakshikumar Somasundaram8-4/+149
[Why] To process SET_CONFIG transactions with DMUB using inbox1 and outbox1 mail boxes. [How] 1) Added inbox1 DPIA command subtype DMUB_CMD__DPIA_SET_CONFIG_ACCESS to issue SET_CONFIG command to DMUB in dc_process_dmub_set_config_async(). DMUB processes the command with DPIA sends reply back immediately or in an outbox1 message triggering an outbox1 interrupt to driver. 2) DMUB posts SET_CONFIG reply as an Outbox1 message of type DMUB_OUT_CMD__SET_CONFIG_REPLY. 3) The dmub async to sync mechanism for AUX is modified to accommodate SET_CONFIG commands for both command issue and reply code paths. Reviewed-by: Jun Lei <[email protected]> Acked-by: Wayne Lin <[email protected]> Acked-by: Nicholas Kazlauskas <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Meenakshikumar Somasundaram <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-06drm/amd/display: Implement end of training for hop in DPIA display pathJimmy Kizito2-5/+83
[Why & How] Clear training pattern sequence for hop in display path once clock recovery and equalization phases of DP tunnel link training completed. Reviewed-by: Jun Lei <[email protected]> Acked-by: Wayne Lin <[email protected]> Acked-by: Nicholas Kazlauskas <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Jimmy Kizito <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-06drm/amd/display: Implement DPIA equalisation phaseJimmy Kizito1-3/+246
[Why] Equalisation is the mandatory second phase of DisplayPort link training over a USB4 DP tunnel. [How] Implement equalisation phase for DP tunneled over USB4 in DPIA training module. Reviewed-by: Jun Lei <[email protected]> Acked-by: Wayne Lin <[email protected]> Acked-by: Nicholas Kazlauskas <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Jimmy Kizito <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-06drm/amd/display: Implement DPIA clock recovery phaseJimmy Kizito2-7/+457
[Why] Clock recovery is the mandatory first phase of DP link training. [How] - Implement clock recovery phase in DPIA training module. - Add helper functions for building SET_CONFIG messages. Reviewed-by: Jun Lei <[email protected]> Acked-by: Wayne Lin <[email protected]> Acked-by: Nicholas Kazlauskas <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Jimmy Kizito <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-06drm/amd/display: Implement DPIA link configurationJimmy Kizito2-6/+45
[Why] Training settings need to be applied to DPIA link at start of each training loop. Note: FEC readiness should be configured before link training while FEC enablement should be configured once training is complete. [How] - Implement DPIA link configuration function. - Account for dynamically assigned link encoders during link configuration. Reviewed-by: Jun Lei <[email protected]> Acked-by: Wayne Lin <[email protected]> Acked-by: Nicholas Kazlauskas <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Jimmy Kizito <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-06drm/amd/display: Implement DPIA training loopJimmy Kizito4-17/+120
[Why] Training of DPIA link differs enough from that of conventional DP link to warrant a separate implementation. [How] - Implement top-level of DPIA training loop. - Make functions shared between DP and DPIA link training "public". Reviewed-by: Jun Lei <[email protected]> Acked-by: Wayne Lin <[email protected]> Acked-by: Nicholas Kazlauskas <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Jimmy Kizito <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-06drm/amd/display: Train DPIA links with fallbackJimmy Kizito2-2/+8
[Why & How] Conventional links are trained with fallback during sink detection. Have DPIA links trained with fallback too. Reviewed-by: Jun Lei <[email protected]> Acked-by: Wayne Lin <[email protected]> Acked-by: Nicholas Kazlauskas <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Jimmy Kizito <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.