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2021-11-03drm/amd/pm: Add missing mutex for pp_get_power_profile_modeMario Limonciello1-1/+5
Prevent possible issues from set and get being called simultaneously. Signed-off-by: Mario Limonciello <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-11-03drm/amdgpu/pm: drop pp_power_profile_mode support for yellow carpMario Limonciello2-89/+2
This was added by commit bd8dcea93a7d ("drm/amd/pm: add callbacks to read/write sysfs file pp_power_profile_mode") but the feature was deprecated from PMFW. Remove it from the driver. Signed-off-by: Mario Limonciello <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-11-03drm/amdkfd: update gfx target version for RenoirGraham Sider1-1/+1
Previously Renoir compiler gfx target version was forced to Raven. Update driver side for completeness. Signed-off-by: Graham Sider <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-11-03drm/amdgpu: Convert SMU version to decimal in debugfsMario Limonciello1-2/+7
This is more useful when talking to the SMU team to have the information in this format, save one less step to manually do it. Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-11-03drm/amdkfd: Handle incomplete migration to system memoryFelix Kuehling2-13/+40
If some pages fail to migrate to system memory, don't update prange->actual_loc = 0. This prevents endless CPU page faults after partial migration failures due to contested page locks. Migration to RAM must be complete during migrations from VRAM to VRAM and during evictions. Implement retry and fail if the migration to RAM fails. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Philip Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-11-03drm/amdkfd: Avoid thrashing of stack and heapFelix Kuehling1-5/+17
Stack and heap pages tend to be shared by many small allocations. Concurrent access by CPU and GPU is therefore likely, which can lead to thrashing. Avoid this by setting the preferred location to system memory. Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Philip Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-11-03drm/amdkfd: Fix SVM_ATTR_PREFERRED_LOCFelix Kuehling1-3/+11
The preferred location should be used as the migration destination whenever it is accessible by the faulting GPU. System memory is always accessible. Peer memory is accessible if it's in the same XGMI hive. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Philip Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-11-03drm/amdgpu: use correct register mask to extract fieldOak Zeng1-5/+13
Aldebaran has different register mask definitions for regiter MC_VM_XGMI_LFB_CNTL. Use the correct masks to interpret fields of this register. Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-11-03drm/amd/amdgpu: fix bad job hw_fence use after free in advance tdrJingwen Chen1-0/+4
[Why] In advance tdr mode, the real bad job will be resubmitted twice, while in drm_sched_resubmit_jobs_ext, there's a dma_fence_put, so the bad job is put one more time than other jobs. [How] Adding dma_fence_get before resbumit job in amdgpu_device_recheck_guilty_jobs and put the fence for normal jobs Signed-off-by: Jingwen Chen <[email protected]> Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-11-02Merge tag 'drm-next-2021-11-03' of git://anongit.freedesktop.org/drm/drmLinus Torvalds362-6622/+53772
Pull drm updates from Dave Airlie: "Summary below. i915 starts to add support for DG2 GPUs, enables DG1 and ADL-S support by default, lots of work to enable DisplayPort 2.0 across drivers. Lots of documentation updates and fixes across the board. core: - improve dma_fence, lease and resv documentation - shmem-helpers: allocate WC pages on x86, use vmf_insert_pin - sched fixes/improvements - allow empty drm leases - add dma resv iterator - add more DP 2.0 headers - DP MST helper improvements for DP2.0 dma-buf: - avoid warnings, remove fence trace macros bridge: - new helper to get rid of panels - probe improvements for it66121 - enable DSI EOTP for anx7625 fbdev: - efifb: release runtime PM on destroy ttm: - kerneldoc switch - helper to clear all DMA mappings - pool shrinker optimizaton - remove ttm_tt_destroy_common - update ttm_move_memcpy for async use panel: - add new panel-edp driver amdgpu: - Initial DP 2.0 support - Initial USB4 DP tunnelling support - Aldebaran MCE support - Modifier support for DCC image stores for GFX 10.3 - Display rework for better FP code handling - Yellow Carp/Cyan Skillfish updates - Cyan Skillfish display support - convert vega/navi to IP discovery asic enumeration - validate IP discovery table - RAS improvements - Lots of fixes i915: - DG1 PCI IDs + LMEM discovery/placement - DG1 GuC submission by default - ADL-S PCI IDs updated + enabled by default - ADL-P (XE_LPD) fixed and updates - DG2 display fixes - PXP protected object support for Gen12 integrated - expose multi-LRC submission interface for GuC - export logical engine instance to user - Disable engine bonding on Gen12+ - PSR cleanup - PSR2 selective fetch by default - DP 2.0 prep work - VESA vendor block + MSO use of it - FBC refactor - try again to fix fast-narrow vs slow-wide eDP training - use THP when IOMMU enabled - LMEM backup/restore for suspend/resume - locking simplification - GuC major reworking - async flip VT-D workaround changes - DP link training improvements - misc display refactorings bochs: - new PCI ID rcar-du: - Non-contiguious buffer import support for rcar-du - r8a779a0 support prep omapdrm: - COMPILE_TEST fixes sti: - COMPILE_TEST fixes msm: - fence ordering improvements - eDP support in DP sub-driver - dpu irq handling cleanup - CRC support for making igt happy - NO_CONNECTOR bridge support - dsi: 14nm phy support for msm8953 - mdp5: msm8x53, sdm450, sdm632 support stm: - layer alpha + zpo support v3d: - fix Vulkan CTS failure - support multiple sync objects gud: - add R8/RGB332/RGB888 pixel formats vc4: - convert to new bridge helpers vgem: - use shmem helpers virtio: - support mapping exported vram zte: - remove obsolete driver rockchip: - use bridge attach no connector for LVDS/RGB" * tag 'drm-next-2021-11-03' of git://anongit.freedesktop.org/drm/drm: (1259 commits) drm/amdgpu/gmc6: fix DMA mask from 44 to 40 bits drm/amd/display: MST support for DPIA drm/amdgpu: Fix even more out of bound writes from debugfs drm/amdgpu/discovery: add SDMA IP instance info for soc15 parts drm/amdgpu/discovery: add UVD/VCN IP instance info for soc15 parts drm/amdgpu/UAPI: rearrange header to better align related items drm/amd/display: Enable dpia in dmub only for DCN31 B0 drm/amd/display: Fix USB4 hot plug crash issue drm/amd/display: Fix deadlock when falling back to v2 from v3 drm/amd/display: Fallback to clocks which meet requested voltage on DCN31 drm/amd/display: move FPU associated DCN301 code to DML folder drm/amd/display: fix link training regression for 1 or 2 lane drm/amd/display: add two lane settings training options drm/amd/display: decouple hw_lane_settings from dpcd_lane_settings drm/amd/display: implement decide lane settings drm/amd/display: adopt DP2.0 LT SCR revision 8 drm/amd/display: FEC configuration for dpia links in MST mode drm/amd/display: FEC configuration for dpia links drm/amd/display: Add workaround flag for EDID read on certain docks drm/amd/display: Set phy_mux_sel bit in dmub scratch register ...
2021-11-01Merge tag 'x86_cc_for_v5.16_rc1' of ↵Linus Torvalds1-1/+3
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull generic confidential computing updates from Borislav Petkov: "Add an interface called cc_platform_has() which is supposed to be used by confidential computing solutions to query different aspects of the system. The intent behind it is to unify testing of such aspects instead of having each confidential computing solution add its own set of tests to code paths in the kernel, leading to an unwieldy mess" * tag 'x86_cc_for_v5.16_rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: treewide: Replace the use of mem_encrypt_active() with cc_platform_has() x86/sev: Replace occurrences of sev_es_active() with cc_platform_has() x86/sev: Replace occurrences of sev_active() with cc_platform_has() x86/sme: Replace occurrences of sme_active() with cc_platform_has() powerpc/pseries/svm: Add a powerpc version of cc_platform_has() x86/sev: Add an x86 version of cc_platform_has() arch/cc: Introduce a function to check for confidential computing features x86/ioremap: Selectively build arch override encryption functions
2021-10-28drm/amdgpu/gmc6: fix DMA mask from 44 to 40 bitsAlex Deucher1-2/+2
The DMA mask on SI parts is 40 bits not 44. Copy paste typo. Fixes: 244511f386ccb9 ("drm/amdgpu: simplify and cleanup setting the dma mask") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1762 Acked-by: Christian König <[email protected]> Tested-by: Paul Menzel <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: MST support for DPIAMeenakshikumar Somasundaram4-0/+111
[Why] - DPIA MST slot registers are not programmed during payload allocation and hence MST does not work with DPIA. - HPD RX interrupts are not handled for DPIA. [How] - Added inbox command to program the MST slots whenever payload allocation happens for DPIA links. - Added support for handling HPD RX interrupts Signed-off-by: Meenakshikumar Somasundaram <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amdgpu: Fix even more out of bound writes from debugfsPatrik Jakobsson1-9/+9
CVE-2021-42327 was fixed by: commit f23750b5b3d98653b31d4469592935ef6364ad67 Author: Thelford Williams <[email protected]> Date: Wed Oct 13 16:04:13 2021 -0400 drm/amdgpu: fix out of bounds write but amdgpu_dm_debugfs.c contains more of the same issue so fix the remaining ones. v2: * Add missing fix in dp_max_bpc_write (Harry Wentland) Fixes: 918698d5c2b5 ("drm/amd/display: Return the number of bytes parsed than allocated") Signed-off-by: Patrik Jakobsson <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amdgpu/discovery: add SDMA IP instance info for soc15 partsAlex Deucher1-0/+14
Add secondary instance version info for soc15 parts. Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amdgpu/discovery: add UVD/VCN IP instance info for soc15 partsAlex Deucher1-0/+3
Add secondary instance version info for vega20, arcturure, and aldebaran. Acked-by: Christian König <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: Enable dpia in dmub only for DCN31 B0Jude Shih3-0/+16
[Why] DMUB binary is common for both A0 and B0. Hence, driver should notify FW about the support for DPIA in B0. [How] Added dpia_supported bit in dmub_fw_boot_options and will be set only for B0. Assign dpia_supported to true before dm_dmub_hw_init in B0 case. v2: fix build without CONFIG_DRM_AMD_DC_DCN (Alex) Signed-off-by: Jude Shih <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: Fix USB4 hot plug crash issueJude Shih1-7/+16
[Why] Notify data from outbox corrupt, the notify type should be 2 (HPD) instead of 0 (No data). We copied the address instead of the value. The memory might be freed in the end of outbox IRQ [How] We should allocate the memory of notify and copy the whole content from outbox to hpd handle function Fixes: 88f52b1fff891e ("drm/amd/display: Support for SET_CONFIG processing with DMUB") Signed-off-by: Jude Shih <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: Fix deadlock when falling back to v2 from v3Nicholas Kazlauskas1-4/+2
[Why] A deadlock in the kernel occurs when we fallback from the V3 to V2 add_topology_to_display or remove_topology_to_display because they both try to acquire the dtm_mutex but recursive locking isn't supported on mutex_lock(). [How] Make the mutex_lock/unlock more fine grained and move them up such that they're only required for the psp invocation itself. Fixes: bf62221e9d0e ("drm/amd/display: Add DCN3.1 HDCP support") Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: Fallback to clocks which meet requested voltage on DCN31Michael Strauss1-3/+10
[WHY] On certain configs, SMU clock table voltages don't match which cause parser to behave incorrectly by leaving dcfclk and socclk table entries unpopulated. [HOW] Currently the function that finds the corresponding clock for a given voltage only checks for exact voltage level matches. In the case that no match gets found, parser now falls back to searching for the max clock which meets the requested voltage (i.e. its corresponding voltage is below requested). Signed-off-by: Michael Strauss <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: move FPU associated DCN301 code to DML folderQingqing Zhuo7-365/+450
[Why & How] As part of the FPU isolation work documented in https://patchwork.freedesktop.org/series/93042/, isolate code that uses FPU in DCN301 to DML, where all FPU code should locate. Cc: Christian König <[email protected]> Cc: Harry Wentland <[email protected]> Cc: Rodrigo Siqueira <[email protected]> Tested-by: Zhan Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: fix link training regression for 1 or 2 laneWenjing Liu1-3/+32
[why] We have a regression that cause maximize lane settings to use uninitialized data from unused lanes. This will cause link training to fail for 1 or 2 lanes because the lane adjust is populated incorrectly sometimes. v2: fix build without CONFIG_DRM_AMD_DC_DCN (Alex) Reviewed-by: Eric Yang <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: add two lane settings training optionsWenjing Liu2-2/+13
[why] option 1: disallow different lanes to have different lane settings option 2: dpcd lane settings will always use the same hw lane settings even if it doesn't match requested lane adjust Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: decouple hw_lane_settings from dpcd_lane_settingsWenjing Liu4-106/+63
[why] As DP features expands, we have encountered many situations where we must configure a different DPCD lane setting from hw lane settings we output. The change is to decouple hw lane settings from dpcd lane settings to provide flexibility to configure dpcd and hw individually. Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: implement decide lane settingsWenjing Liu4-232/+155
[why] Decouple lane settings decision logic all to its own function. The function takes in lane adjust array and link training settings and decide what hw lane setting and dpcd lane setting should be used. Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: adopt DP2.0 LT SCR revision 8Wenjing Liu1-8/+13
[how] revision 8 SCR requires DP Source to write TPS2 and FFE lane adjustment in one 5 byte write aux transaction. It specifies to read aux rd interval value as soon as we turn on TPS1 pattern. Cc: Wayne Lin <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: FEC configuration for dpia links in MST modeMeenakshikumar Somasundaram1-1/+1
[Why] To fix the check condition for fec enable for dpia links in MST mode. [How] dc_link_should_enable_fec() to be used to check whether fec should be enabled in MST mode. Cc: Wayne Lin <[email protected]> Reviewed-by: Jimmy Kizito <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Meenakshikumar Somasundaram <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: FEC configuration for dpia linksMeenakshikumar Somasundaram1-1/+1
[Why] To fix the check condition for fec enable for dpia links. [How] dc_link_should_enable_fec() to be used to check whether fec should be enabled. Cc: Wayne Lin <[email protected]> Reviewed-by: Jimmy Kizito <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Meenakshikumar Somasundaram <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: Add workaround flag for EDID read on certain docksJimmy Kizito2-0/+4
[Why] Certain docks appear to NAK I2C writes to the segment pointer with the MOT (middle of transaction) bit clear. This behaviour can cause EDID reads from higher segments to fail. [How] Add workaround flag for links which connect to docks exhibiting this issue. Cc: Wayne Lin <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Jimmy Kizito <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: Set phy_mux_sel bit in dmub scratch registerHansen5-3/+9
[Why] B0 has pipe mux for DIGC and DIGD which can be connected to PHYF/PHYG or PHYC/PHY D. [How] Based on chip internal hardware revision id determine it is B0 and set DMUB scratch register so DMUBFW can connect the display pipe is connected correctly to the dig. Cc: Wayne Lin <[email protected]> Cc: Nicholas Kazlauskas <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Hansen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: Manually adjust strobe for DCN303Martin Leung1-0/+14
why: DCN303's 4 channel SOC BB causes problems at strobe how: workaround to manually adjust strobe calculation using FCLK restrict. Reviewed-by: Jun Lei <[email protected]> Acked-by: Agustin Gutierrez <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Martin Leung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: 3.2.159Aric Cyr1-1/+1
This new DC version brings improvements in the following areas: - Improvements for USB4; - Isolate FPU code for DCN20, DCN301, and DSC; - Fixes on Linking training; - Refactoring some parts of the code, such as PSR; Acked-by: Agustin Gutierrez <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: [FW Promotion] Release 0.0.90Anthony Koo1-2/+2
Acked-by: Agustin Gutierrez <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Anthony Koo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: Remove unused macrosAnson Jacob3-8/+0
fixed16_to_double & fixed16_to_double_to_cpu are not used. Reviewed-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Acked-by: Agustin Gutierrez <[email protected]> Signed-off-by: Anson Jacob <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: allow windowed mpo + odmDmytro Laktyushkin3-17/+28
This change adds a config flag to allow non fullscreen MPO during ODM. Scaling calculation will still fail configurations where video is only one one side of the screen. Reviewed-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Acked-by: Agustin Gutierrez <[email protected]> Signed-off-by: Dmytro Laktyushkin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: set Layout properly for 8ch audio at timing validationGuo, Bing1-2/+4
Why: For audio packet type 0x02, there are 2 Layouts: Layout = 0 for 2 channels and Layout = 1 for > 2 channels. Layout will affect bandwidth check. Currently, for HDMI FRL, Layout field isn't set and has a default value of 0, so theoretically only 2-channel audio for audio packet type 0x02 is supported now. How: 1. Set Layout properly according to maximum audio channel numbers for audios with audio packet type 0x02. 2. 8ch LPCM audio is not supported for timing modes with v_active <= 576. Reviewed-by: Chris Park <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Acked-by: Agustin Gutierrez <[email protected]> Signed-off-by: Bing Guo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: Fix 3DLUT skipped programmingAric Cyr2-0/+5
We found a compilation error that we thought was caused by the 3DLUT patch; later on, we figured out the root cause of the problem, but we already applied the revert in the wrong patch. This commit brings it back the 3DLUT fix. Acked-by: Agustin Gutierrez <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: 3.2.158Aric Cyr1-1/+1
Acked-by: Agustin Gutierrez <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: [FW Promotion] Release 0.0.89Anthony Koo1-3/+6
- Add flag to control root clock gating in init_hw - Add flag to indicate a diags environment is being used Acked-by: Agustin Gutierrez <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Anthony Koo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: Handle I2C-over-AUX write channel status updateAric Cyr4-10/+44
[Why] When writing long AUX commands some sinks will respond will write status update requiring source to read status. [How] When a write request is replied with data (AUX_ACK_M), retry a read of write status to determine when the write is completed. Reviewed-by: Martin Leung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Acked-by: Agustin Gutierrez <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: Add comment for preferred_training_settingsGeorge Shen1-0/+4
[Why] Currently the naming of preferred_training_settings is ambiguous and has caused confusion regarding its purpose and usage. [How] Add comment to clarify the intention. Reviewed-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Acked-by: Agustin Gutierrez <[email protected]> Signed-off-by: George Shen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: Implement fixed DP drive settingsGeorge Shen6-1/+27
[Why] Currently there are use cases that require DP link to maintain fixed VS and PE in HW regardless of what the sink requests. BIOS integrated info table will specify whether we need to use the fixed drive settings, and the drive settings to use. [How] Implement changes to parse the integrated info table and set the fixed drive settings accordingly. Reviewed-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Acked-by: Agustin Gutierrez <[email protected]> Signed-off-by: George Shen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: restyle dcn31 resource header inline with other asicsDmytro Laktyushkin2-2/+12
Style change for better consistency across codebase Reviewed-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Acked-by: Agustin Gutierrez <[email protected]> Signed-off-by: Dmytro Laktyushkin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: clean up dcn31 revision checkDmytro Laktyushkin1-8/+2
This is unnecessary in clk_mgr Reviewed-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Acked-by: Agustin Gutierrez <[email protected]> Signed-off-by: Dmytro Laktyushkin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: Defer GAMCOR and DSCL power down sequence to vupdateMichael Strauss6-6/+38
[WHY] Every other CM LUT power down sequence is deferred to next vupdate as memory powerdown updates immediately while selecting LUTs is double buffered. Previous update to defer LUT power down missed GAMCOR and DSCL, causing some visible flicker when entering/exiting fullscreen video playback. [HOW] Update dpp deferred update loop to check for valid DPPs in res_pool instead of referencing dcn_ip which turns out to not be populated during runtime. Move GAMCOR and DSCL powerdown to dpp deferred updates. Reviewed-by: Haonan Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Acked-by: Agustin Gutierrez <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: Set i2c memory to light sleep during hw initMichael Strauss3-2/+9
[WHY] i2c memory doesn't get set to light sleep on hw init as intended [HOW] Set i2c to light sleep after reg gets zeroed, ensuring memory power control doesn't get disabled for any other DIO memory Reviewed-by: Haonan Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Acked-by: Agustin Gutierrez <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: fix a crash on USB4 over C20 PHYAhmad Othman1-5/+20
[Why] Crash when USB4 is connected. [How] Added an ASIC specific code guard. Reviewed-by: Nikola Cornij <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Acked-by: Agustin Gutierrez <[email protected]> Signed-off-by: Ahmad Othman <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: move FPU associated DSC code to DML folderQingqing Zhuo8-338/+389
[Why & How] As part of the FPU isolation work documented in https://patchwork.freedesktop.org/series/93042/, isolate code that uses FPU in DSC to DML, where all FPU code should locate. This change does not refactor any functions but move code around. Cc: Christian König <[email protected]> Cc: Hersen Wu <[email protected]> Cc: Anson Jacob <[email protected]> Cc: Harry Wentland <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Agustin Gutierrez <[email protected]> Tested-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: Add support for USB4 on C20 PHY for DCN3.1Ahmad Othman4-6/+64
[Why] Created new fields that matches new B0 structs On DCN31 the mapping of DIO output to PHY differs from A0 to B0 boards with new PHY C20 & this new mapping needed to be handled. [How] Mapped new structure based on new structs Added logic for mapping over A0 and B0 boards Hooked all new structs together. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Agustin Gutierrez <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Ahmad Othman <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-10-28drm/amd/display: dc_link_set_psr_allow_active refactoringRobin Chen10-23/+125
[Why] To expose new power optimization flags to PSR interface. It allows the PSR related power features can be enabled separately base on different use scenarios. Reviewed-by: Anthony Koo <[email protected]> Acked-by: Agustin Gutierrez <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Robin Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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