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path: root/drivers/gpu/drm/amd
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2019-10-03drm/amdkfd: Use better name for sdma queue non HWS pathYong Zhao5-190/+196
The old name is prone to confusion. The register offset is for a RLC queue rather than a SDMA engine. The value is not a base address, but a register offset. Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdkfd: Delete useless SDMA register setting on non HWS pathYong Zhao5-71/+3
HW folks have confirm that we should not touch RESUME_CTX of SDMA*_GFX_CONTEXT_CNTL when manipulating RLC queues. Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amd/display: prevent memory leakNavid Emamdoost5-0/+5
In dcn*_create_resource_pool the allocated memory should be released if construct pool fails. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Navid Emamdoost <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdkfd: Add NAVI12 support from kfd sideshaoyunl1-0/+19
Add device info for both navi12 PF and VF Signed-off-by: shaoyunl <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: restrict hotplug error messageChristian König1-1/+4
We should print the error only when we are hotplugged and crash basically all userspace applications. Signed-off-by: Christian König <[email protected]> Reviewed-by: Emily Deng <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: once more fix amdgpu_bo_create_kernel_atChristian König1-3/+6
When CPU access is needed we should tell that to amdgpu_bo_create_reserved() or otherwise the access is denied later on. Signed-off-by: Christian König <[email protected]> Reviewed-by: Emily Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amd/powerplay: update arcturus smu-driver interaction headerEvan Quan2-8/+9
To pair the latest SMU firmware. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: add comments in ras interrupt callbackTao Zhou3-1/+14
add comments to clarify why checking GFX IP BLOCK for each ras interrupt callback Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: implement common gmc_ras_late_initTao Zhou3-21/+21
common gmc_ecc_late_init can be shared among all generations of gmc v2: rename gmc_ecc_late_init to gmc_ras_late_init Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: move xgmi ras fini to xgmi blockTao Zhou3-11/+17
it's more suitable to put xgmi ras fini in xgmi block Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: move mmhub ras fini to mmhub blockTao Zhou3-12/+16
it's more suitable to put mmhub ras fini in mmhub block Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: move umc ras fini to umc blockTao Zhou3-11/+17
it's more suitable to put umc ras fini in umc block Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: add ras fini for xgmiTao Zhou1-0/+11
add ras fini for xgmi to cleanup xgmi ras framework Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: add ras fini for nbioTao Zhou3-1/+16
add a common nbio ras fini implementation to cleanup nbio ras framework Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: simplify the access to eeprom_control structTao Zhou1-3/+3
simplify the code of accessing to eeprom_control struct Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: remove ih_info parameter of gfx_ras_late_initTao Zhou3-15/+9
gfx_ras_late_init can get the info by itself Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: remove ih_info parameter of umc_ras_late_initTao Zhou3-14/+10
umc_ras_late_init can get the info by itself Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: add common sdma_ras_fini functionTao Zhou3-15/+21
sdma_ras_fini can be shared among all generations of sdma Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: add common gfx_ras_fini functionTao Zhou3-13/+17
gfx_ras_fini can be shared among all generations of gfx Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: add common gmc_ras_fini functionTao Zhou3-27/+28
gmc_ras_fini can be shared among all generations of gmc Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: move mmhub_ras_if from gmc to mmhub blockTao Zhou3-15/+14
mmhub_ras_if is relevant to mmhub Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: replace mmhub_funcs with mmhub.funcsTao Zhou3-6/+5
remove mmhub_funcs in adev Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: add common mmhub member for adevTao Zhou2-0/+8
put mmhub_funcs and ras_if pointer into mmhub struct Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: move umc_ras_if from gmc to umc blockTao Zhou4-17/+17
umc_ras_if is relevant to umc Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: refine sdma4 ras_data_cbTao Zhou1-17/+7
simplify code logic and refine return value v2: remove unused error source code Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: move sdma ecc functions to generic sdma fileTao Zhou3-22/+36
sdma ras ecc functions can be reused among all sdma generations Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: move gfx ecc functions to generic gfx fileTao Zhou3-39/+41
gfx ras ecc common functions could be reused among all gfx generations Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: move umc ras irq functions to umc blockTao Zhou3-67/+72
move umc ras irq functions from gmc v9 to generic umc block, these functions are relevant to umc and they can be shared among all generations of umc Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: update parameter of ras_ih_cbTao Zhou4-7/+9
change struct ras_err_data *err_data to void *err_data, align with umc code and the callback's declaration in each ras block could pay no attention to the structure type Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: fix an UMC hw arbitrator bug(v3)Monk Liu5-1/+77
issue: the UMC6 h/w bug is that when MCLK is doing the switch in the middle of a page access being preempted by high priority client (e.g. DISPLAY) then UMC and the mclk switch would stuck there due to deadlock how: fixed by disabling auto PreChg for UMC to avoid high priority client preempting other client's access on the same page, thus the deadlock could be avoided v2: put the patch in callback of UMC6 v3: rename the callback to "init_registers" Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: remove gfx9 NGGMarek Olšák5-277/+0
Never used. Signed-off-by: Marek Olšák <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu/atomfirmware: simplify the interface to get vram infoAlex Deucher4-71/+37
fetch both the vram type and width in one function call. This avoids having to parse the same data table twice to get the two pieces of data. Reviewed-by: Xiaojie Yuan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu/atomfirmware: use proper index for querying vram type (v3)Alex Deucher1-70/+88
The index is stored in scratch register 4 after asic init. Use that index. No functional change since all asics in a family use the same type of vram (G5, G6, HBM) and that is all we use at the monent, but if we ever need to query other info, we will now have the proper index. v2: module array is variable sized, handle that. v3: fix off by one in array handling Reviewed-by: Xiaojie Yuan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu/display: include slab.h in dcn21_resource.cAlex Deucher1-0/+2
It's apparently needed in some configurations. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu/psp: silence response status warningShirish S1-1/+1
log the response status related error to the driver's debug log since psp response status is not 0 even though there was no problem while the command was submitted. This warning misleads, hence this change. Signed-off-by: Shirish S <[email protected]> Acked-by: Huang Rui <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amd/powerplay: remove duplicate macro of smu_get_uclk_dpm_statesKevin Wang1-2/+0
remove duplicate macro of smu_get_uclk_dpm_states fix commit: drm/amd/powerplay: add the interface for getting ultimate frequency v3 Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Reviewed-by: Prike Liang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amd/amdgpu:Fix compute ring unable to detect hang.Jesse Zhang3-19/+13
When compute fence did not signal, compute ring cannot detect hardware hang because its timeout value is set to be infinite by default. In SR-IOV and passthrough mode, if user does not declare custome timeout value for compute ring, then use gfx ring timeout value as default. So that when there is a ture hardware hang, compute ring can detect it. Signed-off-by: Jesse Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: Use mode2 mode to perform GPU RESET for Renoirchen gong1-0/+3
Renoir need to use mode2 mode to implement GPU RESET Signed-off-by: chen gong <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amd/powerplay: A workaround to GPU RESET on APUchen gong1-1/+4
Changes to function "smu_suspend" in amdgpu_smu.c is a workaround. We should get real information about if baco is enabled or not, while we always consider APU SMU feature as enabled in current code. I know APU do not support baco mode for GPU reset, so I use "adev->flags" to skip function "smu_feature_is_enabled". Signed-off-by: chen gong <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amd/powerplay: Add mode2 mode for GPU RESET in SMUchen gong2-0/+14
Renoir need to use mode2 mode to implement GPU RESET Signed-off-by: chen gong <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdkfd: Sync gfx10 kfd2kgd_calls function pointersYong Zhao1-2/+3
get_hive_id was not set. Also, adjust the function setting sequence. Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdkfd: Fix NULL pointer dereference for set_scratch_backing_va()Yong Zhao6-16/+9
Currently this function pointer is missing for GFX10. Considering it is a void function since GFX9, fix it by checking the function pointer before dereferencing it. Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdkfd: Remove unnecessary pm_init() for non HWS modeYong Zhao1-2/+8
The packet manager is not needed for non HWS mode except Hawaii, so only initialize it for Hawaii under non HWS mode. This will simplify debugging under non HWS mode for all new asics, because it eliminates one variable out of the equation in non HWS mode Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdkfd: Remove excessive print when reserving doorbellsYong Zhao1-4/+8
The dozens of printing messages are compressed into 2 lines. Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdkfd: Add an error print if SDMA RLC is not idleYong Zhao5-10/+30
The message will be useful when troubleshooting the issues. Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu/display: fix 64 bit divideAlex Deucher1-1/+3
Use proper helper for 32 bit. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: correct condition check for psp rlc autoloadLe Ma1-1/+2
Otherwise non-autoload case will go into the wrong routine and fail. Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: add command id in psp response failure messageHawking Zhang1-2/+3
For better clarification of issue. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: enable psp front door loading by default on ArcturusLe Ma1-2/+1
Front door firmware loading is done via the psp rather than the driver. Signed-off-by: Le Ma <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: disable vcn ip block for front door loading on ArcturusLe Ma1-1/+2
Needs more work to enable via front door loading. Signed-off-by: Le Ma <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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