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2019-11-13drm/amd/display: Hook up the DMUB service in DMNicholas Kazlauskas2-0/+317
[Why] We need DMCUB on Renoir to support DMCU and PHY initialization. The DMUB service provides a mechanism to load the DMCUB. [How] Include the DMUB service in amdgpu_dm. Frontdoor loading of the DMCUB firmware needs to happen via PSP. To pass the firmware to PSP we need to hand it off to the firmware list in the base driver during software initialization. Most of the DMUB service can technically be initialized at this point in time, but we don't want to be allocating framebuffer memory for hardware that doesn't support the DMCUB and in order to check that we need to be able to read registers - something DM helpers aren't setup to do in software initialization. So everything but the service creation itself will get deferred to hardware initialization. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-13drm/amd/display: Add PSP FW version mask.Yongqiang Sun1-1/+1
[Why] PSP version format is AB.CD.EF.GH, where CD and GH is the main version. current psp version check for dmcub loading dmcu check 0x00110029, in case of some psp version eg: 0x00110227 which main version should be 0x00110027, will result in unexpeceted dmcub loading dmcu FW. [How] Add psp version mask 0x00FF00FF for checking version. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-13drm/amd/display: Change dmcu init sequence for dmcub loading dmcu FW.Yongqiang Sun5-3/+97
[Why] DMCU isn't intiliazed properly by dmcub loading due to dmcub initialize sequence. [How] Change dmcu init sequece to meet dmcub initilize. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-13drm/amd/display: Add the DMUB serviceNicholas Kazlauskas15-0/+2062
The DMUB service is the interface to the DMCUB. It's required to support Renoir features so it will be enabled and compiled automatically when the Renoir display engine is enabled via CONFIG_DRM_AMD_DC_DCN2_1. DMUB code will initially be guarded by CONFIG_DRM_AMD_DC_DMUB and later switched to CONFIG_DRM_AMD_DC_DCN2_1 with the config option dropped. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-13drm/amd/display: Drop DMCUB from DCN21 resourcesNicholas Kazlauskas1-31/+0
The interface to the DMCUB won't be through DC itself. DC will instead call into the DMUB interface introduced with a future change. The CONFIG_DRM_AMD_DC_DMUB defines will still be used for now but will be dropped at the end of the series. Since this define was never configurable in the first place this code wasn't used. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-13drm/amdgpu: Add PSP loading support for DMCUB ucodeNicholas Kazlauskas1-0/+3
DMCUB ucode requires secure loading through PSP. This is already supported in PSP as GFX_FW_TYPE_DMUB, it just needs to be mapped from AMDGPU_UCODE_ID_DMCUB to GFX_FW_TYPE_DMUB. DMUB is a shorthand name for DMCUB and can be used interchangeably. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-13drm/amdgpu: Add ucode support for DMCUBNicholas Kazlauskas2-1/+19
The DMCUB is a secondary DMCU (Display MicroController Unit) that has its own separate firmware. It's required for DMCU support on Renoir. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-13drm/amd/display: fix dereference of pointer aconnector when it is nullColin Ian King1-3/+2
Currently pointer aconnector is being dereferenced by the call to to_dm_connector_state before it is being null checked, this could lead to a null pointer dereference. Fix this by checking that aconnector is null before dereferencing it. Addresses-Coverity: ("Dereference before null check") Reviewed-by: Mikita Lipski <[email protected]> Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-13drm/amd/display: Add MST atomic routinesMikita Lipski4-41/+108
- Adding encoder atomic check to find vcpi slots for a connector - Using DRM helper functions to calculate PBN - Adding connector atomic check to release vcpi slots if connector loses CRTC - Calculate PBN and VCPI slots only once during atomic check and store them on crtc_state to eliminate redundant calculation - Call drm_dp_mst_atomic_check to verify validity of MST topology during state atomic check v2: squashed previous 3 separate patches, removed DSC PBN calculation, and added PBN and VCPI slots properties to amdgpu connector v3: - moved vcpi_slots and pbn properties to dm_crtc_state and dc_stream_state - updates stream's vcpi_slots and pbn on commit - separated patch from the DSC MST series v4: - set vcpi_slots and pbn properties to dm_connector_state - copy porperties from connector state on to crtc state v5: - keep the pbn and vcpi values only on connnector state - added a void pointer to the stream state instead on two ints, because dc_stream_state is OS agnostic. Pointer points to the current dm_connector_state. v6: - Remove new param from stream v7: - Fix error with using max capable bpc v8: - squash in fix from Gustavo A. R. Silva Reviewed-by: Lyude Paul <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-13drm/amdgpu/vcn: finish delay work before release resourcesAlex Deucher1-0/+2
flush/cancel delayed works before doing finalization to avoid concurrently requests. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-13drm/amd/powerplay: read pcie speed/width info (v2)Kenneth Feng4-9/+69
sysfs interface to read pcie speed&width info on navi1x. v2: fix warning (trivial) Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-11drm/amdgpu/smu_v11: Unify and fix power limitsMatt Coffin8-28/+78
[Why] On Navi10, and presumably arcterus, updating pp_table via sysfs would not re-scale the maximum possible power limit one can set. On navi10, the SMU code ignored the power percentage overdrive setting entirely, and would not allow you to exceed the default power limit at all. [How] Adding a function to the SMU interface to get the pptable version of the default power limit allows ASIC-specific code to provide the correct maximum-settable power limit for the current pptable. v3: fix spelling (Alex) Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Matt Coffin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-11drm/amdgpu/navi10: Implement od clk printingMatt Coffin1-5/+51
[Why] Before this patch, navi10 overdrive settings could not be printed via pp_od_clk_voltage [How] Implement printing for the overdrive settings for the following clocks in navi10's ppt print_clk_levels implementation: * SMU_OD_SCLK * SMU_OD_MCLK * SMU_OD_VDDC_CURVE Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Matt Coffin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-11drm/amdgpu/navi10: implement GFXCLK_CURVE overdriveMatt Coffin2-2/+60
[Why] Before this patch, there was no way to set the gfxclk voltage curve in the overdrive settings for navi10 through pp_od_clk_voltage [How] Add the required implementation to navi10's ppt dpm table editing implementation, similar to the vega20 implementation and interface. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Matt Coffin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-11drm/amdgpu/navi10: implement sclk/mclk OD via pp_od_clk_voltageMatt Coffin3-0/+209
[Why] Before this patch, there was no way to use pp_od_clk_voltage on navi [How] Similar to the vega20 implementation, but using the common smc_v11_0 headers, implemented the pp_od_clk_voltage API for navi10's pptable implementation Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Matt Coffin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-11drm/amd/amdgpu: finish delay works before release resourcesJesse Zhang3-0/+5
flush/cancel delayed works before doing finalization to avoid concurrently requests. Signed-off-by: Jesse Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-11drm/amdgpu/powerplay/smu7: fix AVFS handling with custom powerplay tableAlex Deucher1-0/+7
When a custom powerplay table is provided, we need to update the OD VDDC flag to avoid AVFS being enabled when it shouldn't be. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205393 Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-11drm/amdgpu: avoid upload corrupted ta ucode to pspHawking Zhang1-1/+21
xgmi, ras, hdcp and dtm ta are actually separated ucode and need to handled case by case to upload to psp. We support the case that ta binary have one or multiple of them built-in. As a result, the driver should check each ta binariy's availablity before decide to upload them to psp. In the terminate (unload) case, the driver will check the context readiness before perform unload activity. It's fine to keep it as is. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-08drm/amdgpu/powerplay: fix AVFS handling with custom powerplay tableAlex Deucher1-0/+7
When a custom powerplay table is provided, we need to update the OD VDDC flag to avoid AVFS being enabled when it shouldn't be. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=205393 Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-08drm/amd/powerplay: dynamically disable ds and ulv for computeKenneth Feng3-0/+65
This is to improve the performance in the compute mode for vega10. For example, the original performance for a rocm bandwidth test: 2G internal GPU copy, is about 99GB/s. With the idle power features disabled dynamically, the porformance is promoted to about 215GB/s. Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Evan Quan <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-08drm/amd/powerplay: correct Arcturus OD supportEvan Quan1-3/+5
OD is not supported on Arcturus. Thus the pp_od_clk_voltage sysfs interface is also not supported. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-08drm/amdgpu: allow direct upload save restore list for raven2changzhu1-1/+3
It will cause modprobe atombios stuck problem in raven2 if it doesn't allow direct upload save restore list from gfx driver. So it needs to allow direct upload save restore list for raven2 temporarily. Signed-off-by: changzhu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-07drm/amdgpu: Avoid accidental thread reactivation.Andrey Grodzovsky1-0/+10
Problem: During GPU reset we call the GPU scheduler to suspend it's thread, those two functions in amdgpu also suspend and resume the sceduler for their needs but this can collide with GPU reset in progress and accidently restart a suspended thread before time. Fix: Serialize with GPU reset. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-07Revert "drm/amdgpu: dont schedule jobs while in reset"Andrey Grodzovsky1-4/+1
This reverts commit 89b3d86403f1025f6b430d8f9ffc590efbadce62. We will do a proper fix in next patch. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-07drm/amdgpu: fix vega20 pstate status changeJonathan Kim1-3/+4
vega20 only requires all devices be set to same pstate level for low pstate and not high. Signed-off-by: Jonathan Kim <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-07drm/amdgpu: fix sysfs interface pcie_replay_count error on navi asicKevin Wang1-0/+11
the asic callback function of get_pcie_replay_count is not implement on navi asic, it will cause null pinter error when read this interface. Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Kent Russell <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-07drm/amdgpu: Need to disable msix when unloading driverEmily Deng1-1/+1
For driver reload test, it will report "can't enable MSI (MSI-X already enabled)". Signed-off-by: Emily Deng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-07drm/amdgpu: Add comments to gmc structureOak Zeng1-0/+30
Explain fields like aper_base, agp_start etc. The definition of those fields are confusing as they are from different view (CPU or GPU). Add comments for easier understand. Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-06drm/amdgpu: Improve RAS documentation (v2)Alex Deucher1-7/+33
Clarify some areas, clean up formatting, add section for unrecoverable error handling. v2: fix grammatical errors Reviewed-by: Yong Zhao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-06drm/amdgpu/renoir: move gfxoff handling into gfx9 moduleAlex Deucher2-5/+6
To properly handle the option parsing ordering. Reviewed-by: Yong Zhao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-06drm/amdgpu: fix double reference droppingPan Bian1-4/+2
The reference to object fence is dropped at the end of the loop. However, it is dropped again outside the loop. The reference can be dropped immediately after calling dma_fence_wait() in the loop and thus the dropping operation outside the loop can be removed. Reviewed-by: Christian König <[email protected]> Signed-off-by: Pan Bian <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-06drm/amd/powerplay: fix struct init in renoir_print_clk_levelsRaul E Rangel1-1/+3
drivers/gpu/drm/amd/powerplay/renoir_ppt.c:186:2: error: missing braces around initializer [-Werror=missing-braces] SmuMetrics_t metrics = {0}; ^ Fixes: 8b8031703bd7 ("drm/amd/powerplay: implement sysfs for getting dpm clock") Signed-off-by: Raul E Rangel <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-06drm/amdgpu: fix potential double drop fence referencePan Bian1-0/+2
The object fence is not set to NULL after its reference is dropped. As a result, its reference may be dropped again if error occurs after that, which may lead to a use after free bug. To avoid the issue, fence is explicitly set to NULL after dropping its reference. Acked-by: Christian König <[email protected]> Signed-off-by: Pan Bian <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-06drm/amdgpu: change read of GPU clock counter on Vega10 VFEric Huang1-3/+16
Using unified VBIOS has performance drop in sriov environment. The fix is switching to another register instead. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-06drm/amdgpu: add warning for GRBM 1-cycle delay issue in gfx9changzhu1-0/+7
It needs to add warning to update firmware in gfx9 in case that firmware is too old to have function to realize dummy read in cp firmware. Signed-off-by: changzhu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-06drm/amdgpu: add dummy read by engines for some GCVM status registers in gfx10changzhu4-6/+64
The GRBM register interface is now capable of bursting 1 cycle per register wr->wr, wr->rd much faster than previous muticycle per transaction done interface. This has caused a problem where status registers requiring HW to update have a 1 cycle delay, due to the register update having to go through GRBM. For cp ucode, it has realized dummy read in cp firmware.It covers the use of WAIT_REG_MEM operation 1 case only.So it needs to call gfx_v10_0_wait_reg_mem in gfx10. Besides it also needs to add warning to update firmware in case firmware is too old to have function to realize dummy read in cp firmware. For sdma ucode, it hasn't realized dummy read in sdma firmware. sdma is moved to gfxhub in gfx10. So it needs to add dummy read in driver between amdgpu_ring_emit_wreg and amdgpu_ring_emit_reg_wait for sdma_v5_0. Signed-off-by: changzhu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-06drm/amd/powerplay: fix deadlock on setting power_dpm_force_performance_levelEvan Quan1-5/+14
smu_enable_umd_pstate() will try to get the smu->mutex which was already hold by its parent API smu_force_performance_level() on the call path. Thus deadlock happens. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-06drm/amdgpu: perform p-state switch after the whole hive initializedEvan Quan1-12/+35
P-state switch should be performed after all devices from the hive get initialized. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Reviewed-by: Jonathan Kim <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-06drm/amdgpu: fix possible pstate switch race conditionEvan Quan2-2/+35
Added lock protection so that the p-state switch will be guarded to be sequential. Also update the hive pstate only all device from the hive are in the same state. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-06drm/amdgpu: register gpu instance before fan boost feature enablmentEvan Quan2-1/+7
Otherwise, the feature enablement will be skipped due to wrong count. Fixes: beff74bc6e0fa91 ("drm/amdgpu: fix a race in GPU reset with IB test (v2)") Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-06drm/amd/swSMU: fix smu workload bit map errorKevin Wang2-2/+2
fix workload bit (WORKLOAD_PPLIB_COMPUTE_BIT) map error on vega20 and navi asic. fix commit: drm/amd/powerplay: add function get_workload_type_map for swsmu Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-06drm/amd/powerplay: update Arcturus driver-smu interface headerEvan Quan2-2/+2
To fit the latest SMU firmware. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Le Ma <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-06drm/amdgpu: disallow direct upload save restore list from gfx driverHawking Zhang1-1/+2
Direct uploading save/restore list via mmio register writes breaks the security policy. Instead, the driver should pass s&r list to psp. For all the ASICs that use rlc v2_1 headers, the driver actually upload s&r list twice, in non-psp ucode front door loading phase and gfx pg initialization phase. The latter is not allowed. VG12 is the only exception where the driver still keeps legacy approach for S&R list uploading. In theory, this can be elimnated if we have valid srcntl ucode for VG12. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Candice Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-06drm/amdgpu/discovery: Need to free discovery memoryEmily Deng1-3/+3
When unloading driver, need to free discovery memory. Signed-off-by: Emily Deng <[email protected]> Reviewed-by: Xiaojie Yuan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-06drm/amd/powerplay: print the pptable providerXiaojie Yuan1-0/+2
So we know where the tables came from. Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-06Revert "drm/amd/display: setting the DIG_MODE to the correct value."Zhan Liu1-9/+0
This reverts commit 967a3b85bac91c55eff740e61bf270c2732f48b2. Reason for revert: Root cause of this issue is found. The workaround is not needed anymore. Signed-off-by: Zhan Liu <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-06drm/amd/display: Add ENGINE_ID_DIGD condition check for Navi14Zhan Liu1-0/+5
[Why] Navi10 has 6 PHY, but Navi14 only has 5 PHY, that is because there is no ENGINE_ID_DIGD in Navi14. Without this patch, many HDMI related issues (e.g. HDMI S3 resume failure, HDMI pink screen on boot) will be observed. [How] If "eng_id" is larger than ENGINE_ID_DIGD, then add "eng_id" by 1. Signed-off-by: Zhan Liu <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-06drm/amdgpu: Show resolution correctly in mode validation debug outputNeil Mayhew1-1/+1
Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Neil Mayhew <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-06drm/amdgpu/gpuvm: add some additional comments in amdgpu_vm_update_ptesAlex Deucher1-1/+9
To better clarify what is happening in this function. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-06drm/amdgpu: enable VCN DPG on Raven and Raven2Alex Deucher1-2/+6
It's safe to enable dynamic VCN powergating on raven and raven2 for increased power savings. Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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