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2018-03-01Merge tag 'drm-intel-next-2018-02-21' of ↵Dave Airlie2-3/+3
git://anongit.freedesktop.org/drm/drm-intel into drm-next Driver Changes: - Lift alpha_support protection from Cannonlake (Rodrigo) * Meaning the driver should mostly work for the hardware we had at our disposal when testing * Used to be preliminary_hw_support - Add missing Cannonlake PCI device ID of 0x5A4C (Rodrigo) - Cannonlake port register fix (Mahesh) - Fix Dell Venue 8 Pro black screen after modeset (Hans) - Fix for always returning zero out-fence from execbuf (Daniele) - Fix HDMI audio when no no relevant video output is active (Jani) - Fix memleak of VBT data on driver_unload (Hans) - Fix for KASAN found locking issue (Maarten) - RCU barrier consolidation to improve igt/gem_sync/idle (Chris) - Optimizations to IRQ handlers (Chris) - vblank tracking improvements (64-bit resolution, PM) (Dhinakaran) - Pipe select bit corrections (Ville) - Reduce runtime computed device_info fields (Chris) - Tune down some WARN_ONs to GEM_BUG_ON now that CI has good coverage (Chris) - A bunch of kerneldoc warning fixes (Chris) * tag 'drm-intel-next-2018-02-21' of git://anongit.freedesktop.org/drm/drm-intel: (113 commits) drm/i915: Update DRIVER_DATE to 20180221 drm/i915/fbc: Use PLANE_HAS_FENCE to determine if the plane is fenced drm/i915/fbdev: Use the PLANE_HAS_FENCE flags from the time of pinning drm/i915: Move the policy for placement of the GGTT vma into the caller drm/i915: Also check view->type for a normal GGTT view drm/i915: Drop WaDoubleCursorLP3Latency:ivb drm/i915: Set the primary plane pipe select bits on gen4 drm/i915: Don't set cursor pipe select bits on g4x+ drm/i915: Assert that we don't overflow frontbuffer tracking bits drm/i915: Track number of pending freed objects drm/i915/: Initialise trans_min for skl_compute_transition_wm() drm/i915: Clear the in-use marker on execbuf failure drm/i915: Prune gen8_gt_irq_handler drm/i915: Track GT interrupt handling using the master iir drm/i915: Remove WARN_ONCE for failing to pm_runtime_if_in_use drm: intel_dpio_phy: fix kernel-doc comments at nested struct drm/i915: Release connector iterator on a digital port conflict. drm/i915/execlists: Remove too early assert drm/i915: Assert that we always complete a submission to guc/execlists drm: move read_domains and write_domain into i915 ...
2018-02-28drm/amdgpu: fix module parameter descriptionsAlex Deucher1-2/+2
Some were missing the close parens around options. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-28drm/amdgpu: Map all visible VRAM at startupAmber Lin2-0/+18
When using CPU to update page table, we need to kmap all the PDs/PTs after they are allocated and that requires a TLB shot down on each CPU, which is quite heavy. Instead, we map the whole visible VRAM to a kernel address at once. Pages can be obtained from the offset. v2: move the mapping base from gmc to amdgpu_mman structure, and the implementation in amdgpu_ttm_* functions Signed-off-by: Amber Lin <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-28drm/amd/display: check for ipp before calling cursor operationsShirish S1-2/+4
Currently all cursor related functions are made to all pipes that are attached to a particular stream. This is not applicable to pipes that do not have cursor plane initialised like underlay. Hence this patch allows cursor related operations on a pipe only if ipp in available on that particular pipe. The check is added to set_cursor_position & set_cursor_attribute. Signed-off-by: Shirish S <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2018-02-28drm/amd/display: make dm_dp_aux_transfer return payload bytes instead of sizeShirish S5-21/+13
The drm layer expects aux->transfer() to return the payload bytes read. Currently dm_dp_aux_transfer() returns the payload size which does not gets updated during the read, hence not giving the right data for the drm layer to pars edid. This leads to the drm layer to conclude as the edid is BAD and hence some monitors/devices dont get detected properly. This patch changes the return type of dm_dp_aux_transfer() to actual bytes read during DP_AUX_NATIVE_READ & DP_AUX_I2C_READ. Signed-off-by: Shirish S <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-28drm/amdgpu: disable GFX ring and disable PQ wptr in hw_finiMonk Liu1-1/+7
otherwise there will be DMAR reading error comes out from CP since GFX is still alive and CPC's WPTR_POLL is still enabled, which would lead to DMAR read error. fix: we can hault CPG after hw_fini, but cannot halt CPC becaues KIQ stil need to be alive to let RLCV invoke, but its WPTR_POLL could be disabled. Signed-off-by: Monk Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-28drm/amdgpu: cleanup SA inti and fini(v2)Monk Liu3-59/+11
should use bo_create_kernel instead of split to two function that create and pin the SA bo issue: before this patch, there are DMAR read error in host side when running SRIOV test, the DMAR address dropped in the range of SA bo. fix: after this cleanups of SA init and fini, above DMAR eror gone. v2: keep sa_bo's fini instead of suspend, to keep reporting error Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-28drm/amdgpu: Correct sdma_v4 get_wptr(v2)Emily Deng1-11/+7
the original method will change the wptr value in wb. v2: furthur cleanup Signed-off-by: Emily Deng <[email protected]> Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-28drm/amdgpu: adjust timeout for ib_ring_tests(v2)Monk Liu1-1/+32
issue: sometime GFX/MM ib test hit timeout under SRIOV env, root cause is that engine doesn't come back soon enough so the current IB test considered as timed out. fix: for SRIOV GFX IB test wait time need to be expanded a lot during SRIOV runtimei mode since it couldn't really begin before GFX engine come back. for SRIOV MM IB test it always need more time since MM scheduling is not go together with GFX engine, it is controled by h/w MM scheduler so no matter runtime or exclusive mode MM IB test always need more time. v2: use ring type instead of idx to judge Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-28drm/amdgpu: don't use MM idle_work for SRIOV(v2)Monk Liu2-9/+6
SRIOV doesn't give VF cg/pg feature so the MM's idle_work is skipped for SR-IOV v2: remove superfluous changes since idle_work is not scheduled for SR-IOV so the condition check for SR-IOV inside idle_work also can be dropped v3: drop the SRIOV check in amdgpu_vce/uvd_suspend Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-28drm/amd/pp: Print more smu failed info on Vega10Rex Zhu1-1/+1
Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-28drm/amd/powerplay: fix power over limit on FijiEric Huang1-7/+0
power containment disabled only on Fiji and compute power profile. It violates PCIe spec and may cause power supply failed. Enabling it will fix the issue, even the fix will drop performance of some compute tests. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2018-02-28drm/amdgpu:Fixed wrong emit frame size for encJames Zhu1-1/+1
Emit frame size should match with corresponding function, uvd_v6_0_enc_ring_emit_vm_flush has 5 amdgpu_ring_write Signed-off-by: James Zhu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-28drm/amdgpu: increase gart size to 512MBMonk Liu1-1/+1
256MB is too small consider PTE/PDE shadow and TTM eviction activity Signed-off-by: Monk Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-28drm/amdgpu: move WB_FREE to correct placeMonk Liu1-5/+7
WB_FREE should be put after all engines's hw_fini done, otherwise the invalid wptr/rptr_addr would still be used by engines which trigger abnormal bugs. This fixes couple DMAR reading error in host side for SRIOV after guest kmd is unloaded. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-28drm/amdgpu: change gfx9 ib test to use WBMonk Liu1-50/+57
two reasons to switch SCRATCH reg method to WB method: 1)Because when doing IB test we don't want to involve KIQ health status affect, and since SCRATCH register access is go through KIQ that way GFX IB test would failed due to KIQ fail. 2)acccessing SCRATCH register cost much more time than WB method because SCRATCH register access runs through KIQ which at least could begin after GPU world switch back to current Guest VF Signed-off-by: Monk Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-28drm/amdgpu: cond_exec only for schedule with a jobMonk Liu1-1/+1
issue: under SR-IOV sometimes the iB test will fail on gfx ring fix: with cond_exec inserted in RB the gfx engine would skip part packets if RLCV issue PREEMPT on gfx engine if gfx engine is prior to COND_EXEC packet, this is okay for regular command from UMD, but for the ib test since the whole dma format doesn't support PREEMPT so must remove the COND_EXEC from it. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-28drm/amdgpu: only flush hotplug work without DCMonk Liu1-2/+4
since hotplug_work is initialized under the case of no dc support Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-28drm/amdgpu: skip ECC for SRIOV in gmc late_initMonk Liu1-1/+1
Signed-off-by: Monk Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-28drm/amdgpu: fix&cleanups for wb_clearMonk Liu2-3/+4
fix: should do right shift on wb before clearing cleanups: 1,should memset all wb buffer 2,set max wb number to 128 (total 4KB) is big enough Signed-off-by: Monk Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-26drm/amdgpu/powerplay/smu7: use proper dep table for mclkAlex Deucher3-3/+3
For mclk od, use the vdd dependency on mclk table. Looks like a cut and paste typo. Reviewed-by: Rex Zhu<[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-26drm/amd/amdgpu: Correct VRAM width for APUs with GMC9Tom St Denis1-1/+4
DDR4 has a 64-bit width not 128-bits. It was reporting twice the width. Tested with my Ryzen 2400G. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-26drm/ttm: drop persistent_swap_storage from ttm_bo_init and coChristian König1-2/+2
Never used as parameter, the only driver actually using this is nouveau and there it is initialized after the BO is initialized. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-26drm/ttm: drop ttm->dummy_read_pageChristian König1-3/+2
Only used by the AGP backend and there it can be easily accessed using ttm->bdev->glob. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-26drm/amd/pp: Move common dpm check functions to hardwaremanager.cRex Zhu4-29/+10
Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-26drm/amd/pp: Cleaning up vega10_enable_dpm_tasks functionRex Zhu1-6/+5
1. move display num initialize out of dpm enable tasks. 2. do not set/restore smc telemetry if dpm is runing. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-26drm/amd/pp: Refine code in powerplay for Cz/Vega10Rex Zhu6-39/+43
Add dpm check functions on CZ/Vega10 to smu backend function table. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-26drm/amd/pp: Remove dead error checking code on Vega10Rex Zhu4-142/+67
when smu failed, print out the error info immediately for debug. smum_send_msg_to_smu always return true, so no need to check return value. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-26drm/amd/pp: Add debug info when smu failed on Vega10Rex Zhu1-5/+13
When smu msssage failed, print out return value in dmesg. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-26drm/amd/pp: Remove duplicated vega10_is_smc_ram_running callsRex Zhu1-12/+3
Avoid conflicts in reading the same register mmPCIE_INDEX2 with other clients Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-26drm/amd: Remove inclusion of non-existing include directoriesCorentin Labbe1-2/+0
This patch fix the following build warnings: CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_drv.o cc1: warning: ../display/: No such file or directory [-Wmissing-include-dirs] cc1: warning: ../display/include: No such file or directory [-Wmissing-include-dirs] CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_device.o cc1: warning: ../display/: No such file or directory [-Wmissing-include-dirs] cc1: warning: ../display/include: No such file or directory [-Wmissing-include-dirs] [...] This warning is shown for each file in amdgpu directory, so it spams a lot. Acked-by: Christian König <[email protected]> Signed-off-by: Corentin Labbe <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-26drm/amd: remove inclusion of non-existing scheduler directoryCorentin Labbe1-1/+0
The scheduler directory was removed via commit 1b1f42d8fde4 ("drm: move amd_gpu_scheduler into common location") Remove it from include path. Reviewed-by: Christian König <[email protected]> Signed-off-by: Corentin Labbe <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-26drm/amdgpu: Remove duplicate setting of ->need_swiotlbThierry Reding1-1/+0
There's no need to set this before the number of DMA bits has been properly determined. Signed-off-by: Thierry Reding <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-26drm/amd/pp: Add a pp feature mask bit for AutoWattman featureRex Zhu1-0/+1
Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-26drm/amdgpu: Change default value of module parameter amdgpu_pp_feature_maskRex Zhu1-1/+1
Currently all pp features are enabled by default except OVERDRIVE Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-26drm/amd/powerplay: fix thermal interrupts on vega10Eric Huang1-1/+3
a bug in programming thermal interrupt register masks out interrupts and driver cannot receive interrupts. Setting 0 to mask bits will fix it. Signed-off-by: Eric Huang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-26drm/amdgpu: Add query vram width in CGS query system infoRex Zhu2-0/+4
powerplay need vram width to set default mclk optimization settings(uphyst/downhyst/activity threshold) Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-26drm/amdgpu: use the TTM dummy page instead of allocating oneChristian König13-41/+30
We have a global dummy page in TTM, use that one instead of allocating a new one. Signed-off-by: Christian König <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-26drm/amd/pp: Fix bug that dpm level was not really lockedRex Zhu1-8/+14
Lock the dpm levels when we use SW method to modify the dpm tables directly to avoid a possible race with the smu. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-26drm/amd/pp: Fix error handling when smu return failed on Vega10.Rex Zhu1-12/+14
Clamp the clock index to a valid range when reading it back Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-26drm/ttm: use bit flag to replace allow_reserved_eviction in ttm_operation_ctxRoger He2-4/+4
for saving memory and more bit flag can be used in future Signed-off-by: Roger He <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-20drm/amdgpu: use drm_gem_private_object_initChristian König1-5/+1
We use our own backing store and don't need the shmem file. Signed-off-by: Christian König <[email protected]> Acked-by: Daniel Vetter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-20drm/amdgpu: mitigate workaround for i915Christian König1-11/+20
To be able to use DRI_PRIME with amdgpu and i915 we add all our fences only as exclusive ones. Disable that behavior when sharing between amdgpu itself cause it hinders concurrent execution. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-20drm/amdgpu: implement amdgpu_gem_map_(attach/detach)Christian König3-22/+34
Instead of the pin/unpin callback implement the attach/detach ones. Functional identical, but allows us access to the attachment. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu/powerplay/smu7: drop refresh rate checks for mclk switchingAlex Deucher1-2/+1
The logic has moved to cgs. mclk switching with DC at higher refresh rates should work. Reviewed-by: Eric Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: Harry Wentland <[email protected]>
2018-02-19drm/amdgpu/cgs: add refresh rate checking to non-DC display codeAlex Deucher1-0/+5
Clamp the vblank period to 0 if the refresh rate is larger than 120 hz for non-DC. This allows us to remove the refresh rate checks from powerplay for mclk switching. Reviewed-by: Eric Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/powerplay/smu7: allow mclk switching with no displaysAlex Deucher1-4/+7
If there are no displays attached, there is no reason to disable mclk switching. Fixes mclks getting set to high when there are no displays attached. Reviewed-by: Eric Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2018-02-19drm/amd/powerplay/vega10: allow mclk switching with no displaysAlex Deucher1-4/+7
If there are no displays attached, there is no reason to disable mclk switching. Fixes mclks getting set to high when there are no displays attached. Reviewed-by: Eric Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2018-02-19drm/amd/powerplay: use PP_CAP macro for disable_mclk_switching_for_frame_lockAlex Deucher1-4/+4
Rather than open coding it. Reviewed-by: Eric Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/powerplay: remove unused headersCorentin Labbe2-479/+0
All thoses headers are not used by any source files. Lets just remove them. Signed-off-by: Corentin Labbe <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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