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path: root/drivers/gpu/drm/amd
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2018-02-19drm/amd/display: clean up DCHUBBUB register definition in hwseqEric Bernstein1-75/+1
Cleanup to remove unused register definition from hw sequencer header file since implementation moved from hw sequencer to dchubub file. Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Refactor remove mpcc processing.Yongqiang Sun1-14/+5
No need to use loop find opp, use opp in stream_res. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Move opp reg access from hwss to opp module.Yongqiang Sun5-15/+29
Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: disablePSR in UpdatePlanes in PassiveLevelCharlene Liu1-0/+3
Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Fix null-derefs on non-dcn buildsRoman Li2-2/+4
Fixing regression introduced by 'Use real BE and FE index to program regs.' Signed-off-by: Roman Li <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Move dpp reg access from hwss to dpp module.Yongqiang Sun6-43/+49
Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Check opplist in pipe ctx not in res pool.Yongqiang Sun1-6/+6
Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Drop dm_connector_update_modesHarry Wentland1-8/+2
It's unused since the drm_edid_to_eld cleanup Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Fix check for setting input TFAndrew Jiang6-15/+22
We no longer change the plane state pointer for full updates, and as such, we weren't setting the input transfer function and programming the degamma registers when we are supposed to. Check for a full update, an input TF change, or a gamma change in the update flags instead to correct this. Signed-off-by: Andrew Jiang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Define remove_stream_from_ctx resource funcNikola Cornij2-0/+8
This will allow us to clean up resources on a stream as needed. Signed-off-by: Nikola Cornij <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Make create_stream_for_sink more consistentHarry Wentland1-28/+25
We've got a helper function to call dc_create_stream_for_sink and one other place that calls it directly. Make sure we call the helper functions always since we need to update a bunch of things in stream and don't want to miss that. Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Log which clocks are unsupportedHarry Wentland1-1/+4
It would be useful to know which clocks are unsupported when logging an error message about unsupported clocks. Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Use real BE and FE index to program regs.Yongqiang Sun7-33/+55
In case of some pipes are fused, pipe_idx should not be used to program pipe regs. Instead of that, BE and FE inst number should be used for reg index. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Move hubp reg access from hwss to hubp module.Yongqiang Sun5-21/+36
Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Debug-print reason for mode validation failureHarry Wentland1-2/+3
Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Don't block dual-link DVI modesHarry Wentland1-2/+1
Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Don't allow dual-link DVI on all ASICs.Harry Wentland6-2/+10
Our APUs (Carrizo, Stoney, Raven) don't support it. v2: Don't use is_apu as other ASICs might also not support it Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Debug print when validate_stream failsHarry Wentland1-1/+9
It might be good to understand why validate fails. Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Disable eDP with a proper sequence.Yongqiang Sun4-33/+39
Proper sequence should be: disable backlight dp blank disable output edp power off In enable accelatate mode, all the encoder and controller are disabled, so move disable eDP to the function is the easiest way to implement. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: dal 3.1.28Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Pass signal directly to enable_tmds_outputHarry Wentland5-18/+9
This makes the check for HDMI and dual-link DVI a bit more straightforward. Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Remove unnecessary fail labels in create_stream_for_sinkHarry Wentland1-9/+5
Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Move MAX_TMDS_CLOCK define to headerHarry Wentland4-15/+5
Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: disable eDP backlight for extend monitor only reboot use case.Yongqiang Sun1-1/+27
Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Pass full 3x4 remap matrix for color transformKrunoslav Kovac6-139/+28
Signed-off-by: Krunoslav Kovac <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Prevent master programming in multisyncMikita Lipski3-3/+5
Verify that the stream is master - and program only the slave displays Signed-off-by: Mikita Lipski <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Fix FBC topology changeRoman Li1-4/+19
With FBC enabled there was a potential null-deref on topology change due to hardcorded pipe index. Signed-off-by: Roman Li <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Use pipe_control_lock instead of tg lock.Yongqiang Sun1-2/+2
Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Fix topology change issue in MST rehookJerry (Fangzhi) Zuo1-0/+6
When topology changed and rehook up MST display to the same DP connector, need to take care of drm_dp_mst_port object. Due to the topology is changed, drm_dp_mst_port and corresponding i2c_algorithm object could be NULL in such situation. Signed-off-by: Jerry (Fangzhi) Zuo <[email protected]> Reviewed-by: Roman Li <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: cleanup after FBC init reworkRoman Li2-6/+0
After reworking FBC init for dynamic mem alloc old FBC init code in DC became redundant. Removing it. Signed-off-by: Roman Li <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: make FBC mem alloc dynamicRoman Li1-18/+44
- FBC init reworked to alloc memory based on display mode. - Removed asic-dependencies from dm Signed-off-by: Roman Li <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Eliminate several Maximus-specific code pathsKen Chalmers3-45/+12
This allows Maximus emulation to more closely mirror actual silicon execution. * Enable pool->base.display_clock creation on Maximus. * Enable rest of dce110_apply_ctx_to_hw on Maximus. * Remove apply_ctx_to_hw_fpga (no longer necessary with the full dce110_apply_ctx_to_hw enabled). * Disable the dmcu->funcs->set_psr_wait_loop call in dce112_set_clock for Maximus (this was the only fix-up necessary after enabling dce110_apply_ctx_to_hw; everything else works unmodified on Maximus). Signed-off-by: Ken Chalmers <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: Fix Maximus pixel clock programmingKen Chalmers1-11/+1
Maximus testing now defaults to a 700 MHz emulated dispclk Signed-off-by: Ken Chalmers <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/display: PME sw wa to support waking AZ D3Charlene Liu2-1/+14
Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: fix semicolon.cocci warningsFengguang Wu1-1/+1
drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c:281:2-3: Unneeded semicolon Remove unneeded semicolon. Generated by: scripts/coccinelle/misc/semicolon.cocci Fixes: 620f774f4687 ("drm/amdgpu: separate VMID and PASID handling") CC: Christian König <[email protected]> Signed-off-by: Fengguang Wu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/pp: Refine code shorten variable nameRex Zhu2-17/+9
Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/pp: Add a helper to convert VID to voltage valueRex Zhu2-0/+6
Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: drop extra tlb invalidation in gpuvmAlex Deucher1-2/+0
We only need to flush the HDP here, not invalidate the TLB. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: adjust HDP write queue flushing for tlb invalidationAlex Deucher6-11/+4
Separate tlb invalidation and hdp flushing and move the HDP flush to the caller. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: add HDP asic callbacks for SOC15 (v2)Alex Deucher1-0/+12
Needed to flush and invalidate the HDP block using the CPU. v2: use preferred register on soc15. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Samuel Li <[email protected]> (v1)
2018-02-19drm/amdgpu: add HDP asic callbacks for VIAlex Deucher1-0/+14
Needed to flush and invalidate the HDP block using the CPU. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Samuel Li <[email protected]>
2018-02-19drm/amdgpu: add HDP asic callbacks for CIKAlex Deucher1-0/+14
Needed to flush and invalidate the HDP block using the CPU. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Samuel Li <[email protected]>
2018-02-19drm/amdgpu: add HDP asic callbacks for SIAlex Deucher1-0/+14
Needed to flush and invalidate the HDP block using the CPU. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Samuel Li <[email protected]>
2018-02-19drm/amdgpu: add new asic callbacks for HDP flush/invalidationAlex Deucher1-0/+6
Needed to properly flush the HDP cache with the CPU from rather than the GPU. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Samuel Li <[email protected]>
2018-02-19drm/amdgpu: bump version for gfx9 high priority computeAndres Rodriguez1-1/+2
Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Andres Rodriguez <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: add high priority compute support for gfx9Andres Rodriguez1-0/+100
We follow the same approach as gfx8. The only changes are register access macros. Tested on vega10. The execution latency results fall within the expected ranges from the polaris10 data. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Andres Rodriguez <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/powerplay: use ffs/fls instead of implementing our ownEvan Quan1-23/+4
Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/powerplay: export the thermal ranges of Carrizo (V2)Evan Quan1-0/+15
V2: reuse the SMUThermal structure defined in pp_thermal.h Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/powerplay: export the thermal ranges of VI asics (V2)Evan Quan2-0/+27
V2: move the SMU7Thermal structure to newly created header file Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/powerplay: export vega10 specific thermal ranges (V2)Evan Quan2-0/+50
V2: new header file to hold the common SMU7Thermal structure Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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