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path: root/drivers/gpu/drm/amd
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2017-12-06drm/amd/display: Add dm_logger_append_va APIMichel Dänzer2-5/+17
Same as dm_logger_append, except it takes a va_list instead of a variable number of arguments. dm_logger_append is now a minimal wrapper around dm_logger_append_va. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: remove usage of legacy_cursor_updateShirish S1-30/+13
Currently the atomic check code uses legacy_cursor_update to differnetiate if the cursor plane is being requested by the user, which is not required as we shall be updating plane only if modeset is requested/required. Have tested cursor plane and underlay get updated seamlessly, without any lag or frame drops. Signed-off-by: Shirish S <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup raven1 vcn header files.Feifei Xu5-205/+3
Cleanup asic_reg/raven1/VCN folder. Remove unused vcn_1_0_default.h. Signed-off-by: Feifei Xu <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup raven1 thm header files.Feifei Xu4-3/+3
Cleanup asic_reg/raven1/THM folder. Signed-off-by: Feifei Xu <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup raven1 nbio header files.Feifei Xu6-7/+7
Cleanup asic_reg/raven1/NBIO folder. Signed-off-by: Feifei Xu <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup raven1 mp header files.Feifei Xu5-4/+4
Cleanup asic_reg/raven1/MP folder. Signed-off-by: Feifei Xu <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup raven1 mmhub header files.Feifei Xu5-1032/+4
Cleanup asic_reg/raven1/MMHUB folder.Remove unused mmhub_9_1_default.h Signed-off-by: Feifei Xu <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup raven1 gc header files.Feifei Xu4-35197/+1
Cleanup asic_reg/raven1/GC folder. Remove unused files: gc_9_1_default.h gc_9_1_sh_mask.h Signed-off-by: Feifei Xu <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup raven1 dcn header files.Feifei Xu9-8000/+12
Cleanup asic_reg/raven1/DCN folder.Remove unused dcn_1_0_default.h. Signed-off-by: Feifei Xu <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup raven1 sdma header files.Feifei Xu5-1660/+2
Cleanup asic_reg/raven1/SDMA0 folder.Remove unused sdma0_4_1_sh_mask.h. Signed-off-by: Feifei Xu <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup vega10 header files.Feifei Xu32-36/+36
Remove asic_reg/vega10 folder. Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup vega10 osssys header files.Feifei Xu4-178/+2
Cleanup asic_reg/vega10/OSSSYS folder. Signed-off-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup vega10 smuio header files.Feifei Xu4-102/+2
Cleanup asic_reg/vega10/SMUIO folder. Signed-off-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup vega10 nbif header files.Feifei Xu4-1272/+1
Cleanup asic_reg/vega10/NBIF folder. Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup vega10 nbio header files.Feifei Xu8-10/+10
Cleanup asic_reg/vega10/NBIO folder. Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup vega10 mmhub header files.Feifei Xu8-10/+10
Cleanup asic_reg/vega10/MMHUB folder. Signed-off-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup vega10 gc header files.Feifei Xu10-14/+14
Cleanup asic_reg/vega10/GC folder. Signed-off-by: Feifei Xu <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup vega10 vce header files.Feifei Xu5-6/+6
Cleanup asic_reg/vega10/VCE folder. Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup vega10 uvd header files.Feifei Xu5-130/+3
Cleanup asic_reg/vega10/UVD folder,remove unused uvd_7_0_default.h. Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup vega10 dce header files.Feifei Xu11-9884/+16
Cleanup asic_reg/vega10/DC folder.Remove dce_12_0_default.h. Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include: cleanup vega10 umc header files.Feifei Xu4-1/+1
Remove asic/vega10/UMC folder. Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup vega10 thm header files.Feifei Xu4-3/+3
Cleanup asic_reg/vega10/THM folder. Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup vega10 athub header files.Feifei Xu7-2743/+2501
Cleanup asic_reg/vega10/ATHUB folder,remove unused files. Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup vega10 mp header files.Feifei Xu8-2187/+1844
Cleanup asic_reg/vega10/MP folder, remove mp_9_0_default.h Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup vega10 hdp header files.Feifei Xu11-935/+818
Cleanup asic_reg/vega10/HDP folder, remove hdp_4_0_default.h Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup vega10 sdma0/1 header files.Feifei Xu15-5323/+5323
To remove include/asic_reg/vega10 folder,create IP folders sdma0/1. This patch cleanup asic_reg/vega10/SDMA folders. Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amdgpu:partially revert 1cfd8e237f0318e330190ac21d63c58ae6a1f66cMonk Liu6-12/+94
found RING0 test fail after S3 resume regression, which is introduced by 1cfd8e237f0318e330190ac21d63c58ae6a1f66c Because after suspend VRAM will be cleared, so driver must unpin the GART table(resident in VRAM) during suspend so it can be evicted to system ram and must correspondingly pin it during resume so the GART table could be restored to VRAM. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: dal 3.1.20Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Set OPP default values in init_hwAndrew Jiang2-11/+12
On S3 resume, we do not reconstruct OPP, but we do need to reinitialize some of its values to the default ones. Therefore, move those lines out of the OPP constructor and into init_hw. Also reset the hubp power gated flag, since nothing is power gated at init_hw. Signed-off-by: Andrew Jiang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: dal 3.1.19Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: DMCU and ABM maintenance and refactorAnthony Koo4-28/+36
Remove some globals that should really be per block state. Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Only program watermark for full update.Yongqiang Sun3-30/+23
For scaling and position change, it isn't necessary to program watermark and check P-State as well. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: dal 3.1.18Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Set full update flag in dcn_validate_bandwidthAndrew Jiang1-0/+2
Doing bandwidth validation implies that this is a full update. Set the flag inside the function in case whatever is calling dcn_validate_bandwidth doesn't set it. Signed-off-by: Andrew Jiang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Do not program front-end twiceLeo (Sunpeng) Li3-3/+32
The sequence of front-end > back-end > front-end programming will program the front-end more than once. Add a mode_changed flag, and use it to determine whether the front-end should be programmed before, or after back-end. Signed-off-by: Leo (Sunpeng) Li <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Trigger full update on plane changeLeo (Sunpeng) Li1-0/+5
With the optimized DCN10 frontend programming code, things are programmed only when requested. For now, trigger a full update on all plane changes. Signed-off-by: Leo (Sunpeng) Li <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Rename output_bpc to opp_input_bpcDmytro Laktyushkin3-14/+2
Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: fix refclk conversion from khz int to mhz floatDmytro Laktyushkin1-1/+1
Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: fix mpo validation failureDmytro Laktyushkin1-84/+36
There was an error in translation of mode support check. "N/A" is a failure condition while "" was a special case. This change will differentiate between the two by using a define. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: move csc matrix to hw_sharedYue Hin Lau2-26/+26
Signed-off-by: Yue Hin Lau <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: dal 3.1.17Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: update output csc matrix valuesYue Hin Lau2-22/+16
Signed-off-by: Yue Hin Lau <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Only update output transfer function for full type.Yongqiang Sun1-7/+16
dcn10_translate_regamma_to_hw_format costs 750us to run, it cannot be called within isr, check update flag before calling, only do it for full update. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: performance profiling instrumentationTony Cheng3-0/+15
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Yongqiang Sun <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Remove unnecessary dc_link vtableHarry Wentland2-109/+0
None of this needs to be a function table or dynamic in any way. Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: fix opp header register defineYue Hin Lau1-11/+14
Signed-off-by: Yue Hin Lau <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Update dchub and dpp as per update flags.Yongqiang Sun1-74/+117
Check update flags and update dchub and dpp as per flags, reduce reg access from 347 to 200, duration time reduce to 170us. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Move update_plane_addr to apply_ctx_for_surface for dce.Yongqiang Sun2-2/+5
Move update_plane_addr to apply_ctx_for_surface, address update will just be called once, not twice for updat type is full and medium. This will reduce some reg access and duration time. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: call set_mpc_output_csc from hwsequencerYue Hin Lau3-67/+156
Signed-off-by: Yue Hin Lau <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/display: Fix description of module parameter dc_logMichel Dänzer1-1/+1
It was incorrectly referencing the dc parameter, resulting in an empty description of the dc_log parameter. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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