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2017-12-14drm/amd/display: OPP DPG test patternEric Bernstein3-38/+43
Create opp_set_test_pattern function with similar interface and implementation as timing generator test pattern. Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: Build unity lut for shaperVitaly Prosyak6-274/+325
Add color module to diagnostic compilation Signed-off-by: Vitaly Prosyak <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: Reset MPCC muxes during initEric Bernstein4-49/+35
During HW initialization, instead of assuming or detecting the existing MPCC mux configuration and then removing existing planes, reset all the MPCC muxes. Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: CNVC pseudocode review follow upYue Hin Lau4-247/+244
Signed-off-by: Yue Hin Lau <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: Disable plane right after disconnectedYongqiang Sun1-1/+2
HDR display playing video underflow is observed when switching to full screen due to program a lower watermark right after unlock otg. Instead of disable plane in next flip coming, if there is a plane disconnected, after otg unlock wait for mpcc idle and disable the plane, then program watermark. So there is enough warter mark to make sure current frame data pass through. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: dal 3.1.23Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: Clean up os_types.h a bitHarry Wentland1-6/+2
Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: Fix access of wrong array element TF format conversionHarry Wentland1-2/+2
Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:357 convert_to_custom_float() error: buffer overflow 'arr_points' 2 <= 2 drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:358 convert_to_custom_float() warn: buffer overflow 'arr_points' 2 <= 2 Regression: drm/amd/display: Remove extra arr_points element Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: dal 3.1.22Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: Add dcc_change surface update flagAndrew Jiang3-0/+7
Program the DCC registers when dcc_change is true. Signed-off-by: Andrew Jiang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: Implement work around for optc underflow.Yongqiang Sun5-11/+62
Work around for a hw bug causing optc underflow if blank data double buffer disable and remove mpcc. Checking optc status after otg unlock, after wait mpcc idle check status again, if optc underflow just happens after wait mpcc idle, clear underflow status and enable blank data double buffer. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: Change optimized_required logicAndrew Jiang1-0/+3
Rather than setting it every time there's a full update with surface count > 0, set it when we need to do plane_atomic_disconnect. Also make sure that we unset the flag in plane_atomic_disable, so that in the event we run through a sequence where we do disconnect followed by an immediate disable, we do not do unnecessarily request a passive flip to do the optimization. Signed-off-by: Andrew Jiang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: Add optimized_required flagHarry Wentland2-0/+4
Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Leo (Sunpeng) Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: Use same wait mpcc idle function.Yongqiang Sun1-15/+12
There is already wait mpcc idle function. It is better to use the same function for all wait mpcc idle. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: MPC updatesEric Bernstein2-5/+8
Fix update_mpcc logic to only call assert_mpcc_idle_before_connect if mpcc is not already being used (and required removal). Update set_out_rate_control to include optional flow control parameter. In init_mpcc_from_hw check for case where bot_sel is same as mpcc_id. Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: Fixed read wrong reg to get bot_sel.Yongqiang Sun1-1/+1
Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: Fix potential mem leak in DC constructHarry Wentland1-16/+18
Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:506 construct() warn: possible memory leak of 'dc_ctx' drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:506 construct() warn: possible memory leak of 'dc_vbios' drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:506 construct() warn: possible memory leak of 'dcn_ip' drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:506 construct() warn: possible memory leak of 'dcn_soc' Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: Remove redundant checks in set_default_colorsHarry Wentland1-10/+2
pipe_ctx->stream and pipe_ctx->plane_state are never NULL Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2111 set_default_colors() error: we previously assumed 'pipe_ctx->stream' could be null (see line 2101) Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: Remove plane_res.mi check in dce110_apply_ctx_for_surfaceHarry Wentland1-7/+6
plane_res.mi (memory interface) can never be NULL for DCE110 Found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/dce110/dce110_hw_sequencer.c:2881 dce110_apply_ctx_for_surface() error: we previously assumed 'pipe_ctx->plane_res.mi' could be null (see line 2873) Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: Remove PSR functions in LinuxHarry Wentland1-138/+0
NULL check issue found by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link.c:1976 dc_link_setup_psr() warn: variable dereferenced before check 'link' (see line 1970) We don't use these functions so might as well remove them. Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: Integrating MPC pseudocodeEric Bernstein7-356/+594
Integrating MPC pseudocode to support new blending cases with secondary MPCC list. This includes a design change to MPC data structures and interfaces. Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: dal 3.1.21Tony Cheng1-1/+1
Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: try to find matching audio inst for enc inst firstCharlene Liu1-3/+1
[Description] in eDP+ HDMI/DP clone or extended configuration, audio inst changed from inst 1 to inst0. No failure related this though, just playback device endpoint inst changed. Also remove one addition register read. Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: fix seq issue: turn on clock before programming afmt.Charlene Liu1-1/+3
Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Krunoslav Kovac <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/display: Remove unnecessary wait mpcc idle.Yongqiang Sun1-6/+0
Before power gate plane, mpcc idle wait is processed, no need to wait another time. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-14drm/amd/pp: reset dpm level when adjust power stateRex Zhu1-1/+1
Acked-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-13drm/amd/pp: implement dpm_get_sclk/mclk for RVRex Zhu1-2/+23
RV implementation was missing these callbacks. Used to fetch the clock values for other components. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-13drm/amdgpu: fix huge page setting for ATS caseChunming Zhou1-1/+1
Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-13drm/amdgpu: drop amdgpu_atombios_scratch_regs_save/restoreAlex Deucher2-24/+0
No longer used. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-13drm/amdgpu: drop scratch regs save and restore from GPU reset handlingAlex Deucher1-2/+0
The expectation is that the base driver doesn't mess with these. Some components interact with these directly so let the components handle these directly. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-13drm/amdgpu: drop scratch regs save and restore from S3/S4 handlingAlex Deucher1-2/+0
The expectation is that the base driver doesn't mess with these. Some components interact with these directly so let the components handle these directly. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-13drm/amdgpu: remove some old gc 9.x registersAlex Deucher5-84/+4
Leftover from bring up. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-13drm/amdgpu: drop soc15_init_golden_registersAlex Deucher1-31/+0
The golden register arrays were empty so the function was effectively useless. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-13drm/amdgpu: drop the bios scratch reg callbacks from nbioAlex Deucher3-31/+0
They are not used any longer. We get the scratch register locations from the vbios directly now. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-13drm/amdgpu: convert nbio to use callbacks (v2)Alex Deucher11-183/+209
Cleans up and consolidates all of the per-asic logic. v2: squash in "drm/amdgpu: fix NULL err for sriov detect" (Chunming) Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-12drm/amdgpu: make function names consistent in nbio filesAlex Deucher2-16/+16
All functions should have nbio_v* prefix. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-12drm/amdgpu: correct vce fw data and stack sizeFrank Min1-1/+1
this fix the VCE world switch hang issue Signed-off-by: Frank Min <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-12drm/amdgpu: fix MAP_QUEUES paramterMonk Liu1-1/+1
Should be 0. Signed-off-by: Monk Liu <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-12drm/amdgpu: no need with INT for fence pollingMonk Liu1-1/+1
We are polling so no need for INT. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-12drm/amdgpu: no need to evict VRAM in device_finiMonk Liu1-2/+1
this VRAM evict is not needed and also cost 2seconds to finish because the IRQ is software side disabled before it. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-12drm/amdgpu: allow get_vm_pde to change flags as wellChristian König11-38/+54
And also provide the level for which we need a PDE. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-12drm/amdgpu: batch PDE updates againChristian König1-109/+94
Now instead of one submission for each PDE batch them together over all PDs who need an update. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-12drm/amdgpu: remove keeping the addr of the VM PDsChristian König2-10/+5
No more double house keeping. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-12drm/amdgpu: remove last_entry_used from the VM codeChristian König2-24/+29
Not needed any more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-12drm/amdgpu: avoid the modulo in amdgpu_vm_get_entryChristian König1-3/+3
We can do this with a simple mask as well. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-12drm/amdgpu: use polling mem to set SDMA3 wptr for VFPixel Ding2-8/+20
On Tonga VF, there're 2 sources updating wptr registers for sdma3: 1) polling mem and 2) doorbell. When doorbell and polling mem are both enabled on sdma3, there will be collision hit in occasion between those two sources when ucode and h/w are doing the updating on wptr register in parallel. Issue doesn't happen on CP GFX/Compute since CP drops all doorbell writes when VF is inactive. So enable polling mem and don't use doorbell for SDMA3. Signed-off-by: Pixel Ding <[email protected]> Reviewed-by: Monk Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-12drm/amdgpu: update one PDE at a time v2Christian König1-46/+34
Horrible inefficient, but avoids problems when the root PD size becomes to big. v2: remove incr as well. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-12drm/amdgpu: stop joining PDEsChristian König1-34/+7
That doesn't hit any more most of the time anyway. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-12drm/amdgpu: add amdgpu_evict_vram debugfs fileChristian König1-1/+12
Torture test for MM and VM support, can be used to evict all VRAM while the system is under load. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-12drm/amdgpu: cleanup debugfs handling a bitChristian König3-43/+11
Remove the superflous .debugfs_init callback and register all files in amdgpu_device.c in just one function. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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