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path: root/drivers/gpu/drm/amd
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2020-07-15drm/amdgpu: add smu block for navy_flounderJiansong Chen1-0/+3
Add SMU block for navy_flounder with direct firmware load type. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu/powerplay: add smu support for navy_flounderJiansong Chen3-1/+16
Now navy_flounder will reuse the smu11 driver_if header and ppt functions for sienna_cichlid. Later navy_flounder can maintain its own version if the compatibility is broken. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add gmc cg support for navy_flounderJiansong Chen2-2/+5
The athub version used for navy_flounder is v2.1. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: force pa_sc_tile_steering_override to 0 for navy_flounderJiansong Chen1-1/+2
pa_sc_tile_steering_override is only programmable for gfx10.0/10.1/10.2, and navy_flounder has the same gfx10.3 IP with sienna_cichlid. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: configure navy_flounder gfx according to gfx 10.3Tao Zhou1-0/+9
The gfx version of navy_flounder is 10.3, identical to sienna_cichlid, follow the way of sienna_cichlid. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add virtual display support for navy_flounder.Jiansong Chen1-0/+2
Virtual display support for bring up and virtualization. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add sdma ip block for navy_flounderJiansong Chen2-2/+19
Navy_Flounder has the same sdma IP version with sienna_cichlid, and it has 2 sdma controllers. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add gfx ip block for navy_flounderJiansong Chen2-0/+5
since navy_flounder has similar gc IP version with sienna_cichlid, follow its setting for the moment. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add ih ip block for navy_flounderJiansong Chen2-0/+2
navy_flounder has the same osssys IP verison with sienna_cichlid, follow its setting. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add gmc ip block for navy_flounderJiansong Chen2-6/+13
navy_flounder has similar gc IP version with sienna_cichlid, follow its setting for the moment. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add common ip block for navy_flounderJiansong Chen1-0/+3
Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add support on mmhub for navy_flounderJiansong Chen1-0/+5
navy_flounder has the same mmhub IP version with sienna_cichlid, follow its setting. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: initialize IP offset for navy_flounderJiansong Chen1-0/+1
since navy_flounder has the same ip offset with sienna_cichlid, follow sienna_cichlid setting for the moment. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu/soc15: add support for navy_flounderJiansong Chen1-0/+7
Add soc support. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu/gfx10: add clockgating support for navy_flounderJiansong Chen1-0/+1
Same as navi10. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu/gmc10: add navy_flounder supportJiansong Chen1-0/+3
Same as navi10. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu/gfx10: add support for navy_flounder firmwareJiansong Chen1-0/+10
Declare the gfx/compute firmwares. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: set asic family and ip blocks for navy_flounderJiansong Chen1-0/+1
Add the asic family and IP blocks for navy flounder. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: set fw load type for navy_flounderJiansong Chen1-1/+2
Currently navy_flounder only supports backdoor loading type. Will switch to psp load type when psp is ready. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add navy_flounder gpu info firmwareJiansong Chen1-0/+4
Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add navy_flounder asic typeJiansong Chen1-0/+1
Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: expand to add multiple trap event irq idHuang Rui1-26/+41
Sienna_cichlid has four sdma instances, but other chips don't. So we need expand to add multiple trap event irq id in sdma v5.2. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/sriov skip vcn powergating and dec_ring_testJack Zhang2-5/+20
1.Skip decode_ring test in VF, because VCN in SRIOV does not support direct register read/write. 2.Skip powergating configuration in hw fini because VCN3.0 SRIOV doesn't support powergating. V2: delete unneccessary white lines and refine implementation. Signed-off-by: Jack Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: correct ta header v2 ucode init start addressJohn Clements1-1/+3
resolve bug calculating fw start address within binary Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/sriov porting sriov cap to vcn3.0Jack Zhang1-32/+318
1.In early_init and for sriov, hardcode harvest_config=0, enc_num=1 2.sw_init/fini alloc & free mm_table for sriov doorbell setting for sriov 3.hw_init/fini Under sriov, add start_sriov to config mmsch Skip ring_test to avoid mmio in VF, but need to initialize wptr for vcn rings. 4.Implementation for vcn_v3_0_start_sriov V2:Clean-up some uneccessary funciton declaration. Signed-off-by: Jack Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/sriov add mmsch_v3 interfaceJack Zhang1-0/+130
For VCN3.0 SRIOV, Guest driver needs to communicate with mmsch to set the World Switch for MM appropriately. This patch add the interface for mmsch_v3.0. Signed-off-by: Jack Zhang <[email protected]> Reviewed-by: Dennis Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: optimize rlcg write for gfx_v10Jack Zhang1-7/+19
For gfx10 boards, except for nv12, other boards take mmio write rather than rlcg write Signed-off-by: Jack Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/sriov skip jped ip block and close pgcg flagsJack Zhang1-1/+8
For SIENNA_CICHLID SRIOV, jpeg and pgcp is not supported. Signed-off-by: Jack Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: drop unused code around thermal range settingEvan Quan6-113/+3
Leftover of previous cleanups. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: maximum the code sharing on thermal irq settingEvan Quan1-4/+12
Put the common code in smu_v11_0.c instead of having one copy each. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: sort the call flow on temperature ranges retrievingEvan Quan7-20/+41
This can help to maintain clear code layer. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: cache the software_shutdown_tempEvan Quan4-0/+13
As it's needed in the succeeding thermal irq setting. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: correct Sienna Cichlid temperature limit settingsEvan Quan1-4/+13
These are needed for temp1/2/3 related hwmon interfaces. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: correct Navi1X temperature limit settingsEvan Quan3-9/+18
These are needed for temp1/2/3 related hwmon interfaces. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: correct the supported pcie GenSpeed and LaneCountEvan Quan2-20/+14
The LCLK dpm table setup should be performed in .update_pcie_parameters(). Otherwise, the updated GenSpeed and LaneCount information will be lost. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: drop unnecessary wrapper around pcie parameters settingEvan Quan8-51/+31
This can also help to maintain clear code layer. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: drop unused APIs and parametersEvan Quan5-30/+10
Leftover of previous performance level setting cleanups. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: drop smu_v12_0.c unnecessary wrapper V2Evan Quan4-168/+177
By moving the implemention to renoir_ppt.c considering it's really ASIC specific. V2: fix compile warnings below drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.h:40:25: warning: array subscript is above array bounds [-Warray-bounds] freq = table->FClocks[dpm_level].Freq; \ drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.c:195:2: note: in expansion of macro ‘GET_DPM_CUR_FREQ’ GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq); ^~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.h:46:25: warning: array subscript is above array bounds [-Warray-bounds] freq = table->FClocks[dpm_level].Freq; \ drivers/gpu/drm/amd/amdgpu/../powerplay/renoir_ppt.c:195:2: note: in expansion of macro ‘GET_DPM_CUR_FREQ’ GET_DPM_CUR_FREQ(clk_table, clk_type, dpm_level, *freq); Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: drop unnecessary wrappersEvan Quan1-12/+10
By calling the target APIs directly. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: apply gfxoff disablement/enablement for all SMU11 ASICsEvan Quan1-4/+2
Before and after setting gfx clock soft max/min frequency. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: drop Sienna Cichlid specific set_soft_freq_limited_rangeEvan Quan3-23/+18
Use the common smu_v11_0_set_soft_freq_limited_range. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: drop unnecessary Sienna Cichlid specific APIsEvan Quan1-177/+1
As a common performance level setting API is used. Then these ASIC specific APIs are not needed any more. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: drop unnecessary Navi1x specific APIsEvan Quan1-247/+1
As a common performance level setting API is used. Then these ASIC specific APIs are not needed any more. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: drop unnecessary Arcturus specific APIsEvan Quan1-170/+0
As a common performance level setting API is used. Then these ASIC specific APIs are not needed any more. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: update the common API for performance level settingEvan Quan1-14/+77
So that it can be more widely shared around SMU v11 ASICs. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: update UMD pstate clock settingsEvan Quan4-46/+141
Preparing for coming code sharing around performance level setting. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: add new UMD pstate data structureEvan Quan1-0/+15
This is used to cache the clock frequencies for all UMD pstates. So that we do not need to calculate from scratch on every UMD pstate switch. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: update Sienna Cichlid default dpm table setupEvan Quan1-23/+211
Cache all clocks levels for every dpm table. They are needed by other APIs. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: update Navi10 default dpm table setupEvan Quan1-24/+158
Cache all clocks levels for every dpm table. They are needed by other APIs. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: update Arcturus default dpm table settingEvan Quan1-178/+119
Preparing for coming code sharing around performance level setting. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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