aboutsummaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd
AgeCommit message (Collapse)AuthorFilesLines
2020-08-06drm/amd/display: Fix naming of DSC Debugfs entryEryk Brol1-4/+5
[why] Fix naming and return bits rather than bytes per pixel for naming consistency. Because registers return Bytes per pixel, but DSC Config structure is expecting bits per pixel as input. So when returning the value convert from bytes into bits. Signed-off-by: Eryk Brol <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Reviewed-by: Mikita Lipski <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/display: Rename bytes_pp to the correct bits_ppEryk Brol4-4/+6
[Why] Struct dcn_dsc_state is used for reading current state and parameters of DSC on a pipe, the target rate parameter uses bytes per pixel even though its reading BITS_PER_PIXEL register. [How] Changing it to Bits Per Pixel for consistency. Signed-off-by: Eryk Brol <[email protected]> Signed-off-by: Mikita Lipski <[email protected]> Reviewed-by: Mikita Lipski <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/display: Clean up global sync param retrievalDmytro Laktyushkin3-63/+7
[Why] This change replaces older looping code in favor of these functions. [How] There are built in functions for extracting global sync params during mode validation now. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Acked-by: Eryk Brol <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/swsmu: allow asic to handle sensor type by itselfKevin Wang1-2/+7
1. allow asic to handle sensor type by itself. 2. if not, use smu common sensor to handle it. Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: off by one bugs in smu_cmn_to_asic_specific_index()Dan Carpenter1-5/+5
These tables have _COUNT number of elements so the comparisons should be >= instead of > to prevent reading one element beyond the end of the array. Fixes: 8264ee69f0d8 ("drm/amd/powerplay: drop unused code") Signed-off-by: Dan Carpenter <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: update driver if file for sienna_cichlidLikun Gao3-10/+24
Update sienna_cichlid driver if header and related files. Support new smu metrics for pre & postDS frequency. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: drop unnecessary message support check(v2)Changfeng2-10/+1
Take back patch:drop unnecessary message support check Because the gpu reset fail problem on renoir can be fixed by: drm/amd/powerplay: skip invalid msg when smu set mp1 state It needs to remove SWSMU_CODE_LAYER_L1 in smu_cmn.h to guard a clear code layer. Signed-off-by: changfeng <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amdgpu: update dec ring test for VCN 3.0Boyuan Zhang1-1/+1
Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amdgpu/jpeg3.0: remove extra asic type checkJames Zhu1-5/+4
jpeg ip block is already selected based on ASIC type during set_ip_blocks. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amdgpu: update golden setting for sienna_cichlidLikun Gao1-1/+1
Update golden setting for sienna_cichlid. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: correct smu message for vf modeLikun Gao1-35/+35
Set valid_in_vf to false for the message not support in vf mode on sienna cichlid. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: add msg map for mode1 resetLikun Gao1-0/+1
Mapping Mode1Reset message for sienna_cichlid. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: skip invalid msg when smu set mp1 stateLikun Gao1-0/+3
Some asic may not support for some message of set mp1 state. If the return value of smu_send_smc_msg is -EINVAL, that means it failed to send msg to smc as it can not map an valid message for the ASIC. And with that case, smu_set_mp1_state should be skipped as those ASIC was in fact do not support for that. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: remove the dpm checking in the boot sequenceKenneth Feng1-1/+1
It's not necessary to retrieve the power features status when the asic is booted up the first time. This patch can have the features enablement status still checked in suspend/resume case and removed from the first boot up sequence. Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06Revert "drm/amd/powerplay: drop unnecessary message support check"Changfeng2-1/+10
The below 3 messages are not supported on Renoir SMU_MSG_PrepareMp1ForShutdown SMU_MSG_PrepareMp1ForUnload SMU_MSG_PrepareMp1ForReset It needs to revert patch: drm/amd/powerplay: drop unnecessary message support check to avoid set mp1 state fail during gpu reset on renoir. Signed-off-by: changfeng <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amdgpu: add printing after executing page reservation to eepromGuchun Chen1-1/+4
This will tell users if the faulty page has been written to external eeprom device in dmesg log. Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amdgpu: expand sienna chichlid reg access supportJohn Clements1-0/+45
Added dedicated 64bit reg read/write support Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amdgpu: fix spelling mistake "Falied" -> "Failed"Colin Ian King1-1/+1
There is a spelling mistake in a DRM_ERROR error message. Fix it. This got lost in a merge, restore the fix. Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]> (cherry picked from commit 4afaa61db9cf5250b5734c2531b226e7b3a3d691)
2020-08-06drm/amd/display: Drop dm_determine_update_type_for_commitNicholas Kazlauskas1-182/+17
[Why] This was added in the past to solve the issue of not knowing when to stall for medium and full updates in DM. Since DC is ultimately decides what requires bandwidth changes we wanted to make use of it directly to determine this. The problem is that we can't actually pass any of the stream or surface updates into DC global validation, so we don't actually check if the new configuration is valid - we just validate the old existing config instead and stall for outstanding commits to finish. There's also the problem of grabbing the DRM private object for pageflips which can lead to page faults in the case where commits execute out of order and free a DRM private object state that was still required for commit tail. [How] Now that we reset the plane in DM with the same conditions DC checks we can have planes go through DC validation and we know when we need to check and stall based on whether the stream or planes changed. We mark lock_and_validation_needed whenever we've done this, so just go back to using that instead of dm_determine_update_type_for_commit. Since we'll skip resetting the plane for a pageflip we will no longer grab the DRM private object for pageflips as well, avoiding the page fault issued caused by pageflipping under load with commits executing out of order. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/display: Reset plane for anything that's not a FAST updateNicholas Kazlauskas1-0/+25
[Why] MEDIUM or FULL updates can require global validation or affect bandwidth. By treating these all simply as surface updates we aren't actually passing this through DC global validation. [How] There's currently no way to pass surface updates through DC global validation, nor do I think it's a good idea to change the interface to accept these. DC global validation itself is currently stateless, and we can move our update type checking to be stateless as well by duplicating DC surface checks in DM based on DRM properties. We wanted to rely on DC automatically determining this since DC knows best, but DM is ultimately what fills in everything into DC plane state so it does need to know as well. There are basically only three paths that we exercise in DM today: 1) Cursor (async update) 2) Pageflip (fast update) 3) Full pipe programming (medium/full updates) Which means that anything that's more than a pageflip really needs to go down path #3. So this change duplicates all the surface update checks based on DRM state instead inside of should_reset_plane(). Next step is dropping dm_determine_update_type_for_commit and we no longer require the old DC state at all for global validation. Optimization can come later so we don't reset DC planes at all for MEDIUM udpates and avoid validation, but we might require some extra checks in DM to achieve this. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/display: Use validated tiling_flags and tmz_surface in commit_tailNicholas Kazlauskas1-14/+3
[Why] So we're not racing with userspace or deadlocking DM. [How] These flags are now stored on dm_plane_state itself and acquried and validated during commit_check, so just use those instead. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/display: Avoid using unvalidated tiling_flags and tmz_surface in ↵Nicholas Kazlauskas1-17/+19
prepare_planes [Why] We're racing with userspace as the flags could potentially change from when we acquired and validated them in commit_check. [How] We unfortunately can't drop this function in its entirety from prepare_planes since we don't know the afb->address at commit_check time yet. So instead of querying new tiling_flags and tmz_surface use the ones from the plane_state directly. While we're at it, also update the force_disable_dcc option based on the state from atomic check. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/display: Reset plane when tiling flags changeNicholas Kazlauskas1-3/+16
[Why] Enabling or disable DCC or switching between tiled and linear formats can require bandwidth updates. They're currently skipping all DC validation by being treated as purely surface updates. [How] Treat tiling_flag changes (which encode DCC state) as a condition for resetting the plane. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/display: Store tiling_flags and tmz_surface on dm_plane_stateNicholas Kazlauskas2-25/+37
[Why] Store these in advance so we can reuse them later in commit_tail without having to reserve the fbo again. These will also be used for checking for tiling changes when deciding to reset the plane or not. [How] This change should mostly be a refactor. Only commit check is affected for now and I'll drop the get_fb_info calls in prepare_planes and commit_tail after. This runs a prepass loop once we think that all planes have been added to the context and replaces the get_fb_info calls with accessing the dm_plane_state instead. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: update driver if file for sienna_cichlidLikun Gao2-4/+4
Update drive if file for sienna_cichlid. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amdgpu: new ids flag for tmz (v2)Pierre-Eric Pelloux-Prayer2-1/+4
Allows UMD to know if TMZ is supported and enabled. This commit also bumps KMS_DRIVER_MINOR because if we don't UMD can't tell if "ids_flags & AMDGPU_IDS_FLAGS_TMZ == 0" means "tmz is not enabled" or "tmz may be enabled but the kernel doesn't report it". v2: use amdgpu_is_tmz() and reworded commit message. Signed-off-by: Pierre-Eric Pelloux-Prayer <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: add control method to bypass metrics cache on Vega12Evan Quan1-11/+18
As for the gpu metric export, metrics cache makes no sense. It's up to user to decide how often the metrics should be retrieved. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: add control method to bypass metrics cache on Vega20Evan Quan1-12/+19
As for the gpu metric export, metrics cache makes no sense. It's up to user to decide how often the metrics should be retrieved. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: add control method to bypass metrics cache on RenoirEvan Quan1-8/+14
As for the gpu metric export, metrics cache makes no sense. It's up to user to decide how often the metrics should be retrieved. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: add control method to bypass metrics cache on Sienna CichlidEvan Quan1-24/+49
As for the gpu metric export, metrics cache makes no sense. It's up to user to decide how often the metrics should be retrieved. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: add control method to bypass metrics cache on Navi10Evan Quan1-22/+38
As for the gpu metric export, metrics cache makes no sense. It's up to user to decide how often the metrics should be retrieved. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: add control method to bypass metrics cache on ArcturusEvan Quan1-25/+49
As for the gpu metric export, metrics cache makes no sense. It's up to user to decide how often the metrics should be retrieved. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: add Vega12 support for gpu metrics exportEvan Quan2-0/+112
Add Vega12 gpu metrics export interface. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: add Vega20 support for gpu metrics exportEvan Quan2-7/+117
Add Vega20 gpu metrics export interface. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: enable gpu_metrics export on legacy powerplay routinesEvan Quan2-0/+20
Enable gpu_metrics support on legacy powerplay routines. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: add Renoir support for gpu metrics export(V2)Evan Quan3-3/+91
Add Renoir gpu metrics export interface. V2: use memcpy to make code more compact Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: add Sienna Cichlid support for gpu metrics exportEvan Quan1-2/+89
Add Sienna Cichlid gpu metrics export interface. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: add Navi1x support for gpu metrics exportEvan Quan1-2/+91
Add Navi1x gpu metrics export interface. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: update the data structure for NV12 SmuMetricsEvan Quan2-3/+54
Although it does not bring any problem for now, the coming gpu metrics interface needs to handle them differently based on the asic type. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: add Arcturus support for gpu metrics exportEvan Quan4-0/+111
Add Arcturus gpu metrics export interface. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: implement SMU V11 common APIs for retrieving link speed/widthEvan Quan6-19/+65
This will be shared around all SMU V11 asics. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: add new sysfs interface for retrieving gpu metrics(V2)Evan Quan5-0/+84
A new interface for UMD to retrieve gpu metrics data. V2: rich the documentation Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: define an universal data structure for gpu metrics (V4)Evan Quan1-0/+108
Thus we can provide an interface for UMD to retrieve gpu metrics data. V2: better naming and comments V3: two structures created for dGPU and APU separately V4: add driver attached timestamp Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amdgpu: fix spelling mistake "paramter" -> "parameter"Colin Ian King1-1/+1
There is a spelling mistake in a dev_warn message. Fix it. Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/powerplay: grant Arcturus softmin/max setting on latest PM firmwareEvan Quan1-4/+6
For Arcturus, the softmin/max settings from driver are permitted on the latest(54.26 later) SMU firmware. Thus enabling them in driver. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amdkfd: option to disable system mem limitPhilip Yang3-1/+16
If multiple process share system memory through /dev/shm, KFD allocate memory should not fail if it reaches the system memory limit because one copy of physical system memory are shared by multiple process. Add module parameter no_system_mem_limit to provide user option to disable system memory limit check at runtime using sysfs or during driver module init using kernel boot argument. By default the system memory limit is on. Print out debug message to warn user if KFD allocate memory failed because system memory reaches limit. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06drm/amd/display: Fix wrong return value in dm_update_plane_state()Tianjia Zhang1-2/+1
On an error exit path, a negative error code should be returned instead of a positive return value. Fixes: 9e869063b0021 ("drm/amd/display: Move iteration out of dm_update_planes") Cc: Leo Li <[email protected]> Signed-off-by: Tianjia Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-06Merge branch 'WIP.locking/seqlocks' into locking/urgentIngo Molnar1-2/+0
Pick up the full seqlock series PeterZ is working on. Signed-off-by: Ingo Molnar <[email protected]>
2020-08-06drm/ttm: rename ttm_mem_reg to ttm_resource.Dave Airlie7-41/+41
This name better reflects what the object does. I didn't rename all the pointers it seemed too messy. Signed-off-by: Dave Airlie <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-08-06drm/ttm: rename ttm_mem_type_manager -> ttm_resource_manager.Dave Airlie8-47/+47
This name makes a lot more sense, since these are about managing driver resources rather than just memory ranges. Acked-by: Christian König <[email protected]> Reviewed-by: Ben Skeggs <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
Powered by cgit, Gruvboxed by Blaster4385.