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2023-08-30drm/amd/display: Add DCN35 initQingqing Zhuo2-0/+199
[Why & How] Add init files for DCN35. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add DCN35 DMUBQingqing Zhuo7-2/+999
[Why & How] Add DMUB handling for DCN35. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add DCN35 IRQQingqing Zhuo19-109/+579
[Why & How] - Add IRQ handling for DCN35 - Update IRQ files for other DCNs in accordance to change in irq_service.h Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add DCN35 CLK_MGRQingqing Zhuo11-0/+1717
[Why & How] Add CLK_MGR handling for DCN35. v2: Drop stale SMU interfaces (Alex) Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add DCN35 HWSEQQingqing Zhuo3-0/+1285
[Why & How] Add HWSEQ handling for DCN35. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add DCN35 DSCQingqing Zhuo2-0/+115
[Why & How] Add DSC handling for DCN35. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add DCN35 MMHUBBUBQingqing Zhuo2-0/+130
[Why & How] Add MMHUBBUB handling for DCN35. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add DCN35 HUBBUBQingqing Zhuo2-0/+723
[Why & How] Add HUBBUB handling for DCN35. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add DCN35 HUBPQingqing Zhuo2-0/+163
[Why & How] Add HUBP handling for DCN35. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add DCN35 DWBQingqing Zhuo2-0/+117
[Why & How] Add DWB handling for DCN35. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add DCN35 DPPQingqing Zhuo2-0/+106
[Why & How] Add DPP handling for DCN35. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add DCN35 OPPQingqing Zhuo2-0/+116
[Why & How] Add OPP handling for DCN35. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add DCN35 OPTCQingqing Zhuo2-0/+503
[Why & How] Add OPTC handling for DCN35. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add DCN35 PG_CNTLQingqing Zhuo4-0/+800
[Why & How] Add PG_CNTL handling for DCN35. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add DCN35 DIOQingqing Zhuo6-0/+1286
[Why & How] Add DIO handling for DCN35. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add DCN35 DCCGQingqing Zhuo2-0/+927
[Why & How] Add DCCG handling for DCN35. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add DCN35 GPIOQingqing Zhuo2-0/+2
[Why & How] Add DCN35 support in GPIO. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add DCN35 BIOS command table supportQingqing Zhuo1-0/+1
[Why & How] Add case for DCN35 in command_table_helper2.c. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Update dc.h for DCN35 supportQingqing Zhuo1-0/+56
[Why & How] Update dc.h for DCN35 usage. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Update DCN32 for DCN35 supportQingqing Zhuo4-9/+0
[Why & How] Update DCN32 files for DCN35 usage. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Update DCN314 for DCN35 supportQingqing Zhuo4-12/+58
[Why & How] Update DCN314 files for DCN35 usage. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Update DCN31 for DCN35 supportQingqing Zhuo3-2/+17
[Why & How] Update DCN31 files for DCN35 usage. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Update DCN30 for DCN35 supportQingqing Zhuo2-4/+0
[Why & How] Update DCN30 files for DCN35 usage. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Update DCN20 for DCN35 supportQingqing Zhuo4-2/+77
[Why & How] Update DCN20 files for DCN35 usage. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Update DCN10 for DCN35 supportQingqing Zhuo4-2/+85
[Why & How] Update DCN10 files for DCN35 usage. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Update DCE for DCN35 supportQingqing Zhuo4-3/+36
[Why & How] Update DCE files for DCN35 usage. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add DCN35 family informationQingqing Zhuo2-0/+6
[Why & How] Add DCN35 family information in DC. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add dcn35 register header filesQingqing Zhuo2-0/+68667
[Why & How] Add register headers for DCN35. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amdgpu: Support query ecc cap for aqua_vanjaramHawking Zhang1-2/+16
Driver queries umc_info v4_0 to identify ecc cap for aqua_vanjaram Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Candice Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amdgpu: Add umc_info v4_0 structureHawking Zhang1-0/+18
To be used by aqua_vanjaram Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Candice Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Fix up kdoc format for 'dc_set_edp_power'Srinivasan Shanmugam1-2/+5
Fixes the following W=1 kernel build warning: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc.c:5261: warning: Cannot understand ******************************************* Cc: Ian Chen <[email protected]> Cc: Rodrigo Siqueira <[email protected]> Cc: Harry Wentland <[email protected]> Cc: Aurabindo Pillai <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: always switch off ODM before committing more streamsWenjing Liu1-5/+5
ODM power optimization is only supported with single stream. When ODM power optimization is enabled, we might not have enough free pipes for enabling other stream. So when we are committing more than 1 stream we should first switch off ODM power optimization to make room for new stream and then allocating pipe resource for the new stream. Cc: [email protected] Fixes: 59de751e3845 ("drm/amd/display: add ODM case when looking for first split pipe") Reviewed-by: Dillon Varone <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: 3.2.249Martin Leung1-1/+1
This version brings along the following: - DCN315 fixes - DCN31 fixes - DPIA fixes - Dump the pipe topology when it updates - Misc code cleanups - New debugfs interface to query the current ODM combine configuration - ODM fixes - Potential deadlock while waiting for MPC idle fix - Support for windowed MPO ODM Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Martin Leung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: fix pipe topology logging errorWenjing Liu1-4/+3
[why] There is a logging error in the recently added pipe topology log. If the plane with index 0 uses MPC combine, the log shows that as two separate planes. [how] Initialize plane idx as -1 and increment plane idx before logging any primary dpp pipes of a plane. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add debugfs interface for ODM combine infoAurabindo Pillai4-1/+59
[Why] For use with IGT tests in userspace, the number of ODM segments in use is required to be exposed to userspace to verify that ODM Combine is working as expected when special timings are committed. [How] Add a connector specific debugfs entry that prints the number of ODM segments in use. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: correct z8_watermark 16bit to 20bit maskCharlene Liu1-16/+16
remove double adjustment for DPREFCLK SS. dprefclk adjusted with SS is used for dp audio only. if adjust DP_DTO, need to adjust VID_M/N Reviewed-by: Muhammad Ahmed <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Fix incorrect commentAurabindo Pillai1-2/+1
Fix incorrect comment about hardware capabilities debugfs interface. Reviewed-by: Jerry Zuo <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Skip dmub memory flush when not neededDillon Varone2-1/+10
[WHY&HOW] Readback is only necessary when loaded via CPU. Reviewed-by: Chris Park <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Remove wait while lockedGabe Teeger3-28/+42
[Why] We wait for mpc idle while in a locked state, leading to potential deadlock. [What] Move the wait_for_idle call to outside of HW lock. This and a call to wait_drr_doublebuffer_pending_clear are moved added to a new static helper function called wait_for_outstanding_hw_updates, to make the interface clearer. Cc: [email protected] Fixes: 8f0d304d21b3 ("drm/amd/display: Do not commit pipe when updating DRR") Reviewed-by: Jun Lei <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Gabe Teeger <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: add pipe topology update logWenjing Liu3-8/+168
Given an issue with pipe topology transition. It is very hard to tell the before and after pipe topology without a pipe topology logging. The change adds such logging to help with visualizing the issue. Reviewed-by: Jun Lei <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: switch to new ODM policy for windowed MPO ODM supportWenjing Liu1-19/+65
We need to align windowed MPO ODM support on DCN3x with new ODM policy. Reviewed-by: Jun Lei <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: use new pipe allocation interface in dcn32 fpuWenjing Liu1-149/+339
This commit implements a new pipe resource allocation logic for DCN32 when windowed ODM MPO flag is set to enable testing. By default the flag is not set. It will be toggled on after we complete testing. Reviewed-by: Jun Lei <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: add more pipe resource interfacesWenjing Liu18-464/+659
Redesign pipe resource interfaces in resource.h file. The new interface design addresses the issue with lack of pipe topology encapsulation and lack of pipe accessors. Reviewed-by: Jun Lei <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: add new resource interfaces to update odm mpc slice countWenjing Liu2-6/+432
Define two new interfaces to update mpc and odm slice count. Reviewed-by: Jun Lei <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: add new resource interface for acquiring sec opp heads and ↵Wenjing Liu5-0/+134
release pipe [why] We need a new algorithm for acquiring secondary opp heads for ODM combine in dcn32 and a release pipe interface to properly release pipe resources. [how] add two new interfaces in DCN specific resource file. Reviewed-by: Jun Lei <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: rename function to add otg master for streamWenjing Liu1-44/+69
We are renaming acquire first free pipe to add otg master pipe for stream because the former name doesn't indicate that it acquires the first free pipe to use as an otg master pipe. This could cause coding errors if someone uses it to acquire a different pipe type. Reviewed-by: Jun Lei <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: add comments to add plane functionsWenjing Liu1-21/+70
Adding detail comments describing the problem we are solving with add plane function. Reviewed-by: Jun Lei <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add DPIA Link Encoder Assignment FixMustapha Ghaddar5-6/+58
For DPIA we should have preferred DIG assignment based on DPIA selected as per the ASIC design. Reviewed-by: George Shen <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Mustapha Ghaddar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: update blank state on ODM changesWenjing Liu1-27/+9
When we are dynamically adding new ODM slices, we didn't update blank state, if the pipe used by new ODM slice is previously blanked, we will continue outputting blank pixel data on that slice causing right half of the screen showing blank image. The previous fix was a temporary hack to directly update current state when committing new state. This could potentially cause hw and sw state synchronization issues and it is not permitted by dc commit design. Cc: [email protected] Fixes: 7fbf451e7639 ("drm/amd/display: Reinit DPG when exiting dynamic ODM") Reviewed-by: Dillon Varone <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add smu write msg id fail retry processFudong Wang1-4/+16
A benchmark stress test (12-40 machines x 48hours) found that DCN315 has cases where DC writes to an indirect register to set the smu clock msg id, but when we go to read the same indirect register the returned msg id doesn't match with what we just set it to. So, to fix this retry the write until the register's value matches with the requested value. Cc: [email protected] # 6.1+ Fixes: f94903996140 ("drm/amd/display: Add DCN315 CLK_MGR") Reviewed-by: Charlene Liu <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Fudong Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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