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2023-09-06drm/amdgpu: Restrict bootloader wait to SMUv13.0.6Lijo Lazar1-4/+14
Restrict the wait for boot loader steady state only to SMUv13.0.6. For older SOCs, ASIC init has a longer wait period and that takes care. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Asad Kamal <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amdgpu: Add only valid firmware version nodesLijo Lazar1-4/+29
Show only firmware version attributes that have valid version. Hide others. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Yang Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amdgpu: fix incompatible types in conditional expressionLang Yu2-2/+4
Use proper type. Fixes: 9d4346bdbc64 ("drm/amdgpu: add VPE 6.1.0 support") Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Solomon Chiu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reported-by: kernel test robot <[email protected]> Link: https://lore.kernel.org/oe-kbuild-all/[email protected] Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amdgpu: Use min_t to replace minSrinivasan Shanmugam6-14/+14
Use min_t to replace min, min_t is a bit fast because min use twice typeof. And using min_t is cleaner here since the min/max macros do a typecheck while min_t()/max_t() to an explicit type cast. Fixes the below checkpatch warning: WARNING: min() should probably be min_t() Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Cc: "Pan, Xinhui" <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amd: Add umc v12_0_0 ip headersCandice Li2-0/+128
Add umc v12_0_0 ip headers. Signed-off-by: Candice Li <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amdgpu: Update amdgpu_device_indirect_r/wreg_extCandice Li1-2/+2
Only calculate pcie_index_hi for register address greater than 32bits. Signed-off-by: Candice Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amdgpu: Add RREG64_PCIE_EXT/WREG64_PCIE_EXT functionsCandice Li3-0/+128
Add 64bits register access support on register whose address is greater than 32bits. Signed-off-by: Candice Li <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amdgpu: Declare array with strings as pointers constantSrinivasan Shanmugam2-5/+5
This warning is for the declaration of a static array, and it is recommended to declare it as type "static const char * const" instead of "static const char *". an array pointer declared as type "static const char *" can point to a different character constant because the pointer is mutable. However, if it is declared as type "static const char * const", the pointer will point to an immutable character constant, preventing it from being modified which can better ensure the safety and stability of the program. Fixes the below: WARNING: static const char * array should probably be static const char * const Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Cc: "Pan, Xinhui" <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06amdgpu/pm: Optimize emit_clock_levels for aldebaran - part 3Darren Powell1-55/+27
split switch statement into two and consolidate the common code for printing most of the types of clock speeds Signed-off-by: Darren Powell <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06amdgpu/pm: Optimize emit_clock_levels for aldebaran - part 2Darren Powell1-14/+13
Use variables to remove ternary expression in print statement and improve readability. This will help to optimize the code duplication in the switch statement Also Changed: replaced single_dpm_table->count as iterator in for loops with safer clocks_num_levels value replaced dpm_table.value usage with local var clocks_mhz Signed-off-by: Darren Powell <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06amdgpu/pm: Optimize emit_clock_levels for aldebaran - part 1Darren Powell1-68/+57
Use variables to remove the multiple nested ternary expressions and improve readability. This will help to optimize the code duplication in the switch statement Also Changed: Modify function aldebaran_get_clk_table to void function as it always returns 0 Use const string "attempt_string" to cut down on repetition Signed-off-by: Darren Powell <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06amdgpu/pm: Replace print_clock_levels with emit_clock_levels for aldebaranDarren Powell1-32/+31
Replace print_clock_levels with emit_clock_levels for aldebaran * replace .print_clk_levels with .emit_clk_levels in aldebaran_ppt_funcs * added extra parameter int *offset * removed var size, uses arg *offset instead * removed call to smu_cmn_get_sysfs_buf * errors are returned to caller * returns 0 on success additional incidental changes * changed type of vars i, now to remove comparing mismatch types * renamed var s/now/cur_value/ * switch statement default now returns -EINVAL * RAS Recovery returns -EBUSY Based on commit b06b48d7ddae ("amdgpu/pm: Implement emit_clk_levels for navi10") Signed-off-by: Darren Powell <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amd/display: clean up some inconsistent indentingsYang Li1-14/+14
drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c:288 dcn35_update_clocks() warn: inconsistent indenting Signed-off-by: Yang Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amd/display: clean up some inconsistent indentingsYang Li1-16/+16
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn35/dcn35_hwseq.c:159 dcn35_init_hw() warn: inconsistent indentig Signed-off-by: Yang Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amd/display: clean up one inconsistent indentingYang Li1-1/+1
drivers/gpu/drm/amd/amdgpu/../display/dc/dcn35/dcn35_resource.c:1877 dcn35_resource_construct() warn: inconsistent indenting Signed-off-by: Yang Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amd/display: clean up one inconsistent indentingYang Li1-1/+1
drivers/gpu/drm/amd/amdgpu/../display/dmub/src/dmub_srv.c:355 dmub_srv_hw_setup() warn: inconsistent indenting Signed-off-by: Yang Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amd/display: Remove duplicated include in dcn35_clk_mgr.cYang Li1-1/+0
./drivers/gpu/drm/amd/display/dc/clk_mgr/dcn35/dcn35_clk_mgr.c: dcn35_clk_mgr.h is included more than once. Signed-off-by: Yang Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amd/display: prevent potential division by zero errorsHamza Mahfooz1-3/+6
There are two places in apply_below_the_range() where it's possible for a divide by zero error to occur. So, to fix this make sure the divisor is non-zero before attempting the computation in both cases. Cc: [email protected] Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2637 Fixes: a463b263032f ("drm/amd/display: Fix frames_to_insert math") Fixes: ded6119e825a ("drm/amd/display: Reinstate LFC optimization") Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amd/display: Remove duplicated include in dcn35_hwseq.cYang Li1-1/+0
./drivers/gpu/drm/amd/display/dc/dcn35/dcn35_hwseq.c: clk_mgr.h is included more than once. Signed-off-by: Yang Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amd/display: Remove duplicated include in dcn35_optc.cYang Li1-1/+0
./drivers/gpu/drm/amd/display/dc/dcn35/dcn35_optc.c: dcn35_optc.h is included more than once. Signed-off-by: Yang Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amd/display: Remove duplicated include in dcn35_resource.cYang Li1-1/+0
./drivers/gpu/drm/amd/display/dc/dcn35/dcn35_resource.c: dcn31/dcn31_dio_link_encoder.h is included more than once. Signed-off-by: Yang Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amdgpu: clean up some inconsistent indentingJiapeng Chong1-3/+1
No functional modification involved. drivers/gpu/drm/amd/amdgpu/nbio_v7_11.c:34 nbio_v7_11_get_rev_id() warn: inconsistent indenting. v2: drop leftover printk (Alex) Reported-by: Abaci Robot <[email protected]> Closes: https://bugzilla.openanolis.cn/show_bug.cgi?id=6316 Signed-off-by: Jiapeng Chong <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amd/display: enable cursor degamma for DCN3+ DRM legacy gammaMelissa Wen1-0/+7
For DRM legacy gamma, AMD display manager applies implicit sRGB degamma using a pre-defined sRGB transfer function. It works fine for DCN2 family where degamma ROM and custom curves go to the same color block. But, on DCN3+, degamma is split into two blocks: degamma ROM for pre-defined TFs and `gamma correction` for user/custom curves and degamma ROM settings doesn't apply to cursor plane. To get DRM legacy gamma working as expected, enable cursor degamma ROM for implict sRGB degamma on HW with this configuration. Cc: [email protected] Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2803 Fixes: 96b020e2163f ("drm/amd/display: check attr flag before set cursor degamma on DCN3+") Signed-off-by: Melissa Wen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amdgpu: calling address translation functions to simplify codesYifan Zhang8-16/+8
Use amdgpu_gmc_vram_pa to simplify codes. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amd/pm: only poweron/off vcn/jpeg when they are valid.Yifan Zhang1-0/+23
If vcn is disabled in kernel parameters, don't touch vcn, otherwise it may cause vcn hang. v2: delete unnecessary logs v3: move "is_vcn_enabled" check to smu_dpm_setvcn/jpeg_enable (Evan) Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amd/display: limit the v_startup workaround to ASICs older than DCN3.1Hamza Mahfooz1-1/+2
Since, calling dcn20_adjust_freesync_v_startup() on DCN3.1+ ASICs can cause the display to flicker and underflow to occur, we shouldn't call it for them. So, ensure that the DCN version is less than DCN_VERSION_3_1 before calling dcn20_adjust_freesync_v_startup(). Cc: [email protected] Reviewed-by: Fangzhi Zuo <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06drm/amd/display: remove useless check in should_enable_fbc()Dembskiy Igor1-3/+0
It does not make sense to compare a pointer to array element with NULL. Found by Linux Verification Center (linuxtesting.org) with SVACE. Fixes: 65d38262b3e8 ("drm/amd/display: fbc state could not reach while enable fbc") Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Dembskiy Igor <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-06Revert "drm/amd/display: Remove v_startup workaround for dcn3+"Hamza Mahfooz1-20/+4
This reverts commit 3a31e8b89b7240d9a17ace8a1ed050bdcb560f9e. We still need to call dcn20_adjust_freesync_v_startup() for older DCN3+ ASICs. Otherwise, it can cause DP to HDMI 2.1 PCONs to fail to light up. Cc: [email protected] Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2809 Reviewed-by: Fangzhi Zuo <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-09-01drm/amd: Make fence wait in suballocator uninterruptibleSimon Pilkington1-1/+1
Commit c103a23f2f29 ("drm/amd: Convert amdgpu to use suballocation helper.") made the fence wait in amdgpu_sa_bo_new() interruptible but there is no code to handle an interrupt. This caused the kernel to randomly explode in high-VRAM-pressure situations so make it uninterruptible again. Signed-off-by: Simon Pilkington <[email protected]> Fixes: c103a23f2f29 ("drm/amd: Convert amdgpu to use suballocation helper.") Reviewed-by: Christian König <[email protected]> Signed-off-by: Christian König <[email protected]> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2761 CC: [email protected] # 6.4+
2023-08-31drm/amdgpu: fix amdgpu_cs_p1_user_fenceChristian König1-14/+4
The offset is just 32bits here so this can potentially overflow if somebody specifies a large value. Instead reduce the size to calculate the last possible offset. The error handling path incorrectly drops the reference to the user fence BO resulting in potential reference count underflow. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2023-08-31Revert "Revert "drm/amd/display: Implement zpos property""Hamza Mahfooz1-0/+9
This reverts commit e2066eb4efe0e7d2d329d6e6765ed637a523ac45. The problematic IGT test case (i.e. kms_atomic@plane-immutable-zpos) has been fixed as of commit cb77add45011 ("tests/kms_atomic: remove zpos < N-planes assert") to the IGT repo. So, reintroduce the reverted code. Link: https://gitlab.freedesktop.org/drm/igt-gpu-tools/-/commit/cb77add45011b129e21f3cb2a4089a73dde56179 Acked-by: Alex Deucher <[email protected]> Reviewed-by: Melissa Wen <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-31drm/amdkfd: Add missing gfx11 MQD manager callbacksJay Cornwall1-0/+3
mqd_stride function was introduced in commit 2f77b9a242a2 ("drm/amdkfd: Update MQD management on multi XCC setup") but not assigned for gfx11. Fixes a NULL dereference in debugfs. Signed-off-by: Jay Cornwall <[email protected]> Signed-off-by: Harish Kasiviswanathan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 6.5.x
2023-08-31drm/amdgpu: Free ras cmd input buffer properlyHawking Zhang1-7/+7
Do not access the pointer for ras input cmd buffer if it is even not allocated. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Stanley Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-31drm/amdgpu: Hide xcp partition sysfs under SRIOVRajneesh Bhardwaj1-3/+8
XCP partitions should not be visible for the VF for GFXIP 9.4.3. Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Rajneesh Bhardwaj <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-31drm/amdgpu: use read-modify-write mode for gfx v9_4_3 SQ settingTao Zhou1-1/+2
Instead of using direct update, avoid touching unrelated fields. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-31drm/amdkfd: use mask to get v9 interrupt sq data bits correctlyAlex Sierra1-1/+1
Interrupt sq data bits were not taken properly from contextid0 and contextid1. Use macro KFD_CONTEXT_ID_GET_SQ_INT_DATA instead. Signed-off-by: Alex Sierra <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-31drm/amdgpu: Allocate coredump memory in a nonblocking wayAndré Almeida1-1/+1
During a GPU reset, a normal memory reclaim could block to reclaim memory. Giving that coredump is a best effort mechanism, it shouldn't disturb the reset path. Change its memory allocation flag to a nonblocking one. Signed-off-by: André Almeida <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-31drm/amdgpu: Support query ecc cap for aqua_vanjaramHawking Zhang1-2/+16
Driver queries umc_info v4_0 to identify ecc cap for aqua_vanjaram Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Candice Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-31drm/amdgpu: Add umc_info v4_0 structureHawking Zhang1-0/+18
To be used by aqua_vanjaram Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Candice Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-31drm/amd/display: always switch off ODM before committing more streamsWenjing Liu1-5/+5
ODM power optimization is only supported with single stream. When ODM power optimization is enabled, we might not have enough free pipes for enabling other stream. So when we are committing more than 1 stream we should first switch off ODM power optimization to make room for new stream and then allocating pipe resource for the new stream. Cc: [email protected] Fixes: 59de751e3845 ("drm/amd/display: add ODM case when looking for first split pipe") Reviewed-by: Dillon Varone <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-31drm/amd/display: Remove wait while lockedGabe Teeger3-28/+42
[Why] We wait for mpc idle while in a locked state, leading to potential deadlock. [What] Move the wait_for_idle call to outside of HW lock. This and a call to wait_drr_doublebuffer_pending_clear are moved added to a new static helper function called wait_for_outstanding_hw_updates, to make the interface clearer. Cc: [email protected] Fixes: 8f0d304d21b3 ("drm/amd/display: Do not commit pipe when updating DRR") Reviewed-by: Jun Lei <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Gabe Teeger <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-31drm/amd/display: update blank state on ODM changesWenjing Liu1-27/+9
When we are dynamically adding new ODM slices, we didn't update blank state, if the pipe used by new ODM slice is previously blanked, we will continue outputting blank pixel data on that slice causing right half of the screen showing blank image. The previous fix was a temporary hack to directly update current state when committing new state. This could potentially cause hw and sw state synchronization issues and it is not permitted by dc commit design. Cc: [email protected] Fixes: 7fbf451e7639 ("drm/amd/display: Reinit DPG when exiting dynamic ODM") Reviewed-by: Dillon Varone <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-31drm/amd/display: Add smu write msg id fail retry processFudong Wang1-4/+16
A benchmark stress test (12-40 machines x 48hours) found that DCN315 has cases where DC writes to an indirect register to set the smu clock msg id, but when we go to read the same indirect register the returned msg id doesn't match with what we just set it to. So, to fix this retry the write until the register's value matches with the requested value. Cc: [email protected] # 6.1+ Fixes: f94903996140 ("drm/amd/display: Add DCN315 CLK_MGR") Reviewed-by: Charlene Liu <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Fudong Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-31drm/amdgpu: Add SMU v13.0.6 default reset methodsLijo Lazar2-3/+4
For APUs with SMU v13.0.6, mode-2 reset is kept as default and for others mode-1 is the default reset method. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Asad Kamal <[email protected]> Tested-by: Asad Kamal <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-31Partially revert "drm/amd/display: update add plane to context logic with a ↵Wenjing Liu1-4/+114
new algorithm" This partially reverts commit 460ea8980511 ("drm/amd/display: update add plane to context logic with a new algorithm"). The new secondary pipe allocation logic triggers an issue with a specific hardware state transition and causes a frame of corruption when toggling between windowed MPO and ODM desktop only mode. Ideally hwss is supposed to handle this scenario. We are temporarily reverting the logic and investigate the root cause why this transition would cause corruptions. Fixes: 460ea8980511 ("drm/amd/display: update add plane to context logic with a new algorithm") Reviewed-by: Martin Leung <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-31drm/amd/display: register edp_backlight_control() for DCN301Hamza Mahfooz1-0/+1
As made mention of in commit 099303e9a9bd ("drm/amd/display: eDP intermittent black screen during PnP"), we need to turn off the display's backlight before powering off an eDP display. Not doing so will result in undefined behaviour according to the eDP spec. So, set DCN301's edp_backlight_control() function pointer to dce110_edp_backlight_control(). Cc: [email protected] Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2765 Fixes: 9c75891feef0 ("drm/amd/display: rework recent update PHY state commit") Suggested-by: Swapnil Patel <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-31drm/amdgpu: Add bootloader wait for PSP v13Lijo Lazar1-2/+26
Implement the wait for bootloader call back for PSP v13.0 ASICs. Only for ASICs with PSP v13.0.6, it needs an additional check for VBIOS mailbox status. Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Asad Kamal <[email protected]> Tested-by: Asad Kamal <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-31drm/amdgpu: register a dirty framebuffer callback for fbconHamza Mahfooz1-1/+25
fbcon requires that we implement &drm_framebuffer_funcs.dirty. Otherwise, the framebuffer might take a while to flush (which would manifest as noticeable lag). However, we can't enable this callback for non-fbcon cases since it may cause too many atomic commits to be made at once. So, implement amdgpu_dirtyfb() and only enable it for fbcon framebuffers (we can use the "struct drm_file file" parameter in the callback to check for this since it is only NULL when called by fbcon, at least in the mainline kernel) on devices that support atomic KMS. Cc: Aurabindo Pillai <[email protected]> Cc: Mario Limonciello <[email protected]> Cc: [email protected] # 6.1+ Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2519 Reviewed-by: Mario Limonciello <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-31drm/amdgpu: Updated TCP/UTCL1 programmingMangesh Gadre1-0/+3
Update TCP/UTCL1 thrashing control settings v2: updated rev_id check Signed-off-by: Mangesh Gadre <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-31drm/amd/pm: fix debugfs pm_info outputAlex Deucher1-0/+3
Print both input and avg power. Fixes: 47f1724db4fe ("drm/amd: Introduce `AMDGPU_PP_SENSOR_GPU_INPUT_POWER`") Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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