aboutsummaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd
AgeCommit message (Collapse)AuthorFilesLines
2020-08-06drm/amdgpu: fix spelling mistake "Falied" -> "Failed"Colin Ian King1-1/+1
There is a spelling mistake in a DRM_ERROR error message. Fix it. This got lost in a merge, restore the fix. Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]> (cherry picked from commit 4afaa61db9cf5250b5734c2531b226e7b3a3d691)
2020-08-06Merge branch 'WIP.locking/seqlocks' into locking/urgentIngo Molnar1-2/+0
Pick up the full seqlock series PeterZ is working on. Signed-off-by: Ingo Molnar <[email protected]>
2020-08-05Merge tag 'drm-next-2020-08-06' of git://anongit.freedesktop.org/drm/drmLinus Torvalds414-12135/+228914
Pull drm updates from Dave Airlie: "New xilinx displayport driver, AMD support for two new GPUs (more header files), i915 initial support for RocketLake and some work on their DG1 (discrete chip). The core also grew some lockdep annotations to try and constrain what drivers do with dma-fences, and added some documentation on why the idea of indefinite fences doesn't work. The long list is below. I do have some fixes trees outstanding, but I'll follow up with those later. core: - add user def flag to cmd line modes - dma_fence_wait added might_sleep - dma-fence lockdep annotations - indefinite fences are bad documentation - gem CMA functions used in more drivers - struct mutex removal - more drm_ debug macro usage - set/drop master api fixes - fix for drm/mm hole size comparison - drm/mm remove invalid entry optimization - optimise drm/mm hole handling - VRR debugfs added - uncompressed AFBC modifier support - multiple display id blocks in EDID - multiple driver sg handling fixes - __drm_atomic_helper_crtc_reset in all drivers - managed vram helpers ttm: - ttm_mem_reg handling cleanup - remove bo offset field - drop CMA memtype flag - drop mappable flag xilinx: - New Xilinx ZynqMP DisplayPort Subsystem driver nouveau: - add CRC support - start using NVIDIA published class header files - convert all push buffer emission to new macros - Proper push buffer space management for EVO/NVD channels. - firmware loading fixes - 2MiB system memory pages support on Pascal and newer vkms: - larger cursor support i915: - Rocketlake platform enablement - Early DG1 enablement - Numerous GEM refactorings - DP MST fixes - FBC, PSR, Cursor, Color, Gamma fixes - TGL, RKL, EHL workaround updates - TGL 8K display support fixes - SDVO/HDMI/DVI fixes amdgpu: - Initial support for Sienna Cichlid GPU - Initial support for Navy Flounder GPU - SI UVD/VCE support - expose rotation property - Add support for unique id on Arcturus - Enable runtime PM on vega10 boards that support BACO - Skip BAR resizing if the bios already did id - Major swSMU code cleanup - Fixes for DCN bandwidth calculations amdkfd: - Track SDMA usage per process - SMI events interface radeon: - Default to on chip GART for AGP boards on all arches - Runtime PM reference count fixes msm: - headers regenerated causing churn - a650/a640 display and GPU enablement - dpu dither support for 6bpc panels - dpu cursor fix - dsi/mdp5 enablement for sdm630/sdm636/sdm66 tegra: - video capture prep support - reflection support mediatek: - convert mtk_dsi to bridge API meson: - FBC support sun4i: - iommu support rockchip: - register locking fix - per-pixel alpha support PX30 VOP mgag200: - ported to simple and shmem helpers - device init cleanups - use managed pci functions - dropped hw cursor support ast: - use managed pci functions - use managed VRAM helpers - rework cursor support malidp: - dev_groups support hibmc: - refactor hibmc_drv_vdac: vc4: - create TXP CRTC imx: - error path fixes and cleanups etnaviv: - clock handling and error handling cleanups - use pin_user_pages" * tag 'drm-next-2020-08-06' of git://anongit.freedesktop.org/drm/drm: (1747 commits) drm/msm: use kthread_create_worker instead of kthread_run drm/msm/mdp5: Add MDP5 configuration for SDM636/660 drm/msm/dsi: Add DSI configuration for SDM660 drm/msm/mdp5: Add MDP5 configuration for SDM630 drm/msm/dsi: Add phy configuration for SDM630/636/660 drm/msm/a6xx: add A640/A650 hwcg drm/msm/a6xx: hwcg tables in gpulist drm/msm/dpu: add SM8250 to hw catalog drm/msm/dpu: add SM8150 to hw catalog drm/msm/dpu: intf timing path for displayport drm/msm/dpu: set missing flush bits for INTF_2 and INTF_3 drm/msm/dpu: don't use INTF_INPUT_CTRL feature on sdm845 drm/msm/dpu: move some sspp caps to dpu_caps drm/msm/dpu: update UBWC config for sm8150 and sm8250 drm/msm/dpu: use right setup_blend_config for sm8150 and sm8250 drm/msm/a6xx: set ubwc config for A640 and A650 drm/msm/adreno: un-open-code some packets drm/msm: sync generated headers drm/msm/a6xx: add build_bw_table for A640/A650 drm/msm/a6xx: fix crashstate capture for A650 ...
2020-07-30Revert "drm/amdgpu: Fix NULL dereference in dpm sysfs handlers"Alex Deucher1-3/+6
This regressed some working configurations so revert it. Will fix this properly for 5.9 and backport then. This reverts commit 38e0c89a19fd13f28d2b4721035160a3e66e270b. Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2020-07-30drm/amd/display: Clear dm_state for fast updatesMazin Rezk1-9/+27
This patch fixes a race condition that causes a use-after-free during amdgpu_dm_atomic_commit_tail. This can occur when 2 non-blocking commits are requested and the second one finishes before the first. Essentially, this bug occurs when the following sequence of events happens: 1. Non-blocking commit #1 is requested w/ a new dm_state #1 and is deferred to the workqueue. 2. Non-blocking commit #2 is requested w/ a new dm_state #2 and is deferred to the workqueue. 3. Commit #2 starts before commit #1, dm_state #1 is used in the commit_tail and commit #2 completes, freeing dm_state #1. 4. Commit #1 starts after commit #2 completes, uses the freed dm_state 1 and dereferences a freelist pointer while setting the context. Since this bug has only been spotted with fast commits, this patch fixes the bug by clearing the dm_state instead of using the old dc_state for fast updates. In addition, since dm_state is only used for its dc_state and amdgpu_dm_atomic_commit_tail will retain the dc_state if none is found, removing the dm_state should not have any consequences in fast updates. This use-after-free bug has existed for a while now, but only caused a noticeable issue starting from 5.7-rc1 due to 3202fa62f ("slub: relocate freelist pointer to middle of object") moving the freelist pointer from dm_state->base (which was unused) to dm_state->context (which is dereferenced). Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=207383 Fixes: bd200d190f45 ("drm/amd/display: Don't replace the dc_state for fast updates") Reported-by: Duncan <[email protected]> Signed-off-by: Mazin Rezk <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2020-07-30drm/amdgpu: Prevent kernel-infoleak in amdgpu_info_ioctl()Peilin Ye1-1/+2
Compiler leaves a 4-byte hole near the end of `dev_info`, causing amdgpu_info_ioctl() to copy uninitialized kernel stack memory to userspace when `size` is greater than 356. In 2015 we tried to fix this issue by doing `= {};` on `dev_info`, which unfortunately does not initialize that 4-byte hole. Fix it by using memset() instead. Cc: [email protected] Fixes: c193fa91b918 ("drm/amdgpu: information leak in amdgpu_info_ioctl()") Fixes: d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)") Suggested-by: Dan Carpenter <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Peilin Ye <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-29dma-buf: Use sequence counter with associated wound/wait mutexAhmed S. Darwish1-2/+0
A sequence counter write side critical section must be protected by some form of locking to serialize writers. If the serialization primitive is not disabling preemption implicitly, preemption has to be explicitly disabled before entering the sequence counter write side critical section. The dma-buf reservation subsystem uses plain sequence counters to manage updates to reservations. Writer serialization is accomplished through a wound/wait mutex. Acquiring a wound/wait mutex does not disable preemption, so this needs to be done manually before and after the write side critical section. Use the newly-added seqcount_ww_mutex_t instead: - It associates the ww_mutex with the sequence count, which enables lockdep to validate that the write side critical section is properly serialized. - It removes the need to explicitly add preempt_disable/enable() around the write side critical section because the write_begin/end() functions for this new data type automatically do this. If lockdep is disabled this ww_mutex lock association is compiled out and has neither storage size nor runtime overhead. Signed-off-by: Ahmed S. Darwish <[email protected]> Signed-off-by: Peter Zijlstra (Intel) <[email protected]> Acked-by: Daniel Vetter <[email protected]> Link: https://lkml.kernel.org/r/[email protected]
2020-07-29drm/ttm: make ttm_tt unbind function return void.Dave Airlie1-3/+2
The return value just led to BUG_ON, I think if a driver wants to BUG_ON here it can do it itself. (don't BUG_ON). Reviewed-by: Christian König <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-07-27Merge tag 'amd-drm-next-5.9-2020-07-24' of ↵Dave Airlie53-1950/+3002
git://people.freedesktop.org/~agd5f/linux into drm-next amd-drm-next-5.9-2020-07-24: amdgpu: - Misc sienna cichlid fixes - Final bits of swSMU cleanup - Misc display fixes - Misc VCN fixes - Eeprom i2c cleanup - Drop amd vrr_range debugfs in favor of core drm Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-07-24Merge v5.8-rc6 into drm-nextDave Airlie2-2/+2
I've got a silent conflict + two trees based on fixes to merge. Fixes a silent merge with amdgpu Signed-off-by: Dave Airlie <[email protected]>
2020-07-23Merge tag 'amd-drm-next-5.9-2020-07-17' of ↵Dave Airlie154-3011/+5136
git://people.freedesktop.org/~agd5f/linux into drm-next amd-drm-next-5.9-2020-07-17: amdgpu: - SI UVD/VCE clock support - Updates for Sienna Cichlid - Expose drm rotation property - Atomfirmware updates for renoir - updates to GPUVM hub handling for different register layouts - swSMU restructuring and cleanups - RAS fixes - DC fixes - mode1 reset support for Sienna Cichlid - Add support for Navy Flounder GPUs amdkfd: - Add SMI events watch interface UAPI: - Add amdkfd SMI events watch interface Userspace which uses this interface: https://github.com/RadeonOpenCompute/rocm_smi_lib/commit/2235ede34c456f1c7d3490f6fe74825d442d272e Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-07-23Merge tag 'drm-misc-next-2020-07-22' of ↵Dave Airlie1-7/+2
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for v5.9: UAPI Changes: Cross-subsystem Changes: - Convert panel-dsi-cm and ingenic bindings to YAML. - Add lockdep annotations for dma-fence. \o/ - Describe why indefinite fences are a bad idea - Update binding for rocktech jh057n00900. Core Changes: - Add vblank workers. - Use spin_(un)lock_irq instead of the irqsave/restore variants in crtc code. - Add managed vram helpers. - Convert more logging to drm functions. - Replace more http links with https in core and drivers. - Cleanup to ttm iomem functions and implementation. - Remove TTM CMA memtype as it doesn't work correctly. - Remove TTM_MEMTYPE_FLAG_MAPPABLE for many drivers that have no unmappable memory resources. Driver Changes: - Add CRC support to nouveau, using the new vblank workers. - Dithering and atomic state fix for nouveau. - Fixes for Frida FRD350H54004 panel. - Add support for OSD mode (sprite planes), IPU (scaling) and multiple panels/bridges to ingenic. - Use managed vram helpers in ast. - Assorted small fixes to ingenic, i810, mxsfb. - Remove optional unused ttm dummy functions. Signed-off-by: Dave Airlie <[email protected]> From: Maarten Lankhorst <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-07-21Revert "drm/amd/display: Expose connector VRR range via debugfs"Bhanuprakash Modem1-20/+0
v3: * Rebase (Manasi) v2: * Rebase (Manasi) As both VRR min and max are already part of drm_display_info, drm can expose this VRR range for each connector. Hence this logic should move to core DRM. This reverts commit 727962f030c23422a01e8b22d0f463815fb15ec4. Signed-off-by: Bhanuprakash Modem <[email protected]> Cc: Nicholas Kazlauskas <[email protected]> Cc: Harry Wentland <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Manasi Navare <[email protected]> Cc: AMD gfx <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amdgpu: Fix NULL dereference in dpm sysfs handlersPaweł Gronowski1-6/+3
NULL dereference occurs when string that is not ended with space or newline is written to some dpm sysfs interface (for example pp_dpm_sclk). This happens because strsep replaces the tmp with NULL if the delimiter is not present in string, which is then dereferenced by tmp[0]. Reproduction example: sudo sh -c 'echo -n 1 > /sys/class/drm/card0/device/pp_dpm_sclk' Signed-off-by: Paweł Gronowski <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2020-07-21drm/amd/powerplay: fix a crash when overclocking Vega MQiu Wenbo1-4/+6
Avoid kernel crash when vddci_control is SMU7_VOLTAGE_CONTROL_NONE and vddci_voltage_table is empty. It has been tested on Intel Hades Canyon (i7-8809G). Bug: https://bugzilla.kernel.org/show_bug.cgi?id=208489 Fixes: ac7822b0026f ("drm/amd/powerplay: add smumgr support for VEGAM (v2)") Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Qiu Wenbo <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2020-07-21drm/amdgpu/sienna_cichlid: add SMU i2c support (v2)Alex Deucher1-0/+239
Enable SMU i2c bus access for sienna_cichlid asics. v2: change callback name Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amdgpu/navi1x: add SMU i2c support (v2)Alex Deucher1-0/+239
Enable SMU i2c bus access for navi1x asics. v2: add missing implementation Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amdgpu/swSMU: remove eeprom from the smu i2c handlers (v2)Alex Deucher4-36/+36
The driver uses it for EEPROM access, but it's just an i2c bus. v2: change the callback name as well. Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amdgpu/vega20: enable the smu i2c bus for all boardsAlex Deucher1-7/+4
There is no longer a ras dependency so it's safe to expose on all boards. Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amdgpu: remove eeprom from the smu i2c handlersAlex Deucher3-30/+30
The driver uses it for EEPROM access, but it's just an i2c bus. Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amdgpu: move i2c bus lock out of ras structureAlex Deucher3-8/+4
It's not really ras related. It's just a lock for the bus in general. This removes the ras dependency from the smu i2c bus. Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amdgpu: Fix NULL dereference in dpm sysfs handlersPaweł Gronowski1-6/+3
NULL dereference occurs when string that is not ended with space or newline is written to some dpm sysfs interface (for example pp_dpm_sclk). This happens because strsep replaces the tmp with NULL if the delimiter is not present in string, which is then dereferenced by tmp[0]. Reproduction example: sudo sh -c 'echo -n 1 > /sys/class/drm/card0/device/pp_dpm_sclk' Signed-off-by: Paweł Gronowski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/powerplay: fix a crash when overclocking Vega MQiu Wenbo1-4/+6
Avoid kernel crash when vddci_control is SMU7_VOLTAGE_CONTROL_NONE and vddci_voltage_table is empty. It has been tested on Intel Hades Canyon (i7-8809G). Bug: https://bugzilla.kernel.org/show_bug.cgi?id=208489 Fixes: ac7822b0026f ("drm/amd/powerplay: add smumgr support for VEGAM (v2)") Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Qiu Wenbo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/powerplay: retrieve VCN dpm table per instancesJiansong Chen1-30/+37
To accommodate VCN instances variance, otherwise it may trigger smu response error for configuration with less instances. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/powerplay: update driver if version for navy_flounderJiansong Chen1-1/+1
It's in accordance with pmfw 65.3.0 for navy_flounder. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/powerplay: fix typos for clk mapJiansong Chen1-2/+2
It should be DCLK1->PPCLK_DCLK_1 and VCLK->PPCLK_VCLK_0. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Likun Gao <[email protected]> Acked-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amdgpu/vcn: merge shared memory into vcpuJames Zhu2-13/+6
Merge vcn firmware shared memory bo into vcn vcpu bo. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21Revert "drm/amdgpu/vcn: add shared memory restore after wake up from sleep."James Zhu2-28/+1
This reverts commit 21b704d78352c289d31697824ceea7ad0ff4ce59. To merge vcn firmware shared memory bo into vcn vcpu bo. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/display: 3.2.95Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/display: interface to obtain minimum plane size capsIgor Kravchenko5-5/+18
[Why] Implement an interface to obtain plane size caps [How] Add min_width, min_height fields to dc_plane_cap structure. Set values to 16x16 for discrete ASICs, and 64x64 for others. Signed-off-by: Igor Kravchenko <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/display: Add additional config guards for DCNAurabindo Pillai1-2/+4
[Why&How] Fix build error by protecting code with config guard to enable building amdgpu without CONFIG_DRM_AMD_DC_DCN enabled. This option is disabled by default for allmodconfig. Signed-off-by: Aurabindo Pillai <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/display: Call dsc related functions indirectly via dc interfaceAurabindo Pillai1-1/+1
[Why&How] Accessing dcn20_add_dsc_to_stream_resource directly causes build failure for configuration which has CONFIG_DRM_AMD_DC_DCN disabled. Fix this by calling the corresponding function exposed via dc resource functions. Signed-off-by: Aurabindo Pillai <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/display: Improve compatibility by re-ordering info-packetsNaveed Ashfaq1-4/+4
[why] On DCN20, Some features would not be activated when ALLM was turned on. TV seemed to activate only the latest info packet sent, and the ALLM info packet was sent after the VSIF info packet. The packet indices was also inconsistent between DCN10 and DCN20. [how] Change the packet indices of DCN20 to match those of DCN10. This makes them consistent and also makes the vendor info packet be sent after the hfvsif info packet. Signed-off-by: Naveed Ashfaq <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/display: [FW Promotion] Release 0.0.25Anthony Koo1-2/+2
Signed-off-by: Anthony Koo <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/display: Make new dc interface for adding dsc resourceAurabindo Pillai5-1/+20
[Why] dcn20_add_dsc_to_stream_resource is accessed in amdgpu_dm directly. This creates build error for configuration with DCN disabled. [How] Make the function available through a resource pool function so that dcn20 function need not be called directly. Signed-off-by: Aurabindo Pillai <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/display: rename dsc extended caps as dsc branch decoder capsWenjing Liu4-10/+10
[why] The capability fields are reserved for DSC branch only to report the capability related to the branch's DSC decoder. Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/display: Decouple ABM init from dmcuRoman Li1-3/+10
[Why] With ABM implemented on DMUB the ABM enablement shoudn't be solely rely on dmcu. Otherwise it won't work if dmcu is disabled. [How] 1. Decouple dmcub config copy from dmcu iram copy. 2. Set abm connector property if either dmcu or dmub enabled. Signed-off-by: Roman Li <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/display: Implement AMD VSIF V3Reza Amini4-0/+73
[Why] To support V3 [How] Generate new VSIF for V3 Signed-off-by: Reza Amini <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/display: Add DSC parameters logging to debugfsEryk Brol3-1/+525
[why] Need to add new parameters to debugfs logging so we will know what parameters DSC is using for debug purposes. So we are adding a read function in debugfs to read DSC status registers Signed-off-by: Eryk Brol <[email protected]> Reviewed-by: Mikita Lipski <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/display: remove unhelpful 5ms delayAric Cyr1-4/+0
[Why] Scaler vendor confirmed the 5ms was not helpful so no point in keeping it. [How] Revert 5ms delay after setting training pattern. Signed-off-by: Aric Cyr <[email protected]> Reviewed-by: Ashley Thomas <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amdgpu: do not disable SMU on vm rebootNirmoy Das1-1/+2
For passthrough device, we do baco reset after 1st vm boot so if we disable SMU on 1st VM shutdown baco reset will fail for 2nd vm boot. Signed-off-by: Nirmoy Das <[email protected]> Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amdgpu: add timeout flush mechanism to update wptr for self interrupt (v2)Chengming Gui1-0/+45
outstanding log reaches threshold will trigger IH ring1/2's wptr reported, that will avoid generating interrupts to ring0 too frequent. But if ring1/2's wptr hasn't been increased for a long time, the outstanding log can't reach threshold so that driver can't get latest wptr info and miss some interrupts. v2: squash in warning fix Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Acked-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amdgpu: enable xgmi support for sienna cichlidJohn Clements1-0/+3
set xgmi support flag suring nv ip init sequence Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amdgpu: load asd for sienna cichlidJohn Clements1-1/+0
do not abort psp asd load sequence for sienna cichlid Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/powerplay: tag swSMU code layersEvan Quan13-9/+28
Per designs, the swSMU code is separated into four layers. And the typical calling flow should be like: amdgpu_smu.c -> ${asic}_ppt.c -> smu_v11/12_0.c -> smu_cmn.c. Compile errors will come out for any violations. This can help to prevent cross callings(e.g. amdgpu_smu.c -> ${asic}_ppt.c -> amdgpu_smu.c -> ${asic}_ppt.c) which were common in our code. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/powerplay: revise the calling flow on OD table updateEvan Quan2-8/+7
This can eliminate the cross callings and maintain clear code layer. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/powerplay: drop unnecessary message support checkEvan Quan1-9/+0
These messages are known to be supported by all ASICs. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/powerplay: move SMC message issuing APIs to smu_cmn.cEvan Quan13-313/+252
Considering they can be shared by all ASICs. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/powerplay: update the tables init relatedEvan Quan9-120/+83
To avoid cross calling and maintain clear code layer. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/powerplay: move table setting common code to smu_cmn.cEvan Quan11-81/+103
As they are shared by all ASICs. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.