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2020-07-21drm/amd/powerplay: maximum code sharing around watermarks settingEvan Quan7-182/+166
Maximum code sharing. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/powerplay: move more APIs to smu_cmn.cEvan Quan10-83/+90
Considering they are shared by all ASICs. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/powerplay: common API for disabling all features with exceptionEvan Quan9-8/+30
We are moving to centralize all feature enablement/support checking and setting APIs in smu_cmn.c. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/powerplay: move ppfeature mask setting to smu_cmn.cEvan Quan10-142/+190
Considering they are shared by all ASICs. And we are moving to centralize all feature enablement/support checking and setting APIs in smu_cmn.c. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/powerplay: implement smu_cmn_get_enabled_mask() for all ASICsEvan Quan10-66/+42
Instead of having each for smu v11 and v12. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/powerplay: move dpm feature enablement checking to smu_cmn.cEvan Quan10-87/+95
Considering it is shared by all ASICs and smu_cmn.c should be the right place. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/powerplay: move dpm feature support checking to smu_cmn.cEvan Quan7-33/+35
Considering it is shared by all ASICs and smu_cmn.c should be the right place. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/powerplay: move clock dpm enablement check to smu_v11/v12Evan Quan3-3/+6
As those APIs of smu_v11/v12 are more widely called. And they need this check also. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/powerplay: drop unused codeEvan Quan8-465/+0
Those code were obsoleted by new common API smu_cmn_to_asic_specific_index(). Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/powerplay: unify swSMU index to asic specific index mappingEvan Quan12-201/+528
By this we can drop redundant code. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/powerplay: widely share the API for data table retrievingEvan Quan8-26/+34
Considering the data table retrieving can be more widely shared, amdgpu_atombios.c is the right place. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amdgpu: add read amdgpu_gfxoff status in debugfsJinzhou.Su7-0/+86
Add interface for SMU12 device, used by UMR. v2: fix code style Signed-off-by: Jinzhou.Su <[email protected]> Reviewed-by: Evan Quan <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amdgpu: load ta firmware for sienna cichlidBhawanpreet Lakha1-1/+5
call psp_int_ta_microcode() to parse the ta firmware. Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: John Clements <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amd/powerplay: suppress compile error around BUG_ONEvan Quan1-2/+12
To suppress the compile error below for "ARCH=arc". drivers/gpu/drm/amd/amdgpu/../powerplay/arcturus_ppt.c: In function 'arcturus_fill_eeprom_i2c_req': >> arch/arc/include/asm/bug.h:22:2: error: implicit declaration of function 'pr_warn'; did you mean 'pci_warn'? [-Werror=implicit-function-declaration] 22 | pr_warn("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \ | ^~~~~~~ include/asm-generic/bug.h:62:57: note: in expansion of macro 'BUG' 62 | #define BUG_ON(condition) do { if (unlikely(condition)) BUG(); } while (0) | ^~~ drivers/gpu/drm/amd/amdgpu/../powerplay/arcturus_ppt.c:2157:2: note: in expansion of macro 'BUG_ON' 2157 | BUG_ON(numbytes > MAX_SW_I2C_COMMANDS); Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/amdgpu/smu11: drop code chuck that got accidently re-addedAlex Deucher1-6/+0
Seems to be due to a bad merge. Code was originally added in commit 5aaa8fff3aa950 ("drm/amd/powerplay: unload mp1 for Arcturus RAS baco reset") but later removed in commit 7f70443fd83407 ("drm/amdgpu: set mp1 state before reload"). but is back again. Signed-off-by: Alex Deucher <[email protected]>
2020-07-21drm/ttm: remove TTM_MEMTYPE_FLAG_CMAChristian König1-2/+2
The original intention was to avoid CPU page table unmaps when BOs move between the GTT and SYSTEM domain. The problem is that this never correctly handled changes in the caching attributes or backing pages. Just drop this for now and simply unmap the CPU page tables in all cases. Signed-off-by: Christian König <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> Link: https://patchwork.freedesktop.org/patch/378240/
2020-07-21drm: remove optional dummy function from drivers using TTMChristian König1-5/+0
Implementing those is completely unnecessary. Signed-off-by: Christian König <[email protected]> Reviewed-by: Daniel Vetter <[email protected]> Reviewed-by: Madhav Chauhan <[email protected]> Link: https://patchwork.freedesktop.org/patch/378236/
2020-07-20Merge tag 'drm-misc-next-2020-07-16' of ↵Dave Airlie6-103/+58
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for v5.9: UAPI Changes: Cross-subsystem Changes: - Add ckoenig as dma-buf maintainer. - Revert invalid fix for dma-fence-chain, and fix selftest. - Add fixmes to amifb about APUS support. - Use array3_size in fbcon_prepare_logo, and struct_size() in alloc_apertures. - Fix leaks in neofb, fb/savage and omapfb. - Other small fixes to fb code. - Convert some dt bindings to schema for some panels, and fix simple-framebuffer dt example. Core Changes: - Add DRM_FORMAT_MOD_GENERIC_16_16_TILE as alias to DRM_FORMAT_MOD_SAMSUNG_16_16_TILE, as it can be used more generic. - Add support for multiple DispID extension blocks in edid. - Use https instead of http for some of the urls. - Use drm_* macros for logging in mipi-dsi and fb-helper. - Further cleanup ttm_mem_reg handling. - Remove duplicated words in comments. Driver Changes: - Use __drm_atomic_helper_crtc_reset in all atomic drivers. - Add Amlogic Video FBC support to meson and fourcc to core. - Refactor hisilicon's hibmc_drv_vdac. - Create a TXP CRTC for vc4. - Rework cursor support in ast. - Fix runtime PM in STM. - Allow bigger cursors in vkms. - Cleanup sg handling in radeon and amdgpu, and stop creating dummy gtt nodes with ttm fixed. - Rework crtc handling in mgag200. - Miscellaneous small fixes to meson, vgem, bridge/dw-hdmi, panel/auo,b116xw03, panel/LG LB070WV8, lima, bridge/sil_sii8620, virtio, tilcdc. Signed-off-by: Dave Airlie <[email protected]> From: Maarten Lankhorst <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-07-15drm/amd/amdkfd: Fix large framesize for kfd_smi_ev_read()Aurabindo Pillai1-7/+19
The buffer allocated is of 1024 bytes. Allocate this from heap instead of stack. Also remove check for stack size since we're allocating from heap Signed-off-by: Aurabindo Pillai <[email protected]> Tested-by: Amber Lin <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdkfd: Provide SMI events watchAmber Lin8-0/+278
When the compute is malfunctioning or performance drops, the system admin will use SMI (System Management Interface) tool to monitor/diagnostic what went wrong. This patch provides an event watch interface for the user space to register devices and subscribe events they are interested. After registered, the user can use annoymous file descriptor's poll function with wait-time specified and wait for events to happen. Once an event happens, the user can use read() to retrieve information related to the event. VM fault event is done in this patch. v2: - remove UNREGISTER and add event ENABLE/DISABLE - correct kfifo usage - move event message API to kfd_ioctl.h v3: send the event msg in text than in binary v4: support multiple clients v5: move events enablement from ioctl to fd write v6: sparse fix Signed-off-by: Amber Lin <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: enable ih CG for navy_flounderJiansong Chen1-1/+2
Enable ih CG by setting the corresponding flag. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: enable hdp CG and LS for navy_flounderJiansong Chen1-1/+3
Enable hdp CG and LS by setting the corresponding flags. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: enable mc CG and LS for navy_flounderJiansong Chen1-1/+3
Enable mc CG and LS by setting the corresponding flags. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: enable athub/mmhub PG for navy_flounderJiansong Chen1-1/+3
Enable athub/mmhub PG by setting the corresponding flags. Actually the enablement is exercised by PMFW. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: set VCN1 pg only for sienna_cichlidJiansong Chen1-6/+14
navy_flounder has one VCN instance, and the work around is to avoid smu reponse error when setting VCN1 pg for the chip. It is preferred VCN0 and VCN1 are separated for the pg setting so better power efficiency can be achieved. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/display: add DC support for navy flounderBhawanpreet Lakha3-2/+12
Plumb DC support for navy flounder through. Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: support athub cg setting for navy_flounderJiansong Chen1-0/+1
navy_flounder has athub ip v2.1. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: enable GFX clock gating for navy_flounderJiansong Chen1-1/+4
Enable GFX MGCG, CGCG and 3DCG for navy_flounder. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: enable JPEG3.0 PG and CG for navy_flounderBoyuan Zhang1-2/+4
Enable JPEG3.0 PG and CG for navy_flounder by setting up the flags to the ASIC Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: enable VCN3.0 DPG for navy_flounderBoyuan Zhang1-1/+2
Enable VCN3.0 DPG for navy_flounder by setting up the flag to the ASIC Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: enable VCN3.0 PG and CG for navy_flounderBoyuan Zhang1-2/+2
Enable VCN3.0 PG and CG for navy_flounder by setting up the flags to the ASIC Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: enable cp_fw_write_wait for navy_flounderJiansong Chen1-0/+1
It's the same with sienna_cichlid, cp fw for navy_flounder can support WAIT_REG_MEM packet. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add vcn ip block for navy_flounderBoyuan Zhang1-0/+2
Add vcn3.0 and jpeg3.0 ip blocks for navy_flounder Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add navy_flounder vcn firmware supportBoyuan Zhang1-0/+8
Add navy_flounder to vcn family Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu/gfx10: add gc golden setting for navy_flounderJiansong Chen1-0/+48
Add gc golden setting for navy_flounder Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdkfd: Add kfd2kgd_funcs for navy_flounder kfd supportChengming Gui1-0/+1
Add callbacks to KGD for navy flounder. Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdkfd: Support navy_flounder KFDChengming Gui6-0/+24
Add KFD support for Navy Flounder. Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: use front door firmware loading for navy_flounderJiansong Chen1-2/+1
Same as other navi asics. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add psp block for navy_flounderJiansong Chen1-0/+5
Add psp and smu block for navy_flounder with psp firmware load type. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add psp support for navy_flounderJiansong Chen2-4/+16
Currently skip ASD FW loading and ih reroute per sienna_cichlid. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add smu block for navy_flounderJiansong Chen1-0/+3
Add SMU block for navy_flounder with direct firmware load type. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu/powerplay: add smu support for navy_flounderJiansong Chen3-1/+16
Now navy_flounder will reuse the smu11 driver_if header and ppt functions for sienna_cichlid. Later navy_flounder can maintain its own version if the compatibility is broken. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add gmc cg support for navy_flounderJiansong Chen2-2/+5
The athub version used for navy_flounder is v2.1. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: force pa_sc_tile_steering_override to 0 for navy_flounderJiansong Chen1-1/+2
pa_sc_tile_steering_override is only programmable for gfx10.0/10.1/10.2, and navy_flounder has the same gfx10.3 IP with sienna_cichlid. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: configure navy_flounder gfx according to gfx 10.3Tao Zhou1-0/+9
The gfx version of navy_flounder is 10.3, identical to sienna_cichlid, follow the way of sienna_cichlid. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add virtual display support for navy_flounder.Jiansong Chen1-0/+2
Virtual display support for bring up and virtualization. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add sdma ip block for navy_flounderJiansong Chen2-2/+19
Navy_Flounder has the same sdma IP version with sienna_cichlid, and it has 2 sdma controllers. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add gfx ip block for navy_flounderJiansong Chen2-0/+5
since navy_flounder has similar gc IP version with sienna_cichlid, follow its setting for the moment. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add ih ip block for navy_flounderJiansong Chen2-0/+2
navy_flounder has the same osssys IP verison with sienna_cichlid, follow its setting. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add gmc ip block for navy_flounderJiansong Chen2-6/+13
navy_flounder has similar gc IP version with sienna_cichlid, follow its setting for the moment. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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