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2022-02-17drm/amd/display: Add DCN316 resource and SMU clock managerHansen Dsouza11-3/+3647
Add core DC implementation for DCN316. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Prike Liang <[email protected]> Reviewed-by: Leo Li <[email protected]> Signed-off-by: Hansen Dsouza <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-17drm/amd/display: Add DMUB support for DCN316Leo Li6-1/+103
Initialize DMUB for DCN316. Use same funcs as DCN31 for DCN316. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Prike Liang <[email protected]> Signed-off-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-17drm/amd/display: configure dc hw resource for DCN 3.1.6Prike Liang9-4/+31
- set DC version - add construct/destroy dc clock management function - register dcn interrupt handler Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-17drm/amd/include: Add MP 13.0.8 register headersLeo Li2-0/+1013
Reviewed-by: Prike Liang <[email protected]> Signed-off-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-17drm/amd/include: Add register headers for DCN 3.1.6Leo Li4-0/+226509
Add register headers for the following IPs: - DCN 3.1.6 - DPCS 4.2.3 Acked-by: Harry Wentland <[email protected]> Signed-off-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu/gfx10: Add GC 10.3.7 SupportPrike Liang2-1/+57
Needed to properly initialize GC 10.3.7. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu/sdma5.2: add support for SDMA 5.2.7Prike Liang2-0/+6
Initialize SDMA engine firmware loading. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/pm: Add support for MP1 13.0.8Prike Liang4-0/+4
Set smu sw function and enable swSMU support for MP1. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu/psp: Add support for MP0 13.0.8Prike Liang3-0/+9
Set psp sw funcs callback and firmware loading for MP0. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu/gmc10: add support for GC 10.3.7Prike Liang2-0/+3
Set gfxhub function and configure VM for GC block. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu: update vcn/jpeg PG flags for VCN 3.1.1Sathishkumar S1-1/+3
update vcn and jpeg power gating flags for VCN 3.1.1 Signed-off-by: Sathishkumar S <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu: set new revision id for 10.3.7 GCPrike Liang1-0/+5
Add new revision ID for GC 10.3.7 and set cg/pg flags. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu/discovery: set sw common init for GC 10.3.7Prike Liang1-0/+1
Set nv_common_ip_block for GC 10.3.7. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu/discovery: Add 13.0.9 SMUIO blockPrike Liang1-0/+1
Add SMUIO sw function for the new SMUIO block. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd: smu7: downgrade voltage error to infoMario Limonciello1-2/+2
The message `Voltage value looks like a Leakage ID but it's not patched` shows up as an error on Dell Precision 3540. This doesn't cause functional problems and should be downgraded to info. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1162 Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Mario Limonciello <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu/discovery: add nbio sw func for 7.5.1 nbioPrike Liang1-0/+1
add nbio sw func for the new 7.5.1 nbio block. Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu: make cyan skillfish support code more consistentAlex Deucher5-8/+6
Since this is an existing asic, adjust the code to follow the same logic as previously so the driver state is consistent. No functional change intended. Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/display: For vblank_disable_immediate, check PSR is really usedMichel Dänzer1-8/+9
Even if PSR is allowed for a present GPU, there might be no eDP link which supports PSR. Fixes: 708978487304 ("drm/amdgpu/display: Only set vblank_disable_immediate when PSR is not enabled") Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdkfd: add return value check for queue evictionTao Zhou1-1/+1
Otherwise gpu reset will be triggered unconditionally in poison consumption. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdkfd: Replace zero-length array with flexible-array memberChangcheng Deng1-1/+1
There is a regular need in the kernel to provide a way to declare having a dynamically sized set of trailing elements in a structure. Kernel code should always use "flexible array members" for these cases. The older style of one-element or zero-length arrays should no longer be used. Reference: https://www.kernel.org/doc/html/latest/process/deprecated.html#zero-length-and-one-element-arrays Reported-by: Zeal Robot <[email protected]> Signed-off-by: Changcheng Deng <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/display: Add dsc pre-validation in atomic checkRoman Li5-16/+229
[Why] The previous change: "Add affected crtcs to atomic state for dsc mst unplug" forces modeset on all added crctc regardless whether timing changed or not. Per our implementation of dsc we need modeset only if timing changed. Otherwise dsc can be programmed incorrectly leading to dsc engine hang. [How] During atomic_check pre-compute dsc params. Only set mode_changed if timing is changed. Reviewed-by: Hersen Wu <[email protected]> Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu: Fix wait for RLCG command completionVictor Skvortsov2-1/+3
if (!(tmp & flag)) condition will always evaluate to true when the flag is 0x0 (AMDGPU_RLCG_GC_WRITE). Instead check that address bits are cleared to determine whether the command is complete. Signed-off-by: Victor Skvortsov <[email protected]> Tested-by: Bokun Zhang <[email protected]> Reviewed by: Shaoyun.liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/display: add dsc mst stream pbn log for debugHersen Wu4-0/+52
[why] payload and slot number of display on dsc mst hub will be adjusted when there is change on any display on dsc hub. to monitor dsc enable/disable, pbn change, we need add log. [How] add mst_pbn to dc_dsc_config of dc_crtc_timing. add dsc, pbn, display name within dc_core_enable_stream, dc_core_disable_stream, dc_stream_log Reviewed-by: Jerry Zuo <[email protected]> Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: Hersen Wu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/display: 3.2.173Aric Cyr1-1/+1
This version brings along the following fixes: -Fixes bugs for dsc mst hub -Enables 29 denial itnerface by default -Fixes dmub outbox notificatoin Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/display: [FW Promotion] Release 0.0.104.0Anthony Koo1-2/+2
Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: Anthony Koo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/display: Add affected crtcs to atomic state for dsc mst unplugRoman Li1-2/+5
[Why] When display topology changed on DSC hub we add all crtcs with dsc support to atomic state. Refer to patch:"drm/amd/display: Trigger modesets on MST DSC connectors" However the original implementation may skip crtc if the topology change caused by unplug. That potentially could lead to no-lightup or corruption on DSC hub after unplug event on one of the connectors. [How] Update add_affected_mst_dsc_crtcs() to use old connector state if new connector state has no crtc (undergoes modeset due to unplug) Fixes: 44be939ff7ac58 ("drm/amd/display: Trigger modesets on MST DSC connectors") Reviewed-by: Hersen Wu <[email protected]> Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: Roman Li <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/display: enable z9 denial interface by defaultEric Yang1-1/+1
Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: Eric Yang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu: Add "harvest" to IP discovery sysfsLuben Tuikov1-0/+8
Add the "harvest" field to the IP attributes in the IP discovery sysfs visualization, as this field is present in the binary data. At the time of this commit, the harvest data isn't consistently correct in VBIOS, but it is exposed for completeness, in the hopes that VBIOS will be fixed in the future. Cc: Alex Deucher <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/display: make sure pipe power gating reach requested hw stateCharlene Liu1-3/+18
[why] display mapping change will involved pipe power gating on and off. when doing this too fase, sometimes usbc will have no display. check HW status, it is still in pipe power gating. [how] insert polling HW status to make sure the required state reached. also add dal registry key handling. Reviewed-by: Sung joon Kim <[email protected]> Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/display: dsc mst re-compute pbn for changes on hubHersen Wu1-8/+45
[why] when unplug 1 dp from dsc mst hub, atomic_check new request dc_state only include info for the unplug dp. this will not trigger re-compute pbn for displays still connected to hub. [how] all displays connected to dsc hub are available in dc->current_state, by comparing dc->current_state and new request from atomic_chceck, it will provide info of displays connected to hub and do pbn re-compute. Reviewed-by: Roman Li <[email protected]> Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: Hersen Wu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/display: Fix for dmub outbox notification enableMeenakshikumar Somasundaram6-24/+80
[Why] Currently driver enables dmub outbox notification before oubox ISR is registered. During boot scenario, sometimes dmub issues hpd outbox message before driver registers ISR and those messages are missed. [How] Enable dmub outbox notification after outbox ISR is registered. Also, restructured outbox enable code to call from dm layer and renamed APIs. Reviewed-by: Jun Lei <[email protected]> Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: Meenakshikumar Somasundaram <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/pm: fix some OEM SKU specific stability issuesEvan Quan1-1/+31
Add a quirk in sienna_cichlid_ppt.c to fix some OEM SKU specific stability issues. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu: disable MMHUB PG for PicassoEvan Quan1-1/+4
MMHUB PG needs to be disabled for Picasso for stability reasons. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/pm: fulfill Sienna_Cichlid implementations for DriverSmuConfig settingEvan Quan1-0/+54
Fulfill the implementations for DriverSmuConfig setting on Sienna_Cichlid. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/pm: fulfill Navi1x implementations for DriverSmuConfig settingEvan Quan1-0/+50
Fulfill the implementations for DriverSmuConfig setting on Navi1x. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/pm: enable pm sysfs write for one VF modeYiqing Yao1-2/+2
[why] pm sysfs should be writable in one VF mode as is in passthrough [how] do not remove write access on pm sysfs if device is in one VF mode Fixes: 11c9cc95f818 ("amdgpu/pm: Make sysfs pm attributes as read-only for VFs") Signed-off-by: Yiqing Yao <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/pm: correct the default DriverSmuConfig table settingsEvan Quan4-0/+44
For Some ASICs, with the PMFW default settings, we may see the power consumption reported via metrics table is "Very Erratic". With the socket power alpha filter set as 10/100ms, we can correct that issue. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu/sdma5.2: Adjust the name string for firmwareAlex Deucher1-7/+7
This will make it easier to add new firmwares in the future. Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amdgpu: check return status before using stable_pstateTom Rix1-1/+2
Clang static analysis reports this problem amdgpu_ctx.c:616:26: warning: Assigned value is garbage or undefined args->out.pstate.flags = stable_pstate; ^ ~~~~~~~~~~~~~ amdgpu_ctx_stable_pstate can fail without setting stable_pstate. So check. Fixes: 8cda7a4f96e4 ("drm/amdgpu/UAPI: add new CTX OP to get/set stable pstates") Signed-off-by: Tom Rix <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-16drm/amd/display: Protect update_bw_bounding_box FPU code.Bas Nieuwenhuizen2-2/+7
For DCN3/3.01/3.02 at least these use the fpu. v2: squash in build fix for when DCN is not enabled (Leo) Signed-off-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-14drm/amd/display: reset lane settings after each PHY repeater LTSung Joon Kim1-5/+10
[why] In LTTPR non-transparent mode, we need to reset the cached lane settings before performing link training on the next PHY repeater. Otherwise, the cached lane settings will be used for the next clock recovery e.g. VS = MAX (3) which should not be the case according to the DP specs. We expect to use minimum lane settings on each clock recovery sequence. [how] Reset DPCD and HW lane settings on each repeater LT. Set training pattern to 0 for the repeater that failed LT at the proper place. Reviewed-by: Meenakshikumar Somasundaram <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Jasdeep Dhillon <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-14drm/amdkfd: navi2x requires extended engines to map and unmap sdma queuesJonathan Kim1-2/+9
SDMA 5.2.x queues are required to be mapped and unmapped from the extended engines. Signed-off-by: Jonathan Kim <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-14drm/amdkfd: remove unneeded unmap single queue optionJonathan Kim5-76/+22
The KFD only unmaps all queues, all dynamics queues or all process queues since RUN_LIST is mapped with all KFD queues. There's no need to provide a single type unmap so remove this option. Signed-off-by: Jonathan Kim <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-14drm/amdgpu: Handle the GPU recovery failure in SRIOV environment.Surbhi Kakarya2-1/+20
This patch handles the GPU recovery failure in sriov environment by retrying the reset if the first reset fails. To determine the condition of retry, a new macro AMDGPU_RETRY_SRIOV_RESET is added which returns true if failure is due to ETIMEDOUT, EINVAL or EBUSY, otherwise return false.A new macro AMDGPU_MAX_RETRY_LIMIT is used to limit the retry to 2. It also handles the return status in Post Asic Reset by updating the return code with asic_reset_res and eventually return the return code in amdgpu_job_timedout(). Signed-off-by: Surbhi Kakarya <[email protected]> Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-14drm/amdgpu: print more error infoStanley.Yang2-2/+76
print more error info when deferred uncorrectable ras error changed from V1: move Defferred error msg into query uncorrectable error count function. Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-14drm/amd/pm: correct the sequence of sending gpu reset msgYifan Zhang1-7/+2
the 2nd parameter should be smu msg type rather than asic msg index. Fixes: 7d38d9dc4ecc ("drm/amdgpu: add mode2 reset support for yellow carp") Signed-off-by: Yifan Zhang <[email protected]> Acked-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-14drm/amdgpu: Merge amdgpu_ras_late_init/amdgpu_ras_late_fini to ↵yipechai2-50/+11
amdgpu_ras_block_late_init/amdgpu_ras_block_late_fini 1. Merge amdgpu_ras_late_init to amdgpu_ras_block_late_init. 2. Remove amdgpu_ras_late_init since no ras block calls amdgpu_ras_late_init. 3. Merge amdgpu_ras_late_fini to amdgpu_ras_block_late_fini. 4. Remove amdgpu_ras_late_fini since no ras block calls amdgpu_ras_late_fini. Signed-off-by: yipechai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-14drm/amdgpu: Optimize operating sysfs and interrupt function interface in ↵yipechai2-22/+21
amdgpu_ras.c In order to reduce redundant struct conversion, modify operating sysfs and interrupt function interface parameters. Signed-off-by: yipechai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-14drm/amdgpu: Optimize amdgpu_xgmi_ras_late_init/amdgpu_xgmi_ras_fini function ↵yipechai2-35/+6
code Optimize amdgpu_xgmi_ras_late_init/amdgpu_xgmi_ras_fini function code. Signed-off-by: yipechai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-02-14drm/amdgpu: Optimize amdgpu_umc_ras_late_init/amdgpu_umc_ras_fini function codeyipechai4-38/+22
Optimize amdgpu_umc_ras_late_init/amdgpu_umc_ras_fini function code. Signed-off-by: yipechai <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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