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2020-10-30drm/amd/display: Add formats for DCC with 2/3 planes.Bas Nieuwenhuizen1-0/+96
For DCC we will use 2/3 planes to avoid X rendering to the frontbuffer with DCC compressed images. To make this work with the core KMS validation we need to add extra formats with the extra planes. However, due to flexibility we set bpp = 0 for the extra planes and do the validation ourselves. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/display: Set DC options from modifiers.Bas Nieuwenhuizen1-7/+95
This sets the DC tiling options from the modifier, if modifiers are used for the FB. This patch by itself does not expose the support yet though. There is not much validation yet to limit the scope of this patch, but the current validation is at the same level as the BO metadata path. v2: Add modifier check to should_reset_plane. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/display: Refactor surface tiling setup.Bas Nieuwenhuizen1-103/+119
Prepare for inserting modifiers based configuration, while sharing a bunch of DCC validation & initializing the device-based configuration. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/display: Convert tiling_flags to modifiers.Bas Nieuwenhuizen1-0/+123
This way the modifier path gets exercised all the time, improving testing. Furthermore, for modifiers this is required as getfb2 will always return the modifier if the driver sets allow_fb_modifiers. This only triggers once allow_fb_modifiers is set. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/display: Store tiling_flags in the framebuffer.Bas Nieuwenhuizen4-67/+59
This moves the tiling_flags to the framebuffer creation. This way the time of the "tiling" decision is the same as it would be with modifiers. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/display: Honor the offset for plane 0.Bas Nieuwenhuizen1-5/+9
With modifiers I'd like to support non-dedicated buffers for images. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Cc: [email protected] # 5.1.0 Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd: Init modifier field of helper fb.Bas Nieuwenhuizen1-0/+1
Otherwise the field ends up being used uninitialized when enabling modifiers, failing validation with high likelyhood. v4: Use memset Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> (for v1) Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/display: Do not silently accept DCC for multiplane formats.Bas Nieuwenhuizen1-1/+1
Silently accepting it could result in corruption. Signed-off-by: Bas Nieuwenhuizen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/pm: fix compile warnings about variable used uninitializedEvan Quan1-3/+2
Fix the compile warnings below: >> drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_hwmgr.c:1743:13: warning: variable 'min' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized] >> drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_hwmgr.c:1743:13: warning: variable 'max' is used uninitialized whenever 'if' condition is false [-Wsometimes-uninitialized] Signed-off-by: Evan Quan <[email protected]> Reported-by: kernel test robot <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/pm: fix compile warning about missing prototype for functionEvan Quan1-1/+1
Fix the warning below: >> drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ppatomctrl.c:1234:29: warning: no previous prototype for function 'asic_internal_ss_get_ss_table' [-Wmissing-prototypes] ATOM_ASIC_INTERNAL_SS_INFO *asic_internal_ss_get_ss_table(void *device) ^ drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ppatomctrl.c:1234:1: note: declare 'static' if the function is not intended to be used outside of this translation unit ATOM_ASIC_INTERNAL_SS_INFO *asic_internal_ss_get_ss_table(void *device) ^ static 1 warning generated. Signed-off-by: Evan Quan <[email protected]> Reported-by: kernel test robot <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amdgpu/powerplay: Only apply optimized mclk dpm policy on polarisAlex Deucher1-12/+18
Leads to improper dpm on older parts. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1353 Fixes: 8d89b96fe797 ("drm/amd/powerplay: optimize the mclk dpm policy settings") Reviewed-by: Evan Quan <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/pm: do not use ixFEATURE_STATUS for checking smc runningEvan Quan1-4/+1
This reverts commit f87812284172a9809820d10143b573d833cd3f75 ("drm/amdgpu: Fix bug where DPM is not enabled after hibernate and resume"). It was intended to fix Hawaii S4(hibernation) issue but break S3. As ixFEATURE_STATUS is filled with garbage data on resume which can be only cleared by reloading smc firmware(but that will involve many changes). So, we will revert this S4 fix and seek a new way. Signed-off-by: Evan Quan <[email protected]> Tested-by: Sandeep Raghuraman <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/pm: perform SMC reset on suspend/hibernationEvan Quan5-0/+39
So that the succeeding resume can be performed based on a clean state. Signed-off-by: Evan Quan <[email protected]> Tested-by: Sandeep Raghuraman <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/pm: enable baco reset for HawaiiEvan Quan1-1/+3
Which can be used for S4(hibernation) support. Signed-off-by: Evan Quan <[email protected]> Tested-by: Sandeep Raghuraman <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/pm: correct the baco reset sequence for CI ASICsEvan Quan1-3/+4
Correct some registers bitmasks and add mmBIOS_SCRATCH_7 reset. Signed-off-by: Evan Quan <[email protected]> Tested-by: Sandeep Raghuraman <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amdgpu: perform srbm soft reset always on SDMA resumeEvan Quan1-15/+12
This can address the random SDMA hang after pci config reset seen on Hawaii. Signed-off-by: Evan Quan <[email protected]> Tested-by: Sandeep Raghuraman <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amdgpu: rename nv_is_headless_sku()Flora Cui1-3/+3
for headless NAVI ASICs Signed-off-by: Flora Cui <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amdgpu: disable DCN and VCN for Navi14 0x7340/C9 SKUFlora Cui1-2/+3
Navi14 0x7340/C9 SKU has no display and video support, remove them. Signed-off-by: Flora Cui <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drivers: amdgpu: Correct spelling defalut to default in commentBhaskar Chowdhury1-1/+1
Correct spelling in one of the comment. s/defalut/default/p Signed-off-by: Bhaskar Chowdhury <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amdgpu: fix incorrect enum typeArnd Bergmann1-2/+2
core_link_write_dpcd() returns enum dc_status, not ddc_result: display/dc/core/dc_link_dp.c: In function 'dp_set_panel_mode': display/dc/core/dc_link_dp.c:4237:11: warning: implicit conversion from 'enum dc_status' to 'enum ddc_result' [-Wenum-conversion] Avoid the warning by using the correct enum in the caller. Fixes: 0b226322434c ("drm/amd/display: Synchronous DisplayPort Link Training") Signed-off-by: Arnd Bergmann <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/display: remove unneeded semicolonTom Rix2-2/+2
A semicolon is not needed after a switch statement. Signed-off-by: Tom Rix <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amdgpu: remove unneeded semicolonTom Rix1-1/+1
A semicolon is not needed after a switch statement. Signed-off-by: Tom Rix <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/pm: fix out-of-bound read on pptable->SkuReservedColin Ian King1-1/+0
A recent change added two uint16_t elements to PPTable_t and reduced the uint32_t array down to 8 elements. This results in the dev_info printing of pptable->SkuReserved[8] accessing a value that is out-of-range on array SkuReserved. The array has been shrunk by 1 element, so remove this extraneous dev_info message. Addresses-Coverity: ("Out-of-bounds read") Fixes: 1dc3c5a95b08 ("drm/amd/pm: update driver if file for sienna cichlid") Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/display: remove useless if/elseZou Wei1-7/+4
Fix the following coccinelle report: ./drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c:1367:3-5: WARNING: possible condition with no effect (if == else) Both branches are the same, so remove the if/else altogether. Fixes: 81875979f0b2 ("drm/amd/display: Remove extra pairs of parentheses in dce_calcs.c") Reported-by: Hulk Robot <[email protected]> Signed-off-by: Zou Wei <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amdgpu: drop CONFIG_DRM_AMD_DC_DCN3_01 from atomfirmware.hAlex Deucher1-4/+0
Not needed. Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amdgpu/display: remove dal_cmd_tbl_helper_dcn2_get_table2Alex Deucher2-43/+0
It's unused and identical to dal_cmd_tbl_helper_dce112_get_table2. Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amdgpu/display: remove DRM_AMD_DC_GREEN_SARDINEAlex Deucher5-20/+0
No need for a separate config option at this point. Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amdgpu/powerplay: Only apply optimized mclk dpm policy on polarisAlex Deucher1-12/+18
Leads to improper dpm on older parts. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1353 Fixes: 8d89b96fe797 ("drm/amd/powerplay: optimize the mclk dpm policy settings") Reviewed-by: Evan Quan <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/pm: do not use ixFEATURE_STATUS for checking smc runningEvan Quan1-4/+1
This reverts commit f87812284172a9809820d10143b573d833cd3f75 ("drm/amdgpu: Fix bug where DPM is not enabled after hibernate and resume"). It was intended to fix Hawaii S4(hibernation) issue but break S3. As ixFEATURE_STATUS is filled with garbage data on resume which can be only cleared by reloading smc firmware(but that will involve many changes). So, we will revert this S4 fix and seek a new way. Signed-off-by: Evan Quan <[email protected]> Tested-by: Sandeep Raghuraman <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/pm: perform SMC reset on suspend/hibernationEvan Quan5-0/+39
So that the succeeding resume can be performed based on a clean state. Signed-off-by: Evan Quan <[email protected]> Tested-by: Sandeep Raghuraman <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/pm: enable baco reset for HawaiiEvan Quan1-1/+3
Which can be used for S4(hibernation) support. Signed-off-by: Evan Quan <[email protected]> Tested-by: Sandeep Raghuraman <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/pm: correct the baco reset sequence for CI ASICsEvan Quan1-3/+4
Correct some registers bitmasks and add mmBIOS_SCRATCH_7 reset. Signed-off-by: Evan Quan <[email protected]> Tested-by: Sandeep Raghuraman <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amdgpu: perform srbm soft reset always on SDMA resumeEvan Quan1-15/+12
This can address the random SDMA hang after pci config reset seen on Hawaii. Signed-off-by: Evan Quan <[email protected]> Tested-by: Sandeep Raghuraman <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/amdgpu: simplify pa_sc_tile_steering_override checkChengming Gui1-4/+1
Use ">= CHIP_SIENNA_CICHLID" to replace per asic check Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking.Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30amdgpu:Add flag for updating MGCG on GFX10Jinzhou.Su1-0/+1
Add RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK Signed-off-by: Jinzhou.Su <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amdgpu: cleanup gmc_v9_0_process_interruptChristian König1-92/+91
First of all don't snprintf into a char buffer allocated on the stack with a constant hubname. Then cleanup to exit the function early in case of a ratelimit or SRIOV. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/display: allow 18 bit dp output on DCN3Dmytro Laktyushkin2-15/+1
We need this to pass dp compliance. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Chris Park <[email protected]> Reviewed-by: Nikola Cornij <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amdkfd: Fix getting unique_id in topologyKent Russell3-6/+1
Since the unique_id is now obtained in amdgpu in smu_late_init, topology misses getting the value during KFD device initialization. To work around this, we use amdgpu_amdkfd_get_unique_id to get the unique_id at read time. Due to this, we can remove unique_id from the kfd_dev structure, since we only need it in the KFD node properties struct Signed-off-by: Kent Russell <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30amdgpu: Add GFX MGCG and MGLS for vangoghJinzhou.Su1-1/+5
add GFX Medium Grain Light Sleep support for vangogh add AMD_CG_SUPPORT_GFX_CP_LS and AMD_CG_SUPPORT_GFX_RLC_LS v2: add GFX Medium Grain Clock Gating Signed-off-by: Jinzhou.Su <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/pm: enable the rest functions of swSMU for vangogh.Xiaojian Du1-3/+0
This patch is to enable the rest functions of swSMU for vangogh. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/pm: add some swSMU functions for vangogh.Xiaojian Du1-73/+338
This patch is to add some swSMU functions for vangogh, to support the sensor info on "hwmon" and pm info. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/pm: add one new function to get 32 bit feature mask for vangoghXiaojian Du2-5/+54
This patch is to add one new function to get 32 bit feature mask for vangogh. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/pm: remove some redundant smu message mapping for vangoghXiaojian Du1-4/+0
This patch is to remove some redundant smu message mapping for vangogh. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/pm: set the initial value of pm info to zeroXiaojian Du1-1/+1
This patch is to set the initial value of pm info to zero. The "value64" is ported to the hwmon and debugfs node, it is a uint64 type. When it is used for NV10/VEGA10/VEGA20, its word size is appropriate, because NV10/VEGA10/VEGA20 has a 64bit smu feature mask, which is separated to high 32bit and low 32bit. But some asic has only 32bit smu feature mask,and this 32bit mask will fill the low 32bit of "value64". So if this "value64" is not initialized to zero, the high 32bit will be filled by a meaningless value, when the whole "value64" is ported to the "SMC Feature Mask" in the "amdgpu_pm_info" on some specific asic, it will be a wrong value. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/pm: update the smu v11.5 driver interface header for vangoghXiaojian Du2-36/+36
This patch is to update the smu v11.5 driver interface header for vangogh. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/pm: add UMD Pstate Msg Parameters for vangogh temporarilyXiaojian Du1-0/+5
This patch is to add UMD Pstate Msg Parameters for vangogh temporarily, the values refer to renoir. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/pm: add new smc message mapping for vangoghXiaojian Du1-0/+24
This patch is to add new smc message mapping for vangogh. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/pm: update the smu v11.5 firmware header for vangoghXiaojian Du1-1/+1
This patch is to update the smu v11.5 firmware header for vangogh. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/pm: update the smu v11.5 smc header for vangoghXiaojian Du1-46/+68
This patch is to update the smu v11.5 smc header for vangogh. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amdgpu: fix the issue of reserving bad pages failedDennis Li4-119/+156
In amdgpu_ras_reset_gpu, because bad pages may not be freed, it has high probability to reserve bad pages failed. Change to reserve bad pages when freeing VRAM. v2: 1. avoid allocating the drm_mm node outside of amdgpu_vram_mgr.c 2. move bad page reserving into amdgpu_ras_add_bad_pages, if vram mgr reserve bad page failed, it will put it into pending list, otherwise put it into processed list; 3. remove amdgpu_ras_release_bad_pages, because retired page's info has been moved into amdgpu_vram_mgr v3: 1. formate code style; 2. rename amdgpu_vram_reserve_scope as amdgpu_vram_reservation; 3. rename scope_pending as reservations_pending; 4. rename scope_processed as reserved_pages; 5. change to iterate over all the pending ones and try to insert them with drm_mm_reserve_node(); v4: 1. rename amdgpu_vram_mgr_reserve_scope as amdgpu_vram_mgr_reserve_range; 2. remove unused include "amdgpu_ras.h"; 3. rename amdgpu_vram_mgr_check_and_reserve as amdgpu_vram_mgr_do_reserve; 4. refine amdgpu_vram_mgr_reserve_range to call amdgpu_vram_mgr_do_reserve. Reviewed-by: Christian König <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Dennis Li <[email protected]> Signed-off-by: Wenhui Sheng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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