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2017-05-24drm/amdgpu: add vm ioctlChunming Zhou3-0/+18
It will be used for reserving vmid for shader debugging that requires a fixed vmid. v2: fix warning (Alex) Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu: Enable chained IB MCBP supportTrigger Huang1-6/+11
Support for MCBP/Virtualization in combination with chained IBs is formal released on firmware feature version #46. So enable it according to firmware feature version, otherwise, world switch will hang. Signed-off-by: Trigger Huang <[email protected]> Reviewed-by: Monk Liu <[email protected]> Reviewed-by: Xiangliang Yu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu:fix get wrong gfx always on cu masks.Rex Zhu4-8/+26
Bug: SWDEV-117987: Always on CU mask broken for gfx7+ Signed-off-by: Rex Zhu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu: fix s3 ring test failed on Vi caused by KIQ enabled.Rex Zhu1-3/+2
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu/virt: change the place of virt_init_settingXiangliang Yu2-10/+10
Change place of virt_init_setting function so that can cover the cg and pg flags configuration. Signed-off-by: Xiangliang Yu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu/virt: bypass cg and pg setting for SRIOVXiangliang Yu1-0/+2
GPU hypervisor cover all settings of CG and PG, so guest doesn't need to do anything. Bypass it. Signed-off-by: Frank Min <[email protected]> Signed-off-by: Xiangliang Yu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu: drop support for per ASIC read registersChristian König2-69/+2
Only per family registers are still used. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu: drop support for untouched registersChristian König5-214/+210
I couldn't figure out what this was original good for, but we don't use it any more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu: delete redundant kiq irq funcs type check in gfx8.Rex Zhu1-4/+0
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu: fix typo in dmesg in gfx_v8_0_kiq_kcq_disable.Rex Zhu1-1/+2
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu: add HDMI audio support for si dce6Xiaojie Yuan1-9/+121
Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu: add DP audio support for si dce6 (v3)Xiaojie Yuan2-36/+433
v2: refine dce_v6_0_audio_endpt_wreg() and unify inconsistent method names v3: fix num_pins for tahiti, pitcairn, verde and oland Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Junwei Zhang <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu/gfx8: move CP_PQ_STATUS after doorbell range setting (v2)Alex Deucher1-3/+2
I'm not sure if the order matters, but it seems like it makes more sense to set this after the range is programmed. v2: rebase (Alex) Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu: set cpg doorbell for fiji and polaris.Rex Zhu1-39/+43
add set_doorbell functions for mec and cpg. Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu/gfx8: unify the HQD deactivation codeAlex Deucher1-22/+20
This could be used in Andres' priority scheduling patch as well. Reviewed-by: Andres Rodriguez <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu/gfx8: enable cp/rlc ints after we disable clockgatingAlex Deucher1-0/+2
Even if we disable clockgating, we still need to make sure the cp/rlc interrupts are enabled for powergating which might still be enabled. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu/gfx7: enable cp/rlc ints after we disable clockgatingAlex Deucher1-4/+7
Even if we disable clockgating, we still need to make sure the cp/rlc interrupts are enabled for powergating which might still be enabled. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu/gfx8: move MEC doorbell range settingAlex Deucher1-14/+12
It's global, not queue specific, so move it out of the kiq register init function. Tested-and-Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu/gfx8: fix resume of KIQ and KCQsAlex Deucher1-13/+13
No need to reset the wptr and clear the rings. The UNMAP_QUEUES packet writes the current MQD state back the MQD on suspend, so there is no need to reset it as well. Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu/gfx8: properly disable the KCQs in hw_finiAlex Deucher1-0/+51
Use the UNMAP_QUEUES packet to have the KIQ properly disable them. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu/gfx8: use new KIQ packet definesAlex Deucher1-5/+7
Rather than open coding them. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu/gfx8: move SET_RESOURCES into the same command streamAlex Deucher1-64/+23
As the KCQ setup. This way we only have to wait once for the entire MEC. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu/gfx8: wait once for all KCQs to be createdAlex Deucher1-26/+31
Rather than waiting for each queue. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu: split gfx_v8_0_kiq_init_queue into twoAlex Deucher1-21/+41
One for KIQ and one for the KCQ. This simplifies the logic and allows for future optimizations. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu/gfx8: wait for completion in KIQ initAlex Deucher1-10/+78
We need to make sure the various init sequences submitted to KIQ complete before testing the rings. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24Revert "drm/amd/amdgpu: Disable GFX_PG on Carrizo until compute issues solved"Alex Deucher1-1/+1
Re-enable GFX PG. It's working properly with MEC now that KIQ is enabled. Reviewed-by: Samuel Li <[email protected]> This reverts commit e9ef19aa1bdeac380662a112f1d03a7c3477527f.
2017-05-24drm/amdgpu: Switch baremetal to use KIQ for compute ring management. (v3)David Panariti2-302/+26
KIQ is the Kernel Interface Queue for managing the MEC. Rather than setting up rings via direct MMIO of ring registers, the rings are configured via special packets sent to the KIQ. The allows the MEC to better manage shared resources and certain power events. v2: squash in s3/s4 fix from Rex v3: further fixes from Rex Signed-off-by: David Panariti <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Tom St Denis <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu/gfx8: set doorbell range for polaris as wellAlex Deucher1-2/+5
Add missing chips to the doorbell range setup. These were missed in the KIQ code. Fixes power and performance regressions with KIQ. Spotted by Rex. Tested-and-Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu/gfx8: add additional MQD initializationAlex Deucher1-0/+14
Need to properly set the MTYPE and ROQ space setting. This should fix performance regressions with KIQ enabled. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amd/powerplay: fix pcie dpm table for vega10Eric Huang1-1/+1
This resolves pcie low speed problem. Signed-off-by: Eric Huang <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amd/powerplay: update vega10 smu interface version to E.Rex Zhu1-19/+19
need update smu firmware to version 0x1c20. Signed-off-by: Rex Zhu <[email protected]> Reviewws-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amd/powerplay: delete dead code in vega10_thermal.cRex Zhu1-3/+0
Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amd/powerplay: Add Vega10 Powertune Table v3 support.Rex Zhu3-3/+77
Handle the latest powerplay table format; includes Boost State support. Signed-off-by: Rex Zhu <[email protected]> Reviewws-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amd/powerplay: convert from number of lanes to lane bits on vega10Rex Zhu1-5/+5
We need a mask. Signed-off-by: Rex Zhu <[email protected]> Reviewws-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amd/powerplay: fix bug in processing CKS_Enable bit.Rex Zhu1-1/+1
Typo in the mask. Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amd/powerplay: add avfs fuse overdriver func.Rex Zhu5-3/+1368
Add a function to look up the AVFS fuse values for vega10 These are used to populate the avfs fuse table in the smu. Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amd/powerplay: add power profile support for Vega10 (v2)Eric Huang1-0/+92
This implements the workload specific interface of optimized compute power profile for Vega10. v2: squash in fix (Tom) Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu/gfx9: drop duplicate gfx info init (v3)Alex Deucher1-10/+0
Taken care of by gpu info firmware now. v2: rebase v3: rework based on latest firmware Reviewed-by: Junwei Zhang <[email protected]> Tested-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu: parse the gpu_info firmware (v4)Alex Deucher1-0/+98
And populate the gfx structures from it. v2: update the structures updated by the table v3: rework based on new table structure v4: simplify things Reviewed-by: Junwei Zhang <[email protected]> Tested-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu: add gpu_info firmware (v3)Alex Deucher2-0/+46
Add a new gpu info firmware to store gpu specific configuration data. This allows us to store hw constants in a unified place. v2: adjust structure and elements v3: further restructure Reviewed-by: Junwei Zhang <[email protected]> Tested-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amd/powerplay: fix a signedness bugsDan Carpenter1-1/+1
Smatch complains about a signedness bug here: vega10_hwmgr.c:4202 vega10_force_clock_level() warn: always true condition '(i >= 0) => (0-u32max >= 0)' Fixes: 7b52db39a4c2 ("drm/amd/powerplay: fix bug sclk/mclk level can't be set on vega10.") Signed-off-by: Dan Carpenter <[email protected]> Reviewed-by: Eric Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu: fix NULL pointer panic of emit_gds_switchChunming Zhou1-1/+1
[ 338.384770] BUG: unable to handle kernel NULL pointer dereference at (null) [ 338.384817] IP: [< (null)>] (null) [ 338.385505] RIP: 0010:[<0000000000000000>] [< (null)>] (null) [ 338.385950] Call Trace: [ 338.385993] [<ffffffffa05d2313>] ? amdgpu_vm_flush+0x283/0x400 [amdgpu] [ 338.386025] [<ffffffff811818d3>] ? printk+0x4d/0x4f [ 338.386074] [<ffffffffa05d4906>] amdgpu_ib_schedule+0x4a6/0x4d0 [amdgpu] [ 338.386140] [<ffffffffa0673e54>] amdgpu_job_run+0x64/0x180 [amdgpu] [ 338.386203] [<ffffffffa0672e09>] amd_sched_main+0x2e9/0x4a0 [amdgpu] [ 338.386232] [<ffffffff810bfce0>] ? prepare_to_wait_event+0x110/0x110 [ 338.386295] [<ffffffffa0672b20>] ? amd_sched_select_entity+0xe0/0xe0 [amdgpu] [ 338.386327] [<ffffffff8109b423>] kthread+0xd3/0xf0 [ 338.386349] [<ffffffff8109b350>] ? kthread_park+0x60/0x60 [ 338.386376] [<ffffffff817e1ee5>] ret_from_fork+0x25/0x30 [ 338.386401] Code: Bad RIP value. [ 338.386420] RIP [< (null)>] (null) [ 338.386443] RSP <ffffc90001bd7d40> [ 338.386458] CR2: 0000000000000000 [ 338.398508] ---[ end trace 4c66fcdc74b9a0a2 ]--- Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amd/powerplay/smu7: disable mclk switching for high refresh ratesAlex Deucher1-1/+2
Even if the vblank period would allow it, it still seems to be problematic on some cards. bug: https://bugs.freedesktop.org/show_bug.cgi?id=96868 Cc: [email protected] Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amd/powerplay/smu7: add vblank check for mclk switching (v2)Alex Deucher1-4/+27
Check to make sure the vblank period is long enough to support mclk switching. v2: drop needless initial assignment (Nils) bug: https://bugs.freedesktop.org/show_bug.cgi?id=96868 Cc: [email protected] Acked-by: Christian König <[email protected]> Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu/ci: disable mclk switching for high refresh rates (v2)Alex Deucher1-0/+6
Even if the vblank period would allow it, it still seems to be problematic on some cards. v2: fix logic inversion (Nils) bug: https://bugs.freedesktop.org/show_bug.cgi?id=96868 Cc: [email protected] Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu: fix fundamental suspend/resume issueChristian König6-54/+30
Reinitializing the VM manager during suspend/resume is a very very bad idea since all the VMs are still active and kicking. This can lead to random VM faults after resume when new processes become the same client ID assigned. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2017-05-24drm/amd/powerplay: fix a signedness bugsDan Carpenter1-1/+1
Smatch complains about a signedness bug here: vega10_hwmgr.c:4202 vega10_force_clock_level() warn: always true condition '(i >= 0) => (0-u32max >= 0)' Fixes: 7b52db39a4c2 ("drm/amd/powerplay: fix bug sclk/mclk level can't be set on vega10.") Signed-off-by: Dan Carpenter <[email protected]> Reviewed-by: Eric Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amdgpu: fix NULL pointer panic of emit_gds_switchChunming Zhou1-1/+1
[ 338.384770] BUG: unable to handle kernel NULL pointer dereference at (null) [ 338.384817] IP: [< (null)>] (null) [ 338.385505] RIP: 0010:[<0000000000000000>] [< (null)>] (null) [ 338.385950] Call Trace: [ 338.385993] [<ffffffffa05d2313>] ? amdgpu_vm_flush+0x283/0x400 [amdgpu] [ 338.386025] [<ffffffff811818d3>] ? printk+0x4d/0x4f [ 338.386074] [<ffffffffa05d4906>] amdgpu_ib_schedule+0x4a6/0x4d0 [amdgpu] [ 338.386140] [<ffffffffa0673e54>] amdgpu_job_run+0x64/0x180 [amdgpu] [ 338.386203] [<ffffffffa0672e09>] amd_sched_main+0x2e9/0x4a0 [amdgpu] [ 338.386232] [<ffffffff810bfce0>] ? prepare_to_wait_event+0x110/0x110 [ 338.386295] [<ffffffffa0672b20>] ? amd_sched_select_entity+0xe0/0xe0 [amdgpu] [ 338.386327] [<ffffffff8109b423>] kthread+0xd3/0xf0 [ 338.386349] [<ffffffff8109b350>] ? kthread_park+0x60/0x60 [ 338.386376] [<ffffffff817e1ee5>] ret_from_fork+0x25/0x30 [ 338.386401] Code: Bad RIP value. [ 338.386420] RIP [< (null)>] (null) [ 338.386443] RSP <ffffc90001bd7d40> [ 338.386458] CR2: 0000000000000000 [ 338.398508] ---[ end trace 4c66fcdc74b9a0a2 ]--- Signed-off-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amd/powerplay/smu7: disable mclk switching for high refresh ratesAlex Deucher1-1/+2
Even if the vblank period would allow it, it still seems to be problematic on some cards. bug: https://bugs.freedesktop.org/show_bug.cgi?id=96868 Cc: [email protected] Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-05-24drm/amd/powerplay/smu7: add vblank check for mclk switching (v2)Alex Deucher1-4/+27
Check to make sure the vblank period is long enough to support mclk switching. v2: drop needless initial assignment (Nils) bug: https://bugs.freedesktop.org/show_bug.cgi?id=96868 Cc: [email protected] Acked-by: Christian König <[email protected]> Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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