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path: root/drivers/gpu/drm/amd
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2017-06-15drm/amdgpu/gfx9: fix compute ring doorbell indexAlex Deucher1-1/+1
This got lost when the code was revamped. Copy/paste bug from gfx8. Reported-by: Evan Quan <[email protected]> Fixes: 78c168342 (drm/amdgpu: allow split of queues with kfd at queue granularity v4) Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-15drm/amd/amdgpu: Rename KIQ ring to avoid spacesTom St Denis1-1/+1
Swap space for underscore in ring name. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-15drm/amd/amdgpu: gfx9 tidy ups (v2)Tom St Denis1-19/+7
A couple of simple tidy ups to register programming. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> (v2): Avoid using 'data' uninitialized Signed-off-by: Alex Deucher <[email protected]>
2017-06-15drm/amdgpu: add contiguous flag in ucode bo createhorchen1-1/+2
Under VF environment, the ucode would be settled to the visible VRAM, As it would be pinned to the visible VRAM, it's better to add contiguous flag,otherwise it need to move gpu address during the pin process. This movement is not necessary. Signed-off-by: horchen <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-15drm/amdgpu: fix missed gpu info firmware when cache firmware during S3Huang Rui2-8/+13
gpu_info firmware is released after data is used. But when system enters into suspend, upper class driver will cache all firmware names. At that time, gpu_info will be failing to load. It seems an upper class issue, that we should not release gpu_info firmware until device finished. [ 903.236589] cache_firmware: amdgpu/vega10_sdma1.bin [ 903.236590] fw_set_page_data: fw-amdgpu/vega10_sdma1.bin buf=ffff88041eee10c0 data=ffffc90002561000 size=17408 [ 903.236591] cache_firmware: amdgpu/vega10_sdma1.bin ret=0 [ 903.464160] __allocate_fw_buf: fw-amdgpu/vega10_gpu_info.bin buf=ffff88041eee2c00 [ 903.471815] (NULL device *): loading /lib/firmware/updates/4.11.0-custom/amdgpu/vega10_gpu_info.bin failed with error -2 [ 903.482870] (NULL device *): loading /lib/firmware/updates/amdgpu/vega10_gpu_info.bin failed with error -2 [ 903.492716] (NULL device *): loading /lib/firmware/4.11.0-custom/amdgpu/vega10_gpu_info.bin failed with error -2 [ 903.503156] (NULL device *): direct-loading amdgpu/vega10_gpu_info.bin Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-15drm/amdgpu: export test ib debugfs interfaceHuang Rui1-0/+54
As Christian and David's suggestion, submit the test ib ring debug interfaces. It's useful for debugging with the command submission without VM case. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-15drm/amd/powerplay: add GPU power display for vega10Eric Huang1-0/+20
Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-15drm/amd/powerplay: update vega10_ppsmc.hEric Huang1-1/+2
Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-15drm/amdgpu: avoid to reset wave_front_size to 0Hawking Zhang1-2/+0
No need to clear it. The values are set explicitly. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-15drm/amdgpu: add new member in gpu_info fwHawking Zhang3-0/+11
Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-14drm/amdgpu: Fix overflow of watermark calcs at > 4k resolutions.Mario Kleiner4-8/+20
Commit d63c277dc672e0 ("drm/amdgpu: Make display watermark calculations more accurate") made watermark calculations more accurate, but not for > 4k resolutions on 32-Bit architectures, as it introduced an integer overflow for those setups and resolutions. Fix this by proper u64 casting and division. Signed-off-by: Mario Kleiner <[email protected]> Reported-by: Ben Hutchings <[email protected]> Fixes: d63c277dc672 ("drm/amdgpu: Make display watermark calculations more accurate") Cc: Ben Hutchings <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Signed-off-by: Alex Deucher <[email protected]>
2017-06-09drm/amdgpu/gfx: fix MEC interrupt enablement for pipes != 0Alex Deucher3-49/+124
The interrupt registers are not indexed. Fixes: 763a47b8e (drm/amdgpu: teach amdgpu how to enable interrupts for any pipe v3) Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-09drm/amd/powerplay: fix copy error in powerplay.Rex Zhu1-3/+3
v2: fix typos. should disable led dpm feature when stop dpm. Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-09drm/amdgpu: move comment to the right placeAlex Xie1-2/+2
Signed-off-by: Alex Xie <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-09drm/amdgpu: fix a typo in commentAlex Xie1-1/+1
Signed-off-by: Alex Xie <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-09drm/amdgpu: remove duplicate function prototypesAlex Xie1-1/+0
There are two identical function prototypes in same header file Signed-off-by: Alex Xie <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-09drm/amdgpu: Support page table update via CPUHarish Kasiviswanathan1-1/+87
v2: Fix logical mistake. If CPU update failed amdgpu_vm_bo_update_mapping() would not return and instead fall through to SDMA update. Minor change due to amdgpu_vm_bo_wait() prototype change Signed-off-by: Harish Kasiviswanathan <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-09drm/amdgpu: Support page directory update via CPUHarish Kasiviswanathan1-42/+119
If amdgpu.vm_update_context param is set to use CPU, then Page Directories will be updated by CPU instead of SDMA v2: Call amdgpu_vm_bo_wait before updating the page tables to ensure the PD/PT BOs are free v3: Minor changes - due to amdgpu_vm_bo_wait() prototype change, local variable declaration order and function comments. Signed-off-by: Harish Kasiviswanathan <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-09drm/amdgpu: Add amdgpu_sync_waitHarish Kasiviswanathan2-0/+20
v2: Add intr option Helper function useful for CPU update of VM page tables. Also useful if kernel have to synchronously wait till VM page tables are updated. Signed-off-by: Harish Kasiviswanathan <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-09drm/amdgpu: Add vm context module paramHarish Kasiviswanathan5-3/+61
Add VM update mode module param (amdgpu.vm_update_mode) that can used to control how VM pde/pte are updated for Graphics and Compute. BIT0 controls Graphics and BIT1 Compute. BIT0 [= 0] Graphics updated by SDMA [= 1] by CPU BIT1 [= 0] Compute updated by SDMA [= 1] by CPU By default, only for large BAR system vm_update_mode = 2, indicating that Graphics VMs will be updated via SDMA and Compute VMs will be updated via CPU. And for all all other systems (by default) vm_update_mode = 0 Signed-off-by: Harish Kasiviswanathan <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-08drm/amdgpu: drop deprecated drm_get_pci_dev and drm_put_devAlex Deucher1-2/+26
Open code them so we can adjust the order in the driver more easily. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-08drm/amdgpu: call pci_[un]register_driver() directlyAlex Deucher1-2/+2
Rather than calling the deprecated drm_pci_init() and drm_pci_exit() which just wrapped the pci functions anyway. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-08drm/amdgpu/radeon: Use radeon by default for CIK GPUsMichel Dänzer3-8/+11
Even if CONFIG_DRM_AMDGPU_CIK is enabled. There is no feature parity yet for CIK, in particular amdgpu doesn't support HDMI/DisplayPort audio without DC. v2: * Clarify the lack of feature parity being related to HDMI/DP audio. * Fix "SI" typo in DRM_AMDGPU_CIK help entry. Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Michel Dänzer <[email protected]>
2017-06-08drm/amdgpu: Update Kconfig help for SI and CIK supportFelix Kuehling1-4/+12
Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Michel Dänzer <[email protected]>
2017-06-08drm/amdgpu: Add module param to control SI supportFelix Kuehling3-0/+26
If AMDGPU supports SI, add a module parameter to control SI support. It's off by default in AMDGPU as long as SI suppost is experimental, while it is on by default in radeon. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Michel Dänzer <[email protected]> [ Michel Dänzer: Squash in amdgpu_si_support initialization fix ] Signed-off-by: Michel Dänzer <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]>
2017-06-08drm/amdgpu: Add module param to control CIK supportFelix Kuehling3-0/+26
If AMDGPU supports CIK, add a module parameter to control CIK support. It's on by default in AMDGPU, while it is off by default in radeon. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Michel Dänzer <[email protected]>
2017-06-07drm/amdgpu/gfx: consolidate mqd buffer setup codeAlex Deucher4-132/+74
It was duplicated across multiple generations. Reviewed-by: Alex Xie <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-07drm/amdgpu/gfx: move mec parameter setup into sw_initAlex Deucher3-47/+47
This will allow us to share more mec code. Reviewed-by: Alex Xie <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-07drm/amdgpu/gfx: move more common KIQ code to amdgpu_gfx.cAlex Deucher4-211/+122
Lots more common stuff. Reviewed-by: Alex Xie <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-07drm/amdgpu: move mec queue helpers to amdgpu_gfx.hAlex Deucher6-39/+40
They are gfx related, not general helpers. Reviewed-by: Alex Xie <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-07drm/amdgpu/gfx9: remove spurious line in kiq setupAlex Deucher1-1/+0
This overrode what queue was actually assigned for kiq. Reviewed-by: Alex Xie <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-07drm/amdgpu/gfx8: whitespace changeAlex Deucher1-1/+2
Make it consistent. Reviewed-by: Alex Xie <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-07drm/amdgpu/gfx9: Raven has two MECsAlex Deucher1-0/+1
This was missed when Andres' queue patches were rebased. Fixes: 42794b27 (drm/amdgpu: take ownership of per-pipe configuration v3) Reviewed-by: Alex Xie <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-07drm/amdgpu: move gfx_v*_0_compute_queue_acquire to common codeAlex Deucher5-114/+42
Same function was duplicated in all gfx IP files. Reviewed-by: Alex Xie <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-07drm/amdgpu: fix mec queue policy on single MEC asicsAlex Deucher3-9/+27
Fixes hangs on single MEC asics. Fixes: 2ed286fb434 (drm/amdgpu: new queue policy, take first 2 queues of each pipe v2) Reviewed-by: Alex Xie <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-07drm/amdgpu/gfx: create a common bitmask function (v2)Alex Deucher5-40/+25
The same function was duplicated in all the gfx IPs. Use a single implementation for all. v2: use static inline (Alex Xie) Reviewed-by: Alex Xie <[email protected]> Suggested-by: Andres Rodriguez <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-07drm/amdgpu/gfx8: drop per-APU CU limitsAlex Deucher1-69/+2
Always use the max for the family rather than the per sku limits. This makes sure the mask is always the max size to avoid reporting the wrong number of CUs. Reviewed-by: Alex Xie <[email protected]> Reviewed-by: Andres Rodriguez <[email protected]> Cc: [email protected] Signed-off-by: Alex Deucher <[email protected]>
2017-06-06drm/amdgpu/gfx6: properly cache mc_arb_ramcfgAlex Deucher1-1/+2
This was missing for gfx6. Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2017-06-06drm/amdgpu/gfx9: new queue policy, take first 2 queues of each pipeAlex Deucher1-2/+2
Instead of taking the first pipe and giving the rest to kfd, take the first 2 queues of each pipe. Effectively, amdgpu and amdkfd own the same number of queues. But because the queues are spread over multiple pipes the hardware will be able to better handle concurrent compute workloads. amdgpu goes from 1 pipe to 4 pipes, i.e. from 1 compute threads to 4 amdkfd goes from 3 pipe to 4 pipes, i.e. from 3 compute threads to 4 gfx9 was missed when this patch set was rebased to include gfx9. Acked-by: Tom St Denis <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Andres Rodriguez <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-06drm/amdgpu/gfx9: allocate queues horizontally across pipesAlex Deucher1-63/+52
Pipes provide better concurrency than queues, therefore we want to make sure that apps use queues from different pipes whenever possible. Optimize for the trivial case where an app will consume rings in order, therefore we don't want adjacent rings to belong to the same pipe. gfx9 was missed when these patches were rebased. Reviewed-by: Tom St Denis <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Andres Rodriguez <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-06drm/amd/powerplay: fix memory leak in cz_hwmgr backendHawking Zhang1-0/+6
vddc_dep_on_dal_pwrl is allocated and initialized in cz_hwmgr_backend_init Thus free the memory in cz_hwmgr_backend_fini Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2017-06-06drm/amd/powerplay: fix memory leak in rv_hwmgr backendHawking Zhang1-0/+10
vddc_dep_on_dal_pwrl and vq_budgeting_table are allocated and initialized in rv_hwmgr_backend_init. Thus free the memory in rv_hwmgr_backend_fini Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-06drm/amd/powerplay: add sclk and mclk overdrive for vega10Eric Huang1-15/+133
For overclocking sclk and mclk. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-06drm/amd/powerplay: fix populate dpm level failed when s3 on vega10.Rex Zhu1-7/+6
As the min clk may be large than boot level can support. in this case, just ignore the min clk. Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-06drm/amdgpu: update to use RREG32_SOC15/WREG32_SOC15 for gmc9Huang Rui1-5/+5
Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-06drm/amdgpu: update to use RREG32_SOC15/WREG32_SOC15 for mmhubHuang Rui1-94/+83
Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-06drm/amdgpu: update to use RREG32_SOC15/WREG32_SOC15 for gfxhubHuang Rui1-77/+64
Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-06drm/amdgpu: fix the gart table cleared issue for S3Huang Rui6-1/+14
Something writes over the first 8 MB so reserve this on vega10 until we root cause it. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-06drm/amdgpu: add ip block number printsHuang Rui1-0/+3
User is able to follow the ip block number to write the ip_block_mask for selecting the one which user would like to enable. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-06-06drm/amdgpu: add ip name print for selecting ips with ip_block_maskHuang Rui1-1/+2
Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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