aboutsummaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd/pm
AgeCommit message (Collapse)AuthorFilesLines
2020-10-07drm/amdgpu/swsmu: fix ARC build errorsAlex Deucher2-4/+24
We want to use the dev_* functions here rather than the pr_* variants. Switch to using dev_warn() which mirrors what we do on other asics. Fixes the following build errors on ARC: ../drivers/gpu/drm/amd/amdgpu/../powerplay/navi10_ppt.c: In function 'navi10_fill_i2c_req': ../arch/arc/include/asm/bug.h:24:2: error: implicit declaration of function 'pr_warn'; did you mean 'drm_warn'? [-Werror=implicit-function-declaration] ../drivers/gpu/drm/amd/amdgpu/../powerplay/sienna_cichlid_ppt.c: In function 'sienna_cichlid_fill_i2c_req': ../arch/arc/include/asm/bug.h:24:2: error: implicit declaration of function 'pr_warn'; did you mean 'drm_warn'? [-Werror=implicit-function-declaration] Reported-by: kernel test robot <[email protected]> Cc: Randy Dunlap <[email protected]> Cc: Evan Quan <[email protected]> Cc: Vineet Gupta <[email protected]> Cc: [email protected] Acked-by: Randy Dunlap <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/powerplay: add vangogh ppt into swSMUHuang Rui2-0/+5
This patch is to add vangogh ppt funcions into swSMU block. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amd/powerplay: partially enable swsmu for vangoghHuang Rui1-0/+6
This patch is to partially enable swSMU for vangogh for the moment. Signed-off-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu/powerplay: add smu initialize funcitons for vangogh (v4)Xiaojian Du2-0/+384
This patch is to add smu initialize functions for vangogh. v2: squash in updates v3: drop duplicate table entries v4: rebase fixes Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu/powerplay: add vangogh asic name in smu v11 (v2)Xiaojian Du2-0/+4
This patch is to add vangogh asic name in smu v11. v2: drop smu firmware name (N/A for VG) Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu/powerplay: add smu v11.5 smc header for vangoghXiaojian Du1-0/+86
This patch is to add smu v11.5 smc header for vangogh. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu/powerplay: add smu v11.5 firmware header for vangogh (v2)Xiaojian Du1-0/+120
This patch is to add smu v11.5 firmware header for vangogh v2: squash in updates Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/admgpu/powerplay: add smu v11.5 driver interface header for vangoghXiaojian Du1-0/+239
This patch is to add smu v11.5 driver interface header for vangogh. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-05drm/amdgpu/powerplay: add new smu messages and feature masks for vangogh (v2)Xiaojian Du1-6/+47
This patch is to add new smu messages and feature masks for vangogh. v2: squash in updates and typo fixes Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-01drm/amdgpu/swsmu: add interrupt work handler for smu11 partsAlex Deucher5-2/+13
We need to schedule the smu AC/DC interrupt ack to avoid potentially sleeping if the smu message mutex is contended. Fixes: e1188aacad1730 ("drm/amdgpu/smu11: add support for SMU AC/DC interrupts") Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-01drm/amdgpu/swsmu: add interrupt work functionAlex Deucher2-0/+17
So we can schedule work from interrupts. This might include long tasks or things that could sleep. Fixes: e1188aacad1730 ("drm/amdgpu/smu11: add support for SMU AC/DC interrupts") Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-29drm/amdgpu/swsmu/smu12: fix force clock handling for mclkAlex Deucher1-3/+5
The state array is in the reverse order compared to other asics (high to low rather than low to high). Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1313 Reviewed-by: Prike Liang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-29drm/amd/powerplay: add one sysfs file to support the feature to modify gfx ↵Xiaojian Du6-2/+117
clock on Raven/Raven2/Picasso APU. This patch is to add one sysfs file -- "pp_od_clk_voltage" for Raven/Raven2/Picasso APU, which is only used by dGPU like VEGA10. This sysfs file supports the feature to modify gfx engine clock(Mhz units), it can be used to configure the min value and the max value for gfx clock limited in the safe range. Command guide: echo "s level clock" > pp_od_clk_voltage s - adjust teh sclk level level - 0 or 1, "0" represents the min value, "1" represents the max value clock - the clock value(Mhz units), like 400, 800 or 1200, the value must be within the OD_RANGE limits. Example: $ cat pp_od_clk_voltage OD_SCLK: 0: 200Mhz 1: 1400Mhz OD_RANGE: SCLK: 200MHz 1400MHz $ echo "s 0 600" > pp_od_clk_voltage $ echo "s 1 1000" > pp_od_clk_voltage $ cat pp_od_clk_voltage OD_SCLK: 0: 600Mhz 1: 1000Mhz OD_RANGE: SCLK: 200MHz 1400MHz Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-25drm/amd/pm: fix screen flicker seen on Navi14 with 2*4K monitorsEvan Quan1-31/+12
Revert the guilty change introduced by the commit below: drm/amd/pm: postpone SOCCLK/UCLK enablement after DAL initialization(V2) Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-25drm/amdgpu: Remove some useless codeEmily.Deng1-7/+0
Signed-off-by: Emily.Deng <[email protected]> Reviewed-by: Frank Min <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-25drm/amd: Skip not used microcode loading in SRIOVJingwen Chen2-9/+14
smc, sdma, sos, ta and asd fw is not used in SRIOV. Skip them to accelerate sw_init for navi12. v2: skip above fw in SRIOV for vega10 and sienna_cichlid v3: directly skip psp fw loading in SRIOV Signed-off-by: Jingwen Chen <[email protected]> Reviewed-by: Emily.Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-25drm/amd/pm: Skip use smc fw data in SRIOVJingwen Chen1-29/+32
smc fw is not needed in SRIOV, thus driver should not try to get smc fw data. Signed-off-by: Jingwen Chen <[email protected]> Reviewed-by: Emily.Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-22drm/amd/pm: update driver if file for sienna cichlidLikun Gao2-3/+3
Update driver if file for sienna cichlid. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-22drm/amd/pm: drop redundant watermarks bitmap settingEvan Quan1-5/+0
As this is already set inside the implementation of smu_set_watermarks_table(). Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-22drm/amd/pm: decouple the watermark table setting from socclk/uclk dpmsEvan Quan1-8/+7
As they have no real dependence. And for Navi1x, the socclk/uclk dpms are enabled after DAL initialization. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-22drm/amd/pm: correct the pmfw version check for Navi14Evan Quan1-3/+4
Otherwise, that will be always true for Navi14. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-22drm/amd/pm: Removed fixed clock in auto mode DPMSudheesh Mavila1-4/+6
SMU10_UMD_PSTATE_PEAK_FCLK value should not be used to set the DPM. Suggested-by: Evan Quan <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Sudheesh Mavila <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-22drm/amd/powerplay: optimize the mclk dpm policy settingsEvan Quan1-3/+13
Different mclk dpm policy will be applied based on the VRAM width. Signed-off-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-22drm/amd/pm: simplify the return expression of smu_hw_finiLiu Shixin1-6/+1
Simplify the return expression. Signed-off-by: Liu Shixin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-18drm/amd/pm: Skip smu_post_init in SRIOVJingwen Chen1-0/+3
smu_post_init needs to enable SMU feature, while this require virtualization off. Skip it since this feature is not used in SRIOV. v2: move the check to the early stage of smu_post_init. v3: fix typo Signed-off-by: Jingwen Chen <[email protected]> Reviewed-by: Emily.Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-18drm/amd/pm: apply dummy reads workaround for CDR enabled onlyEvan Quan1-3/+5
For CDR disabled case, the dummy reads workaround is not needed. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-17drm/amdgpu/powerplay: hwmgr - modify the return valueXiaoliang Pang2-2/+2
Return value should be -EINVAL rather than EINVAL Fixes: f83a9991648bb("drm/amd/powerplay: add Vega10 powerplay support (v5)") Fixes: 2cac05dee6e30("drm/amd/powerplay: add the hw manager for vega12 (v4)") Cc: Eric Huang <[email protected]> Cc: Evan Quan <[email protected]> Reviewed-by: Evan Quan <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Xiaoliang Pang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-17drm/amd/pm: correct Renoir UMD Stable Pstate settingsEvan Quan2-1/+52
Update the UMD stable Pstate settings with correct clocks. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-17drm/amd/pm: lower Raven UMD Stable Pstate VCN valuesEvan Quan2-2/+3
SMU FCLK,SOCCLK have dependency on VCN CLKs. Lower VCN values so that FCLK, SOCCLK reflect values set by UMD Stable Pstate. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-17drm/amd/pm: move NAVI1X power mode switching workaround to post_initEvan Quan2-15/+19
Since that should be the correct place to put ASIC specific workarounds. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-17drm/amd/pm: apply no power source workaround if dc reported by gpioEvan Quan1-10/+12
If dc reported by gpio is supported, the power source switching will be performed by pmfw automatically. Thus the power source setting workaround for Navi1x will be not needed. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-17drm/amd/pm: process pending AC/DC switch interruptEvan Quan1-10/+30
Process any pending interrupt that occured before driver register for interrupt from GPIO/SMU. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-17drm/amd/pm: add Raven2 watermark WmType settingEvan Quan2-1/+13
Which tells it's a normal pstate change or memory retraining. Signed-off-by: Evan Quan <[email protected]> Tested-by: Changfeng Zhu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-17drm/amd/pm: add Renoir watermark WmType settingEvan Quan1-0/+4
Which tells it's a normal pstate change or memory retraining. Signed-off-by: Evan Quan <[email protected]> Tested-by: Changfeng Zhu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-17drm/amd/pm: drop unnecessary wrappers around watermark settingEvan Quan5-111/+76
The convertion to "struct dm_pp_clock_range_for_mcif_wm_set_soc15" is totally unnecessary and can be dropped. Signed-off-by: Evan Quan <[email protected]> Tested-by: Changfeng Zhu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-17drm/amd/pm: minor cleanupsEvan Quan1-17/+5
Drop unneeded "ret". Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-17drm/amd/pm: drop unnecessary table existence and dpm enablement checkEvan Quan4-32/+5
Either this was already performed in parent API. Or the table is confirmed to exist. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-17drm/amd/pm: drop unnecessary smu_baco->mutex lock protections(V2)Evan Quan4-12/+1
As these operations are performed in hardware setup and there is actually no race conditions during this period considering: 1. the hardware setup is serial and cannot be in parallel 2. all other operations can be performed only after hardware setup complete. V2: rich the commit log description Signed-off-by: Evan Quan <[email protected]> Acked-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-17drm/amd/pm: drop unnecessary feature->mutex lock protections(V2)Evan Quan2-6/+0
As these operations are performed in hardware setup and there is actually no race conditions during this period considering: 1. the hardware setup is serial and cannot be in parallel 2. all other operations can be performed only after hardware setup complete. V2: rich the commit log description Signed-off-by: Evan Quan <[email protected]> Acked-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-17drm/amd/pm: make namings and comments more readableEvan Quan1-4/+4
And to fit more accurately what the cod does. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-17drm/amd/pm: correct the requirement for umc cdr workaroundEvan Quan1-10/+9
The workaround can be applied only with UCLK DPM enabled. And expand the workaround to more Navi10 SKUs and also Navi14. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-17drm/amd/pm: apply the CDR workarounds only with some specific UMC firmwares(V2)Evan Quan3-9/+49
And different workaround will be applied based on hybrid cdr bit. V2: add pmfw version guard to make sure the new workaround applied only with pmfw >= 42.53.0 Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-17drm/amd/pm: implement a new umc cdr workaroundEvan Quan4-1/+234
By uploading dummy pstate tables. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-17drm/amd/pm: allocate a new buffer for pstate dummy readingEvan Quan2-0/+46
This dummy reading buffer will be used for the new Navi1x UMC CDR workaround. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-17drm/amd/pm: revise the umc hybrid cdr workaroundEvan Quan1-27/+34
Drop the unused message(SMU_MSG_DAL_DISABLE_DUMMY_PSTATE_CHANGE). And do not apply this workaround when the max uclk frequency is greater than 750Mhz. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-17drm/amd/pm: put Navi1X umc cdr workaround in post_smu_initEvan Quan4-12/+14
That's where the uclk dpm get enabled and then the uclk cdr workaround can be applied. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-17drm/amd/pm: postpone SOCCLK/UCLK enablement after DAL initialization(V2)Evan Quan3-24/+46
This is needed for Navi1X only. And it may help for display missing or hang issue seen on some high resolution monitors. V2: no UCLK DPM enablement for Navi10 A0 secure SKU Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-17drm/amd/pm: wrapper for postponing some setup job after DAL initializatioa(V2)Evan Quan3-0/+8
So that ASIC specific actions can be added. V2: better namings Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/pm: support runtime pptable update for sienna_cichlid etc.Jiansong Chen1-3/+9
This avoids smu issue when enabling runtime pptable update for sienna_cichlid and so on. Runtime pptable udpate is needed for test and debug purpose. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-15drm/amd/pm: update driver if version for navy_flounderJiansong Chen1-1/+1
It's in accordance with pmfw 65.8.0 for navy_flounder. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.