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path: root/drivers/gpu/drm/amd/pm/amdgpu_pm.c
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2020-11-05drm/amdgpu: add missing clock gating info in amdgpu_pm_infoKevin Wang1-0/+5
add missing clock gating informations in amdgpu_pm_info 1. AMD_CG_SUPPORT_VCN_MGCG 2. AMD_CG_SUPPORT_HDP_DS 3. AMD_CG_SUPPORT_HDP_SD 4. AMD_CG_SUPPORT_IH_CG 5. AMD_CG_SUPPORT_JPEG_MGCG Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-11-04drm/amdgpu: cleanup debug log in amdgpu_set_pp_features()Kevin Wang1-2/+0
Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-11-04drm/amdgpu: Add GFX Fine Grain Clock Gating flagJinzhou.Su1-0/+1
Add AMD_CG_SUPPORT_GFX_FGCG for FGCG Signed-off-by: Jinzhou.Su <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-30drm/amd/pm: set the initial value of pm info to zeroXiaojian Du1-1/+1
This patch is to set the initial value of pm info to zero. The "value64" is ported to the hwmon and debugfs node, it is a uint64 type. When it is used for NV10/VEGA10/VEGA20, its word size is appropriate, because NV10/VEGA10/VEGA20 has a 64bit smu feature mask, which is separated to high 32bit and low 32bit. But some asic has only 32bit smu feature mask,and this 32bit mask will fill the low 32bit of "value64". So if this "value64" is not initialized to zero, the high 32bit will be filled by a meaningless value, when the whole "value64" is ported to the "SMC Feature Mask" in the "amdgpu_pm_info" on some specific asic, it will be a wrong value. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-15drm/amd/pm: populate Arcturus PCIE link stateEvan Quan1-3/+0
Populate current link speed, width and clock domain frequency. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-09drm/amdgpu/swsmu: clean up a bunch of stale interfacesAlex Deucher1-4/+4
These were leftover from the initial implementation, but never used. Drop them. Reviewed-by: Evan Quan <[email protected]> Noticed-by: Ryan Taylor <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-09-29drm/amd/powerplay: add one sysfs file to support the feature to modify gfx ↵Xiaojian Du1-0/+12
clock on Raven/Raven2/Picasso APU. This patch is to add one sysfs file -- "pp_od_clk_voltage" for Raven/Raven2/Picasso APU, which is only used by dGPU like VEGA10. This sysfs file supports the feature to modify gfx engine clock(Mhz units), it can be used to configure the min value and the max value for gfx clock limited in the safe range. Command guide: echo "s level clock" > pp_od_clk_voltage s - adjust teh sclk level level - 0 or 1, "0" represents the min value, "1" represents the max value clock - the clock value(Mhz units), like 400, 800 or 1200, the value must be within the OD_RANGE limits. Example: $ cat pp_od_clk_voltage OD_SCLK: 0: 200Mhz 1: 1400Mhz OD_RANGE: SCLK: 200MHz 1400MHz $ echo "s 0 600" > pp_od_clk_voltage $ echo "s 1 1000" > pp_od_clk_voltage $ cat pp_od_clk_voltage OD_SCLK: 0: 600Mhz 1: 1000Mhz OD_RANGE: SCLK: 200MHz 1400MHz Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-24drm/amdgpu: Get DRM dev from adev by inline-fLuben Tuikov1-97/+97
Add a static inline adev_to_drm() to obtain the DRM device pointer from an amdgpu_device pointer. Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-24drm/amdgpu: drm_device to amdgpu_device by inline-f (v2)Luben Tuikov1-40/+40
Get the amdgpu_device from the DRM device by use of an inline function, drm_to_adev(). The inline function resolves a pointer to struct drm_device to a pointer to struct amdgpu_device. v2: Use a typed visible static inline function instead of an invisible macro. Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-24drm/amdgpu: refine codes to avoid reentering GPU recoveryDennis Li1-58/+58
if other threads have holden the reset lock, recovery will fail to try_lock. Therefore we introduce atomic hive->in_reset and adev->in_gpu_reset, to avoid reentering GPU recovery. v2: drop "? true : false" in the definition of amdgpu_in_reset Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Dennis Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-18drm/amdgpu/pm: only hide average power on SI and pre-RENOIR APUsAlex Deucher1-2/+7
We can get this on RENOIR and newer via the SMU metrics table. Reviewed-by: Evan Quan <[email protected]> Acked-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-18drm/amdgpu/pm: remove duplicate checkAlex Deucher1-2/+1
FAMILY_KV is APUs and we already check for APUs. Reviewed-by: Evan Quan <[email protected]> Acked-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-08-14drm/amd/pm: optimize the power related source code layoutEvan Quan1-0/+3613
The target is to provide a clear entry point(for power routines). Also this can help to maintain a clear view about the frameworks used on different ASICs. Hopefully all these can make power part more friendly to play with. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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