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path: root/drivers/gpu/drm/amd/include
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2019-08-27drm/amd: Import smuio_11_0 headers for EEPROM access on Vega20Andrey Grodzovsky2-0/+323
v3: Merge CKSVII2C_IC regs into exsisting headers. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-08-23drm/amdgpu/display: add flag for multi-display mclk switchingAlex Deucher1-0/+1
Add a dcfeaturemask flag for mclk switching. Disable by default; enable once the feature has seen more testing. Set amdgpu.dcfeaturemask=2 on the kernel command line in grub to enable this. Acked-by: Evan Quan <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-08-21drm/amdgpu: Fix a typo in the include header guard of 'navi12_ip_offset.h'Christophe JAILLET1-2/+2
'_navi10_ip_offset_HEADER' is already used in 'navi10_ip_offset.h', so use '_navi12_ip_offset_HEADER' instead here. Reviewed-by: Xiaojie Yuan <[email protected]> Signed-off-by: Christophe JAILLET <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-08-15drm/amd/poweplay: Add amd_pm_funcs callback for mode 2Andrey Grodzovsky1-0/+1
Add callback to call the new mode2 reset interface. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-08-15drm/amdgpu: implement querying ras error count for mmhubTao Zhou2-0/+243
get mmhub ea ras error count by accessing EDC_CNT register Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-08-12drm/amdgpu: add renoir header files (v2)Huang Rui2-0/+1202
This patch add all renoir header files. v2: clean up headers (Alex) Acked-by: Huang Rui <[email protected]> Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-08-02drm/amdgpu: add CGTT_GS_NGG_CLK_CTRL register to gc headerXiaojie Yuan2-0/+41
gc 10.1.2 introduced this new register Signed-off-by: Xiaojie Yuan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-08-02drm/amdgpu: add ip offset header for navi12 (v2)Xiaojie Yuan1-0/+1119
This adds the absolute offsets of each IP regiser block. v2: Squash in MP1 update Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-08-02drm/amdkfd: Extend CU mask to 8 SEs (v3)Jay Cornwall1-4/+4
Following bitmap layout logic introduced by: "drm/amdgpu: support get_cu_info for Arcturus". v2: squash in fixup for gfx_v9_0.c (Alex) v3: squash in debug print output fix Signed-off-by: Jay Cornwall <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-08-02drm/amdgpu: Update NBIO headers to add TXCLK3/4Kent Russell2-0/+36
These are added for VG20, and are needed for PCIe bandwidth. Signed-off-by: Kent Russell <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-31drm/amd/include: add define of TCP_EDC_CNT_NEWDennis Li1-0/+2
Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-31drm/amd/include: add bitfield define for EDC registersDennis Li1-0/+157
Add EDC registers to support VEGA20 RAS Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-31drm/amdgpu: add umc v6_1_1 IP headersHawking Zhang2-0/+122
the change introduces IP headers for unified memory controller (umc) Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Dennis Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-31drm/amdgpu: add rsmu v_0_0_2 ip headersHawking Zhang2-0/+59
remote smu (rsmu) is a sub-block used as ip register interface, error handling, reset generation.etc Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Dennis Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amd/powerplay: add new sensor type for VCN powergate statusEvan Quan1-0/+1
VCN is widely used in new ASICs and different from tranditional UVD and VCE. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amd/include: adjust base offset of SMUIO and THM for ArcturusLe Ma1-6/+2
Arcturus has different _BASE_IDX value in some HWIP_offset.h. To make source files like smu_v11_0.c and soc15.c that include HWIP_offset.h of Vega20 reusable for Arcturus, align this base offset with Vega20. Signed-off-by: Le Ma <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amd/powerplay: add smcdpminfo table v4_6 supportEvan Quan1-0/+86
New smcdpminfo table used in arcturus. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu/powerplay: add a new interface to set the mp1 stateAlex Deucher1-0/+8
This is required for certain cases such as various GPU resets (mode1, mode2), BACO, shutdown, unload, etc. to put the SMU into the appropriate state for when the hw is re-initialized. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-18drm/amdgpu: exposing fica registers to df offsetsJonathan Kim1-0/+4
exposing fica registers to poll df pie data for xgmi error counters for vega20. Signed-off-by: Jonathan Kim <[email protected]> Reviewed-by: Alexander Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-18drm/amd/powerplay: correct SW SMU valid mapping checkEvan Quan1-0/+1
Current implementation is not actually able to detect invalid message/table/workload mapping. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-18drm/amdgpu/: add clientID for 2nd vcn instanceJames Zhu1-1/+1
add clientID for 2nd vcn instance, remove unused SOC15_IH_CLIENTID_SYSHUB. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-18drm/amdgpu: add VMC1 interrupt client id for ArcturusLe Ma1-0/+1
New IH client id for VMC1. Signed-off-by: Le Ma <[email protected]> Acked-by: Snow Zhang < [email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-18drm/amdgpu: add SDMA 2~7 interrupt client id for ArcturusLe Ma1-1/+7
Add new client ids. Signed-off-by: Le Ma <[email protected]> Acked-by: Snow Zhang < [email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-18drm/amdgpu: add Arcturus ip_offset header (v3)Le Ma1-0/+1654
Provides the absolute offsets of the IP register blocks. v2: update chip name in source code v3: squash in MP offset updates (Alex) Signed-off-by: Le Ma <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-18drm/amdgpu: add VCN2.5 headersLeo Liu2-0/+4588
VCN is the multi-media block. Signed-off-by: Leo Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-18drm/amdgpu: add sdma 4.2.2 header files for ArcturusLe Ma16-0/+32046
SDMA is the system DMA block. Signed-off-by: Le Ma <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-18drm/amdgpu: add mmhub 9.4.1 header files for AcrturusLe Ma3-0/+56570
mmhub is the GPU memory hub used by SDMA and VCN. Signed-off-by: Le Ma <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-18drm/amdgpu/soc15: initialize reg base for navi14 (v2)Xiaojie Yuan1-0/+1119
Initialize the IP register base offsets for navi14. v2: squash in MP, CLK, THM updates Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-11drm/amd/powerplay: increase the SMU msg response waiting timeEvan Quan1-1/+1
This is expected to fix some mode1 reset failures. And this affects SMU part only as the timeout setting for other parts is controlled by a different macro. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-25drm/amd/powerplay: make athub pg bit configured by pg_flagsHuang Rui1-1/+2
The athub pg features enabling should be indicated by pg_flags. Reported-by: Lijo Lazar <[email protected]> Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display: Create DWB resource for DCN2Charlene Liu2-0/+20
[Description] dcn20 has num_dwb =1 in the res cap, but not created. Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Duke Du <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/mes10.1: add ip block mes10.1 (v2)Jack Xiao1-1/+2
MES takes over the scheduling capability of GFX and SDMA, add MES as a standalone ip. v2: squash in updates (Alex) Acked-by: Hawking Zhang <[email protected]> Signed-off-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/discovery: update definition for struct die_headerXiaojie Yuan1-2/+2
Update to latest spec. Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/discovery: add harvest info data tableXiaojie Yuan1-1/+17
Add support for the harvest tables. Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/discovery: update definitions of table_info and binary_headerXiaojie Yuan1-0/+4
Use the proper definitions. Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/discovery: add ip discovery initial supportXiaojie Yuan1-0/+145
The IP discovery table lists is populated by the psp at power on and includes all of the hw details on the board: - List of IPs and MMIO offsets - IP harvest details - IP configuration details v2: prefix struct and function names with 'amdgpu' v3: read table binary from vram using mmMM_INDEX and mmMM_DATA update TABLE_BINARY_MAX_SIZE to 64kb (1 TMR) add 'instance_number' field per ip info consider endianness and replace uint8/16/32_t with u8/16/32 initialize register base addresses initialize adev->gfx.config and adev->gfx.cu_info to replace gpu info fw get major and minor version using a single api don't expose internal data structures in amdgpu_discovery.h v4: RCC_CONFIG_MEMSIZE is in MB units hold mmio_idx_lock while reading ip discovery binary v5: pick out discovery.h as a cross-OS header do structure pointer cast directly consider endianness while using the member of structure convert base addresses to dword at boot up, PSP BL copies ip discovery binary from VBIOS(SPIROM) image to the top of the frame buffer (just below the reserved regions for PSP & SMU). ip discovery data table includes the collection of each ip's identification number, base addresses, version number, and harvest setting placeholder. gc data table includes gfx info structure. Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amd/display: move dcn v1_0 irq source header to ivsrcid/dcn/Hawking Zhang1-0/+0
interrupt source packet definitions for the display block (DCN). Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add irq sources for vcn v2_0 (v2)Hawking Zhang1-0/+32
Add the interrupt source packet definitions. v2: update (Alex) Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add irq sources for sdma v5_0Hawking Zhang2-0/+87
Add the interrupt source packet definitions. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add irq sources for gfx v10_1Hawking Zhang1-0/+53
Add the interrupt source packet definitions. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu/athub2: enable athub2 clock gatingJack Xiao1-0/+2
Enable athub2 clock gating and light sleep Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add flag to support IH clock gatingHawking Zhang1-0/+1
Add new flag for IH (interrupt handler) clockgating. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add new HDP CG flagsHawking Zhang1-0/+2
HDP 5.0 supports SRAM power gating. all the LS (Light Sleep)/ DS (Deep Sleep)/SD (Shut Down) modes are supported. However, only one of these modes can be enabled at one time. There is no dynamic power mode switch support. clock/power gating has to be disabled before making any power mode change. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add v10 structs header (v2)Huang Rui1-0/+1258
Header for CP structures (MQD, etc.) V2: squash in updates Signed-off-by: Huang Rui <[email protected]> Acked-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add navi10 ip offset headerHawking Zhang2-1/+858
Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: atomfirmware.h updates for navi10Hawking Zhang1-8/+180
Updated tables for Navi10. Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add navi10 enums headerHawking Zhang1-0/+22764
Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add SMUIO 11.0 register headersHawking Zhang2-0/+1012
Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add OSS 5.0 register headersHawking Zhang2-0/+1658
Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add MMHUB 2.0 register headersHawking Zhang3-0/+10293
Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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