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2020-02-28drm/amdkfd: Make get_tile_config() genericYong Zhao1-4/+0
Given we can query all the asic specific information from amdgpu_gfx_config, we can make get_tile_config() generic. Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-02-26drm/amdkfd: Avoid ambiguity by indicating it's cp queueYong Zhao1-1/+1
The queues represented in queue_bitmap are only CP queues. Signed-off-by: Yong Zhao <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-02-26drm/amd: Extend ROCt to surface UUID for devices that have themDivya Shikre1-0/+4
Devices from Arcturus onwards will have their UUID exposed to Thunk. Adding neccessary functions to the kernel to propagate the uuid. Signed-off-by: Divya Shikre <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-02-25amdgpu/gmc_v9: save/restore sdpif regs during S3Shirish S1-0/+2
fixes S3 issue with IOMMU + S/G enabled @ 64M VRAM. Suggested-by: Alex Deucher <[email protected]> Signed-off-by: Shirish S <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-30drm/amdgpu: Enable DISABLE_BARRIER_WAITCNT for ArcturusJoseph Greathouse1-2/+4
In previous gfx9 parts, S_BARRIER shader instructions are implicitly S_WAITCNT 0 instructions as well. This setting turns off that mechanism in Arcturus and beyond. With this, shaders must follow the ISA guide insofar as putting in explicit S_WAITCNT operations even after an S_BARRIER. v2: Fix patch title to list component Signed-off-by: Joseph Greathouse <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amdgpu: add EDC counter registers of gc for ArcturusDennis Li2-0/+1012
add reg headers to gc includes v2: remove unused registers and fields in this patch set Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amdgpu: update mmhub 9.4.1 header files for AcrturusDennis Li1-0/+128
Add mask & shift definition of MAM_D(0~3)MEM for all mmhub ranges. Signed-off-by: Dennis Li <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-22drm/amdgpu: added support to get mGPU DRAM baseJohn Clements2-0/+11
resolves issue with RAS error injection in mGPU configuration Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-16drm/amd/include: Add OCSC registersRodrigo Siqueira4-2/+24
Add registers for handling Post Gamma Color Blending (OCSC), which is useful for conversion from RGB->YUV for HDMI. Reviewed-by: Leo Li <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-16drm/amdkfd: use kiq to load the mqd of hiq queue for gfx v9 (v6)Aaron Liu1-0/+4
There is an issue that CP will check the HIQ queue to be configured and mapped with KIQ ring, otherwise, it will be unable to read back the secure buffer while the gfxoff is enabled even with trusted IP blocks. v1 -> v2: - Fix to remove surplus set_resources packets. - Fill the whole configuration in MQD. - Change the author as Aaron because he addressed the key point of this issue. - Add kiq ring lock. v2 -> v3: - Free the lock while in error return case. - Remove the programming only needed by the queue is unmapped. v3 -> v4: - Remove doorbell programming because it's used for restarting queue. - Remove CP scheduler programming because map_queue packet will handle this. v4 -> v5: - Remove cp_hqd_active because mec ucode will enable it while use map_queues. - Revise goto out_unlock. - Correct the right doorbell offset for HIQ that kfd driver assigned in the packet. v5 -> v6: - Merge Arcturus fix into this patch because it will get oops in Arcturus platform. Reported-by: Lisa Saturday <[email protected]> Signed-off-by: Aaron Liu <[email protected]> Signed-off-by: Huang Rui <[email protected]> Reviewed-and-Tested-by: Aaron Liu <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-16drm/amdgpu: flush TLB functions removal from kfd2kgd interfaceAlex Sierra1-2/+0
[Why] kfd2kgd interface will be deprecated. This removal only covers TLB invalidation for now. They have been replaced in amdgpu_amdkfd API. [How] TLB invalidate functions removed from the different amdkfd_gfx_v* versions. Signed-off-by: Alex Sierra <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-14drm/amdgpu: add defines for DF and TCP HashingJoseph Greathouse3-0/+17
On Arcturus, we need TC channel hashing, which is set by the driver, to match DF hashing, which is set by VBIOS. To match these, we plan to query the DF information and then properly set the TC configuration bits to match them. This patch adds the required fields to register definitions in preparation for a future patch which will use them. Signed-off-by: Joseph Greathouse <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-14drm/amd/amdgpu: add missing umc_6_1_2_sh_mask.h header file (v2)Tom St Denis1-0/+91
(v2): Fix preprocessor tag Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-01-14drm/amdgpu: add MCUMC_ADDRT0 offset to ip header fileGuchun Chen2-0/+4
Both are needed on vega20 and arcturus chip. Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-23drm/amdgpu: update the method to get fb_loc of memory training(V4)Tianci.Yin1-14/+0
The method of getting fb_loc changed from parsing VBIOS to taking certain offset from top of VRAM Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-23drm/amdgpu: Add mmCOMPUTE_STATIC_THREAD_MGMT_SE4-7 to support ArcturusJames Zhu1-0/+8
Arcturus has 8 SEs. Add mmCOMPUTE_STATIC_THREAD_MGMT_SE4-7 for EDC GPR _workarounds, Signed-off-by: James Zhu <[email protected]> Reviewed-by: Yong Zhao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-23drm/amdgpu: add perfmons accessible during df c-statesJonathan Kim1-0/+16
During DF C-State, Perfmon counters outside of range 1D700-1D7FF will encounter SLVERR affecting xGMI performance monitoring. PerfmonCtr[7:4] is being added to avoid SLVERR during read since it falls within this range. PerfmonCtl[7:4] is being added in order to arm PerfmonCtr[7:4]. Since PerfmonCtl[7:4] exists outside of range 1D700-1D7FF, DF routines will be enabled to opportunistically re-arm PerfmonCtl[7:4] on retry after SLVERR. Signed-off-by: Jonathan Kim <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-18drm/amdgpu: move umc offset to one new header file for ArcturusGuchun Chen1-0/+31
Code refactor and no functional change. Fixes: 4cf781c24c3b ("drm/amdgpu: Added RAS UMC error query support for Arcturus") Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-18drm/amdgpu: add dpcs20 registersRoman Li2-0/+4559
add reg headers to dpcs includes Signed-off-by: Roman Li <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-18drm/amdgpu: move dpcs headers to dpcs includesRoman Li2-0/+0
- create dpcs directory for dpcs asic_reg headers - move dpcs21 reg headers from dcn to dpcs directory Signed-off-by: Roman Li <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-22drm/amdgpu: refine query function of mmhub EDC counter in vg20Dennis Li4-310/+138
Add codes to print the detail EDC info for the subblock of mmhub v2: Move the EDC_CNT registers' defintion from mmhub_9_4 header files to mmhub_1_0 ones. Add mmhub_v1_0_ prefix for the local static variable and function. v3: squash in DC fix Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-19drm/amdgpu: add JPEG PG and CG interfaceLeo Liu1-0/+2
From JPEG2.0, it will use its own PG/CG Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-19drm/amdgpu: add JPEG IP block typeLeo Liu1-1/+2
From VCN2.0, JPEG2.0 is a separated IP block. Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-06drm/amd/powerplay: support xgmi pstate setting on powerplay routine V2Evan Quan1-0/+4
Add xgmi pstate setting on powerplay routine. V2: split the change of is_support_sw_smu_xgmi into a separate patch Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu: Add DC feature mask to disable fractional pwmLeo Li1-0/+1
[Why] Some LED panel drivers might not like fractional PWM. In such cases, backlight flickering may be observed. [How] Add a DC feature mask to disable fractional PWM, and associate it with the preexisting dc_config flag. The flag is only plumbed through the dmcu firmware, so plumb it through the driver path as well. To disable, add the following to the linux cmdline: amdgpu.dcfeaturemask=0x4 Bugzilla: https://bugzilla.kernel.org/show_bug.cgi?id=204957 Signed-off-by: Leo Li <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Tested-by: Lukáš Krejčí <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu/display: add dc feature mask for psr enablementRoman Li1-0/+1
[Why] Adding psr mask to dc features allows selectively disable/enable psr. Current psr implementation may not work with non-pageflipping application. Until resolved it should be disabled by default. [How] Add dcfeaturemask for psr enablement. Disable by default. To enable set amdgpu.dcfeaturemask=0x8 in grub kernel command line. Signed-off-by: Roman Li <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-25drm/amdgpu: add VCN0 and VCN1 needed headersJane Jian1-0/+12
Add mmsch part registers Signed-off-by: Jane Jian <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amdgpu: update atomfirmware header with memory training related members(v3)Tianci.Yin1-6/+21
add new vram_reserve_block structure and atomfirmware_internal_constants enumeration Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Luben Tuikov <[email protected]> Signed-off-by: Tianci.Yin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: Add DCN_BASE regsBhawanpreet Lakha1-0/+34
Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-17drm/amd/display: Add DP_DPHY_INTERNAL_CTR regsBhawanpreet Lakha1-0/+10
Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-15drm/amdgpu: add new SMU 7.1.3 registers for BACOAlex Deucher2-0/+3
Reviewed-by: Evan Quan <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-15drm/amdgpu: add new SMU 7.1.2 registers for BACOAlex Deucher2-0/+3
Reviewed-by: Evan Quan <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-15drm/amdgpu: add new SMU 7.0.1 registers for BACOAlex Deucher2-0/+3
Reviewed-by: Evan Quan <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-15drm/amdgpu: add new BIF 5.0 register for BACOAlex Deucher2-0/+3
Reviewed-by: Evan Quan <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-15drm/amdgpu: add new BIF 4.1 register for BACOAlex Deucher2-0/+3
Reviewed-by: Evan Quan <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-15drm/amd/include: add register define for VML2 and ATCL2Dennis Li2-4/+32
Add VML2 and ATCL2 ECC registers to support VEGA20 RAS Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-15drm/amdgpu/discovery: reserve discovery data at the top of VRAMXiaojie Yuan1-1/+0
IP Discovery data is TMR fenced by the latest PSP BL, so we need to reserve this region. Tested on navi10/12/14 with VBIOS integrated with latest PSP BL. v2: use DISCOVERY_TMR_SIZE macro as bo size use amdgpu_bo_create_kernel_at() to allocate bo Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-15drm/amd/powerplay: enable df cstate control on powerplay routineEvan Quan1-0/+6
Currently this is only supported on Vega20 with 40.50 and later SMC firmware. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amd/amdgpu: add IH cg support on soc15 projectKenneth Feng1-0/+4
enable/disable IH clock gating on soc15 projects. Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdkfd: Eliminate get_atc_vmid_pasid_mapping_validYong Zhao1-5/+3
get_atc_vmid_pasid_mapping_valid() is very similar to get_atc_vmid_pasid_mapping_pasid(), so they can be merged into a new function get_atc_vmid_pasid_mapping_info() to reduce register access times. More importantly, getting the PASID and the valid bit atomically with a single read fixes some potential race conditions where the mapping changes between the two reads. Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdgpu: Add SMUIO values for other I2C controller v2Kent Russell2-0/+268
These are the offsets for CKSVII2C1, and match up with the values already added for CKSVII2C v2: Don't remove some of the CSKVII2C values Signed-off-by: Kent Russell <[email protected]> Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-10-03drm/amdkfd: Fix NULL pointer dereference for set_scratch_backing_va()Yong Zhao1-0/+5
Currently this function pointer is missing for GFX10. Considering it is a void function since GFX9, fix it by checking the function pointer before dereferencing it. Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-09-16drm/amdgpu: add pcie bif ras related registersGuchun Chen2-0/+55
These registers will be accessed for querying ras errors. Signed-off-by: Tao Zhou <[email protected]> Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-09-13drm/amd/display: update renoir_ip_offset.hAaron Liu1-1/+1
This patch updates MP1_BASE in renoir_ip_offset.h Signed-off-by: Aaron Liu <[email protected]> Acked-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-09-13drm/amdgpu: Support new arcturus mtypeOak Zeng1-0/+1
Arcturus repurposed mtype WC to RW. Modify gmc functions to support the new mtype Signed-off-by: Oak Zeng <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Shaoyun Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-09-13drm/amdgpu: update nbio v7_4 ip header filesHawking Zhang2-5/+5
Add mmBIF_INTR_CNTL and its shift mask. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-09-13drm/amdgpu: add nbif v7_4 irq source header for vega20Hawking Zhang1-0/+42
nbif v7_4 interrupt source definition Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-08-30drm/amdgpu: update IH_CHICKEN in oss 4.0 IP header for VG/RV seriesAaron Liu1-0/+4
In Renoir's emulator, those chicken bits need to be programmed. Signed-off-by: Aaron Liu <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-08-29drm/amd/display: Add Renoir registers (v3)Bhawanpreet Lakha7-0/+75988
add registers for dcn, clk, and renoir ip offsets v2: header cleanup (Alex) v3: Add DPCS registers (Hersen) Acked-by: Harry Wentland <[email protected]> Signed-off-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-08-27drm/amd/powerplay: Add interface to lock SMU HW I2C.Andrey Grodzovsky1-0/+1
v2: PPSMC_MSG_RequestI2CBus seems not to work and so to avoid conflict over I2C bus and engine disable thermal control access to force SMU stop using the I2C bus until the issue is reslolved. Expose and call vega20_is_smc_ram_running to skip locking when SMU FW is not yet loaded. v3: Remove the prevoius hack as the SMU found the bug. v5: Typo fix Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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