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Add support for MACO flag checking.
MACO mode only works if BACO is supported.
Signed-off-by: Ma Jun <[email protected]>
Reviewed-by: Lijo Lazar <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Rodrigo Siqueira <[email protected]>
Acked-by: Roman Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Signed-off-by: Rodrigo Siqueira <[email protected]>
Acked-by: Roman Li <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Align with FW changes.
Signed-off-by: Lang Yu <[email protected]>
Reviewed-by: Veerabadhran Gopalakrishnan <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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v1: Add smuio v14_0_2 register offset and shift masks
header files. (Hawking)
v2: Update smuio v14_0_2 register offset and shift masks
header files to RE2. (Likun)
v3: Update smuio v14_0_2 register offset and shift masks
header files to RE2.5. (Likun)
v4: Clean up smuio v14_0_2 ip headers (Alex)
Signed-off-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Signed-off-by: Likun Gao <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Reviewed-by: Likun Gao <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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[Why & How]
Registers and offset are missing. Add it back
Acked-by: Wayne Lin <[email protected]>
Signed-off-by: Rodrigo Siqueira <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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This will add the sensor value of VCN activity for some ASICs.
Signed-off-by: Xiaojian Du <[email protected]>
Reviewed-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Add UCE and FED bit definitions.
Signed-off-by: Tao Zhou <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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v1: Add pcie v6_1_0 register offset and shift masks
header files. (Hawking)
v2: Update pcie v6_1_0 register offset and shift masks
header files to RE2. (Likun)
v3: Update pcie v6_1_0 register offset and shift masks
header files to RE2.5. (Likun)
v4: Update pcie v6_1_0 register offset and shift masks
header files to RE3. (Likun)
v5: Updates (Alex)
Signed-off-by: Hawking Zhang <[email protected]>
Signed-off-by: Likun Gao <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Reviewed-by: Likun Gao <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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v1: Add nbif v6_3_1 register offset and shift masks
header files. (Hawking)
v2: Update nbif v6_3_1 register offset and shift masks
header files to RE2. (Likun)
v3: Update nbif v6_3_1 register offset and shift masks
header files to RE2.5. (Likun)
v4: Update nbif v6_3_1 register offset and shift masks
header files to RE3. (Likun)
v5: Updates (Alex)
Signed-off-by: Hawking Zhang <[email protected]>
Signed-off-by: Likun Gao <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Reviewed-by: Likun Gao <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Add register headers for DCN 3.5.1.
Signed-off-by: Hamza Mahfooz <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Add new firmware header definitions reqiured for DCN401
Signed-off-by: Aurabindo Pillai <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Remove implementation to get pcie usage for nbio v7.9
as pcie usage is handled by fw
This reverts commit 59070fd9ccea58c3363d39f69c25fa98c71eb02f.
Signed-off-by: Asad Kamal <[email protected]>
Reviewed-by: Lijo Lazar <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Fix up doorbell setup and clockgating.
v2: squash in fixes (Alex)
Signed-off-by: Yifan Zhang <[email protected]>
Signed-off-by: Lang Yu <[email protected]>
Signed-off-by: Veerabadhran Gopalakrishnan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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v1: Add mp v14_0_2 register offset and shift masks
header files. (Hawking)
v2: Update mp v14_0_2 register offset and shift masks
header files to RE2. (Likun)
v3: Update mp v14_0_2 register offset and shift masks
header files to RE2.5. (Likun)
v4: Update mp v14_0_2 register offset and shift masks
header files to RE3. (Likun)
v5: Updates (Alex)
Signed-off-by: Hawking Zhang <[email protected]>
Signed-off-by: Likun Gao <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Reviewed-by: Likun Gao <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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v1: Add vcn v5_0_0 register offset and shift masks
header files. (Hawking)
v2: Update vcn v5_0_0 register offset and shift masks
header files to RE2. (Likun)
v3: Update vcn v5_0_0 register offset and shift masks
header files to RE2.5. (Likun)
v4: Update vcn v5_0_0 register offset and shift masks
header files to RE3. (Likun)
v5: Clean up vcn v5_0_0 ip headers. (Alex)
Signed-off-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
Signed-off-by: Likun Gao <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Reviewed-by: Likun Gao <[email protected]
Signed-off-by: Alex Deucher <[email protected]>
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v1: Add hdp v7_0_0 register offset and shift masks
header files (Hawking)
v2: Update hdp v7_0_0 register offset and shift masks
header files for RE2.5 (Likun)
v3: Clean up hdp v7_0_0 ip headers (Alex)
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Likun Gao <[email protected]>
Signed-off-by: Likun Gao <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Jpeg DPG support for GC IP v11_5_0
Signed-off-by: Saleemkhan Jamadar <[email protected]>
Reviewed-by: Leo Liu <[email protected]>
Reviewed-by: Veerabadhran Gopalakrishnan <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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v1: Add osssys v7_0_0 register offset and shift masks
header files. (Hawking)
v2: Update osssys v7_0_0 register offset and shift masks
header files to RE2. (Likun)
v3: Update osssys v7_0_0 register offset and shift masks
header files to RE2.5. (Likun)
v4: Clean up osssys v7_0_0 ip headers (Alex)
Signed-off-by: Hawking Zhang <[email protected]>
Signed-off-by: Likun Gao <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Reviewed-by: Likun Gao <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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v1: Add lsdma v7_0_0 register offset and shift masks
header files (Hawking)
v2: Update lsdma v7_0_0 register offset and shift masks
header files for RE2.5 (Likun)
v3: Clean up lsdma v7_0_0 ip headers (Alex)
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Likun Gao <[email protected]>
Signed-off-by: Likun Gao <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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v1: Add athub v4_1_0 register offset and shift masks
header files. (Hawking)
v2: Update athub v4_1_0 register offset and shift masks
header files to RE2. (Likun)
v3: Update athub v4_1_0 register offset and shift masks
header files to RE2.5 (Likun)
v4: Update athub v4_1_0 register offset and shift masks
header files to RE3. (Likun)
v5: Clean up athub v4_1_0 ip headers. (Alex)
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Likun Gao <[email protected]>
Signed-off-by: Likun Gao <[email protected]>
Reviewed-by: Hawking Zhang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Cc: Jun Lei <[email protected]>
Cc: Aurabindo Pillai <[email protected]>
Cc: Hamza Mahfooz <[email protected]>
Cc: Harry Wentland <[email protected]>
Cc: Alex Deucher <[email protected]>
Reviewed-by: Aurabindo Pillai <[email protected]>
Signed-off-by: Rodrigo Siqueira <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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For debugging IPS-related issues, expose a new debug mask
that allows to disable IPS.
Usage:
amdgpu.dcdebugmask=0x800
Signed-off-by: Roman Li <[email protected]>
Tested-by: Mark Broadworth <[email protected]>
Reviewed-by: Mario Limonciello <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Replace [1] with []. Silences UBSAN warnings.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3107
Reviewed-by: Lijo Lazar <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Replace [1] with []. Silences UBSAN warnings.
Link: https://bugs.launchpad.net/ubuntu/+source/linux/+bug/2039926
Acked-by: Christian König <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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amdgpu_reg_state_sysfs_fini could be invoked at the
time when asic_func is even not initialized, i.e.,
amdgpu_discovery_init fails for some reason.
Signed-off-by: Hawking Zhang <[email protected]>
Reviewed-by: Lijo Lazar <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Fix the following errors reported by checkpatch:
ERROR: open brace '{' following struct go on the same line
ERROR: spaces required around that '=' (ctx:WxV)
Signed-off-by: chenxuebing <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Fix the following errors reported by checkpatch:
ERROR: open brace '{' following struct go on the same line
Signed-off-by: chenxuebing <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Fix the following errors reported by checkpatch:
ERROR: open brace '{' following struct go on the same line
Signed-off-by: chenxuebing <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Fix the following errors reported by checkpatch:
ERROR: open brace '{' following struct go on the same line
Signed-off-by: chenxuebing <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Fix the following errors reported by checkpatch:
ERROR: open brace '{' following struct go on the same line
Signed-off-by: chenxuebing <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Fix the following errors reported by checkpatch:
ERROR: open brace '{' following struct go on the same line
ERROR: space required after that ',' (ctx:VxV)
Signed-off-by: chenxuebing <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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sienna_cichlid_ip_offset.h
Fix the following errors reported by checkpatch:
ERROR: open brace '{' following struct go on the same line
Signed-off-by: chenxuebing <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Fix the following errors reported by checkpatch:
ERROR: open brace '{' following struct go on the same line
Signed-off-by: chenxuebing <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Fix the following errors reported by checkpatch:
ERROR: open brace '{' following struct go on the same line
Signed-off-by: chenxuebing <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Fix the following errors reported by checkpatch:
ERROR: open brace '{' following struct go on the same line
ERROR: space prohibited before that ',' (ctx:WxE)
Signed-off-by: chenxuebing <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Fix the following errors reported by checkpatch:
ERROR: open brace '{' following struct go on the same line
Signed-off-by: chenxuebing <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Fix the following errors reported by checkpatch:
ERROR: open brace '{' following enum go on the same line
Signed-off-by: chenxuebing <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Fix the following errors reported by checkpatch:
ERROR: open brace '{' following enum go on the same line
Signed-off-by: chenxuebing <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Fix the following errors reported by checkpatch:
ERROR: open brace '{' following struct go on the same line
Signed-off-by: chenxuebing <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Fix the following errors reported by checkpatch:
ERROR: space prohibited before that ',' (ctx:WxV)
Signed-off-by: chenxuebing <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Fix the following errors reported by checkpatch:
ERROR: open brace '{' following struct go on the same line
Signed-off-by: chenxuebing <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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[Why]
Enable the Panel Replay if eDP panel and ASIC support.
(prioritize Panel Replay over PSR)
[How]
- Setup the Panel Replay config during the device init
(prioritize Panel Replay over PSR).
- Separate the Replay init function into two functions
amdgpu_dm_link_setup_replay() and amdgpu_dm_set_replay_caps()
to fix the issue in the earlier commit that cause PSR and Replay
enabled at the same time.
Reviewed-by: Sun peng Li <[email protected]>
Acked-by: Alex Hung <[email protected]>
Signed-off-by: Tom Chung <[email protected]>
Tested-by: Daniel Wheeler <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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This patch is to update headers for nbio v7.11.
Signed-off-by: Yifan Zhang <[email protected]>
Acked-by: Alex Deucher <[email protected]>
Reviewed-by: Tim Huang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Add new gpu_metrics_v1_5 to acquire vcn/jpeg activity
& pcie nak error counters
Signed-off-by: Asad Kamal <[email protected]>
Reviewed-by: Lijo Lazar <[email protected]>
Reviewed-by: Le Ma <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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[WHY]
Prepare for enabling the Panel Replay feature
[HOW]
- Add some Panel Replay setting functions in DC
- Add the Panel Replay resource in dcn35_resource.c
- Add debug masks for Panel Replay
Tested-by: Daniel Wheeler <[email protected]>
Acked-by: Rodrigo Siqueira <[email protected]>
Reviewed-by: Leo Li <[email protected]>
Signed-off-by: Tom Chung <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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This reverts commit 44e60b14d5a72f91fd0bdeae8da59ae37a3ca8e5.
Since, it causes a regression in which eDP displays with PSR support,
but no Replay support (Sink support <= 0x03), fail to enable PSR and
consequently all IGT amd_psr tests fail. So, revert this until a more
suitable fix can be found.
This got brought back accidently with the backmerge.
Acked-by: Leo Li <[email protected]>
Signed-off-by: Ivan Lipski <[email protected]>
Signed-off-by: Hamza Mahfooz <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Some issues have been raised that appear to be tied to PSR-SU.
To allow users to confirm they're tied to PSR-SU without turning off
PSR entirely introduce a new debug mask:
amdgpu.dcdebugmask=0x200
Reviewed-by: Harry Wentland <[email protected]>
Signed-off-by: Mario Limonciello <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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MES provides the driver a call to explicitly flush stale process memory
within the MES to avoid a race condition that results in a fatal
memory violation.
When SET_SHADER_DEBUGGER is called, the driver passes a memory address
that represents a process context address MES uses to keep track of
future per-process calls.
Normally, MES will purge its process context list when the last queue
has been removed. The driver, however, can call SET_SHADER_DEBUGGER
regardless of whether a queue has been added or not.
If SET_SHADER_DEBUGGER has been called with no queues as the last call
prior to process termination, the passed process context address will
still reside within MES.
On a new process call to SET_SHADER_DEBUGGER, the driver may end up
passing an identical process context address value (based on per-process
gpu memory address) to MES but is now pointing to a new allocated buffer
object during KFD process creation. Since the MES is unaware of this,
access of the passed address points to the stale object within MES and
triggers a fatal memory violation.
The solution is for KFD to explicitly flush the process context address
from MES on process termination.
Note that the flush call and the MES debugger calls use the same MES
interface but are separated as KFD calls to avoid conflicting with each
other.
Signed-off-by: Jonathan Kim <[email protected]>
Tested-by: Alice Wong <[email protected]>
Reviewed-by: Eric Huang <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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Enable event log through the HW specific FW API
Signed-off-by: shaoyunl <[email protected]>
Reviewed-by: Felix Kuehling <[email protected]>
Signed-off-by: Alex Deucher <[email protected]>
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