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path: root/drivers/gpu/drm/amd/include
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2023-03-13drm/amd/amdgpu: Add missing INT_STAT_DEBUG registers to GC 10.1 and 10.3 headersTom St Denis4-0/+116
Checked against database, copied from GC 9.4.2 header. Signed-off-by: Tom St Denis <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amdgpu: add mp v13_0_6 ip headersHawking Zhang2-0/+1130
Add mp v13_0_6 register offset and shift masks header files v2: update headers (Alex) Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amdgpu/pm: add capped/uncapped power profile modesPerry Yuan1-0/+2
Capped and uncapped workload types switching are supported on Vangogh, User can switch the power profile and check current type with below commands. 1) switch to capped mode: `# echo 8 > /sys/class/drm/card0/device/pp_power_profile_mode` 2) switch to uncapped mode: `# echo 9 > /sys/class/drm/card0/device/pp_power_profile_mode` 3) check current mode: $ cat /sys/class/drm/card0/device/pp_power_profile_mode 1 3D_FULL_SCREEN 3 VIDEO 4 VR 5 COMPUTE 6 CUSTOM 8 CAPPED 9 UNCAPPED* Acked-by: Kenneth Feng <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Perry Yuan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amdgpu: add sdma v4_4_2 ip headersHawking Zhang2-0/+4385
Add sdma v4_4_2 register offset and shift masks header files v2: update headers (Alex) Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amdgpu: add hdp v4_4_2 ip headersHawking Zhang2-0/+882
Add hdp v4_4_2 register offset and shift masks header files v2: update headers (Alex) Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-02-23drm/amdgpu: added a sysfs interface for thermal throttlingKun Liu1-0/+2
added a sysfs interface for thermal throttling, then userspace can get/update thermal limit Signed-off-by: Kun Liu <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-02-15drm/amd/display: disable SubVP + DRR to prevent underflowAurabindo Pillai1-0/+1
[Why&How] Temporarily disable SubVP+DRR since Xorg has an architectural limitation where freesync will not work in a multi monitor configuration. SubVP+DRR requires that freesync be working. Whether OS has variable refresh setting enabled or not, the state on the crtc remains same unless an application requests VRR. Due to this, there is no way to know whether freesync will actually work or not while we are on the desktop from the kernel's perspective. If userspace does not have a limitation with multi-display freesync (for example wayland), then this feature can be enabled by adding a dcfeaturemask option to amdgpu on the kernel cmdline like: amdgpu.dcfeaturemask=0x200 Signed-off-by: Aurabindo Pillai <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-02-14drm/amd/amdgpu: implement mode2 reset on smu_v13_0_10Kenneth Feng1-0/+1
implement mode2 reset on smu_v13_0_10 Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amdgpu: correct query xgmi3x16 pcs error statusStanley.Yang1-0/+87
There is xgmi3x16 pcs error status for aldebaran, driver should check xgmi3x16 pcs error status field instead of gopx16 pcs error status field. Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17drm/amdgpu: Add gfx ras poison consumption irq handling on gfx v11_0_3YiPeng Chai1-0/+2
Add gfx ras poison consumption irq handling on gfx v11_0_3. V2: Move ras poison consumption irq handling code of gfx v11_0_3 to gfx_v11_0_3.c. V5: Create dedicated irq handler for RLC_GC_FED_INTERRUPT. V6: Remove invalid function call. Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-01-17amd/amdgpu: Add RLC_RLCS_FED_STATUS_* to gc v11_0_3 ip headersYiPeng Chai2-0/+58
V2: Add RLC_RLCS_FED_STATUS_0 and RLC_RLCS_FED_STATUS_1 register offset and shift masks. Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-15drm/amdgpu: Add df v4_3 headersCandice Li2-0/+187
Add df v4_3 header files. Signed-off-by: Candice Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-15drm/amd/pm: fulfill swsmu peak profiling mode shader/memory clock settingsEvan Quan1-0/+2
Enable peak profiling mode shader/memory clocks reporting for swsmu framework. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-12-01drm/amd/amdgpu: update mes11 api defJack Xiao1-1/+5
Update the api def of mes11. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Tested-and-acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-23drm/amdgpu: add missing license to some filesAlex Deucher3-0/+3
The driver is MIT, so add the licenses. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2265 Acked-by: Luben Tuikov <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-23drm/amdgpu: add register definition for VCN RAS initializationTao Zhou2-1/+29
Prepare for enableing VCN RAS poison. v2: move SHIFT and MASK definitions to related sh_mask.h file. Signed-off-by: Tao Zhou <[email protected]> Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-23drm/amdgpu: Replace remaining 1-element array with flex-arrayPaulo Miguel Almeida1-1/+1
One-element arrays are deprecated, and we are replacing them with flexible array members instead. So, replace one-element array with flexible-array member in struct GOP_VBIOS_CONTENT and refactor the rest of the code accordingly. Important to mention is that doing a build before/after this patch results in no functional binary output differences. This helps with the ongoing efforts to tighten the FORTIFY_SOURCE routines on memcpy() and help us make progress towards globally enabling -fstrict-flex-arrays=3 [1]. Link: https://github.com/KSPP/linux/issues/79 Link: https://github.com/KSPP/linux/issues/238 Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101836 [1] Signed-off-by: Paulo Miguel Almeida <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-17drm/amdgpu: add irq source id definition for VCN/JPEG 4.0Tao Zhou1-0/+3
Add interrupt source id macros. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-15drm/amdgpu: Replace one-elements array with flex-array membersPaulo Miguel Almeida1-3/+3
One-element arrays are deprecated, and we are replacing them with flexible array members instead. So, replace one-element array with flexible-array member in structs ATOM_I2C_VOLTAGE_OBJECT_V3, ATOM_ASIC_INTERNAL_SS_INFO_V2, ATOM_ASIC_INTERNAL_SS_INFO_V3, and refactor the rest of the code accordingly. Important to mention is that doing a build before/after this patch results in no functional binary output differences. This helps with the ongoing efforts to tighten the FORTIFY_SOURCE routines on memcpy() and help us make progress towards globally enabling -fstrict-flex-arrays=3 [1]. Link: https://github.com/KSPP/linux/issues/79 Link: https://github.com/KSPP/linux/issues/238 Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101836 [1] Signed-off-by: Paulo Miguel Almeida <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-10drm/amdgpu: Replace one-element array with flex-array memberPaulo Miguel Almeida1-8/+8
One-element arrays are deprecated, and we are replacing them with flexible array members instead. So, replace one-element array with flexible-array member in structs _ATOM_CONNECTOR_DEVICE_TAG_RECORD, _ATOM_OBJECT_GPIO_CNTL_RECORD, _ATOM_BRACKET_LAYOUT_RECORD, _ATOM_BRACKET_LAYOUT_RECORD, _ATOM_LEAKAGE_VOLTAGE_OBJECT_V3, _ATOM_FUSION_SYSTEM_INFO_V3, _ATOM_I2C_DATA_RECORD, _ATOM_I2C_DEVICE_SETUP_INFO, _ATOM_ASIC_MVDD_INFO and refactor the rest of the code accordingly. While at it, removed a redundant casting. Important to mention is that doing a build before/after this patch results in no binary output differences. This helps with the ongoing efforts to tighten the FORTIFY_SOURCE routines on memcpy() and help us make progress towards globally enabling -fstrict-flex-arrays=3 [1]. Link: https://github.com/KSPP/linux/issues/79 Link: https://github.com/KSPP/linux/issues/238 Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101836 [1] Signed-off-by: Paulo Miguel Almeida <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-10drm/amdgpu: add vram reservation based on vram_usagebyfirmware_v2_2Tong Liu011-9/+54
Move TMR region from top of FB to 2MB for FFBM, so we need to reserve TMR region firstly to make sure TMR can be allocated at 2MB Signed-off-by: Tong Liu01 <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-09drm/amdgpu: Replace 1-element array with flexible-array memberPaulo Miguel Almeida1-4/+4
One-element arrays are deprecated, and we are replacing them with flexible array members instead. So, replace one-element array with flexible-array member in structs _ATOM_GPIO_PIN_ASSIGNMENT, _ATOM_DISPLAY_OBJECT_PATH, _ATOM_DISPLAY_OBJECT_PATH_TABLE, _ATOM_OBJECT_TABLE and refactor the rest of the code accordingly. Important to mention is that doing a build before/after this patch results in no functional binary output differences. This helps with the ongoing efforts to tighten the FORTIFY_SOURCE routines on memcpy() and help us make progress towards globally enabling -fstrict-flex-arrays=3 [1]. Link: https://github.com/KSPP/linux/issues/79 Link: https://github.com/KSPP/linux/issues/238 Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101836 [1] Signed-off-by: Paulo Miguel Almeida <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-04drm/amdgpu: Fix type of second parameter in odn_edit_dpm_table() callbackNathan Chancellor1-1/+2
With clang's kernel control flow integrity (kCFI, CONFIG_CFI_CLANG), indirect call targets are validated against the expected function pointer prototype to make sure the call target is valid to help mitigate ROP attacks. If they are not identical, there is a failure at run time, which manifests as either a kernel panic or thread getting killed. A proposed warning in clang aims to catch these at compile time, which reveals: drivers/gpu/drm/amd/amdgpu/../pm/swsmu/amdgpu_smu.c:3008:29: error: incompatible function pointer types initializing 'int (*)(void *, uint32_t, long *, uint32_t)' (aka 'int (*)(void *, unsigned int, long *, unsigned int)') with an expression of type 'int (void *, enum PP_OD_DPM_TABLE_COMMAND, long *, uint32_t)' (aka 'int (void *, enum PP_OD_DPM_TABLE_COMMAND, long *, unsigned int)') [-Werror,-Wincompatible-function-pointer-types-strict] .odn_edit_dpm_table = smu_od_edit_dpm_table, ^~~~~~~~~~~~~~~~~~~~~ 1 error generated. There are only two implementations of ->odn_edit_dpm_table() in 'struct amd_pm_funcs': smu_od_edit_dpm_table() and pp_odn_edit_dpm_table(). One has a second parameter type of 'enum PP_OD_DPM_TABLE_COMMAND' and the other uses 'u32'. Ultimately, smu_od_edit_dpm_table() calls ->od_edit_dpm_table() from 'struct pptable_funcs' and pp_odn_edit_dpm_table() calls ->odn_edit_dpm_table() from 'struct pp_hwmgr_func', which both have a second parameter type of 'enum PP_OD_DPM_TABLE_COMMAND'. Update the type parameter in both the prototype in 'struct amd_pm_funcs' and pp_odn_edit_dpm_table() to 'enum PP_OD_DPM_TABLE_COMMAND', which cleans up the warning. Link: https://github.com/ClangBuiltLinux/linux/issues/1750 Reported-by: Sami Tolvanen <[email protected]> Reviewed-by: Kees Cook <[email protected]> Signed-off-by: Nathan Chancellor <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-11-04drm/amdgpu: Replace one-element array with flexible-array memberPaulo Miguel Almeida1-1/+1
One-element arrays are deprecated, and we are replacing them with flexible array members instead. So, replace one-element array with flexible-array member in struct _ATOM_FAKE_EDID_PATCH_RECORD and refactor the rest of the code accordingly. Important to mention is that doing a build before/after this patch results in no binary output differences. This helps with the ongoing efforts to tighten the FORTIFY_SOURCE routines on memcpy() and help us make progress towards globally enabling -fstrict-flex-arrays=3 [1]. Link: https://github.com/KSPP/linux/issues/79 Link: https://github.com/KSPP/linux/issues/238 Link: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101836 [1] Signed-off-by: Paulo Miguel Almeida <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-17drm/amdkfd: Fix type of reset_type parameter in hqd_destroy() callbackNathan Chancellor1-2/+3
When booting a kernel compiled with CONFIG_CFI_CLANG on a machine with an RX 6700 XT, there is a CFI failure in kfd_destroy_mqd_cp(): [ 12.894543] CFI failure at kfd_destroy_mqd_cp+0x2a/0x40 [amdgpu] (target: hqd_destroy_v10_3+0x0/0x260 [amdgpu]; expected type: 0x8594d794) Clang's kernel Control Flow Integrity (kCFI) makes sure that all indirect call targets have a type that exactly matches the function pointer prototype. In this case, hqd_destroy()'s third parameter, reset_type, should have a type of 'uint32_t' but every implementation of this callback has a third parameter type of 'enum kfd_preempt_type'. Update the function pointer prototype to match reality so that there is no more CFI violation. Link: https://github.com/ClangBuiltLinux/linux/issues/1738 Signed-off-by: Nathan Chancellor <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-10-11drm/amdgpu: Update umc v8_10_0 headersCandice Li2-0/+5
Add GeccCtrl offset and mask to umc v8_10_0 headers. Signed-off-by: Candice Li <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-29drm/amdgpu: pass queue size and is_aql_queue to MESGraham Sider1-1/+2
Update mes_v11_api_def.h add_queue API with is_aql_queue parameter. Also re-use gds_size for the queue size (unused for KFD). MES requires the queue size in order to compute the actual wptr offset within the queue RB since it increases monotonically for AQL queues. v2: Make is_aql_queue assign clearer Signed-off-by: Graham Sider <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-29drm/amd/amdgpu: Add missing XGMI hive registers for mmhub 9.4.1Tom St Denis2-0/+12
These are used by umr to sort the hive nodes since the kernel initializes the nodes in order of bus enumeration not XGMI hive enumeration. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-14drm/amd/pm:add new gpu_metrics_v2_3 to acquire average temperature infoLi Ma1-0/+58
Add new gpu_metrics_v2_3 to acquire average temperature info from SMU metrics. To acquire average temp info from gpu_metrics interface, but gpu_metrics_v2_2 only has members to show current temp info. --- v1: Only add average_temperature_gfx in gpu_metrics_v2_3. v2: Add average temp members for soc, core and l3 in gpu_metrics_v2_3 and put these new members at the end of gpu_metrics_v2_3. Add operation to read average temp info from metrics table. v3: Merge v1 and v2 and rename the patch. v4: Merge v3. Add firmware version judgment in vangogh_common_get_gpu_metrics to maintain backward compatibility and rename the patch. "return ret" on error scenario in smu_cmn_get_smc_version. Signed-off-by: Li Ma <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-13drm/amd/amdgpu: update GC 10.3.0 pwrdecTom St Denis2-1/+1558
The 10.3 GC headers were missing most of the pwrdec block. This patch adds the registers and bits present in the 10.1 header but based on the contents of the 10.3 specs. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-09-07drm/amd/amdgpu: Add missing CGTS*TCC_DISABLE to 10.3 headersTom St Denis2-0/+14
The TCC_DISABLE registers were not included in the 10.3 headers and instead just placed directly in the gfx_v10_0.c source. This patch adds them to the headers so tools like umr can scan them and support them. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-30drm/amdgpu: add gc v11_0_3 ip headersFrank Min2-0/+56726
Add gc v11_0_3 register offset and shift masks header files v2: update registers (Alex) Signed-off-by: Frank Min <[email protected]> Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-29drm/amdgpu: Update mes_v11_api_def.hGraham Sider1-1/+2
New GFX11 MES FW adds the trap_en bit. For now hardcode to 1 (traps enabled). Signed-off-by: Graham Sider <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-22drm/amdgpu: add TX_POWER_CTRL_1 macro definitions for NBIO IP v7.7.0Tim Huang2-0/+15
Add the BIF0_PCIE_TX_POWER_CTRL_1 register offset and mask macro definitions for AMD_CG_SUPPORT_BIF_LS. Signed-off-by: Tim Huang <[email protected]> Reviewed-by: Yifan Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-08-16drm/amdgpu: save and restore gc hub regsVictor Zhao1-0/+4
Save and restore gfxhub regs as they will be reset during mode 2 Signed-off-by: Victor Zhao <[email protected]> Acked-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-29drm/amdgpu: add header files for MP 13.0.4Xiaojian Du2-0/+997
This patch will add header files for MP 13.0.4. Signed-off-by: Xiaojian Du <[email protected]> Reviewed-by: Tim Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-28drm/amd/amdgpu: add additional page fault settings for gfx11Chengming Gui2-0/+28
Add three additional page fault settings. V2: move reg offset definition to header file. (Alex) V3: add all shift/mask definitions of used reg. (Hawking) Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-25drm/amd: Fix typo 'the the' in commentSlark Xiao1-2/+2
Replace 'the the' with 'the' in the comment. Signed-off-by: Slark Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-25drm/amd/display: Add dcdebugmask option for disabling MPOLeo Li1-0/+1
[Why & How] It's useful to disable MPO when debugging or testing. Therefore, add a dcdebugmask option to disable MPO. Signed-off-by: Leo Li <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-18drm/amdgpu: add umc v8_10_0 ip headersYiPeng Chai2-0/+127
Add umc v8_10_0 register offset and shift masks header files Signed-off-by: YiPeng Chai <[email protected]> Reviewed-by: Alexander Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-13drm/amdgpu: Add reg headers for DCN314Roman Li4-0/+139486
Register headers for the following IPs: - DCN 3.1.4 - DPCS 3.1.4 v2:(squash) clean up (Alex) Signed-off-by: Roman Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-13drm/amdgpu: fix file permissions on some filesAlex Deucher6-0/+0
Drop execute. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2085 Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-05drm/amdgpu/mes11: fix to unmap legacy queueJack Xiao1-1/+5
MES fw updated to support unmapping legacy gfx/compute queue. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-05drm/amd/display: Program ACP related registerAlan Liu1-0/+2
- Setup the shift and mask of HDMI_ACP_SEND register - Program the register in hdmi stream encoder - Also update ACP register in azalia configuration Reviewed-by: Harry Wentland <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alan Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-05drm/amd/display: Add missing registers for ACPRodrigo Siqueira5-0/+10
We are missing some ACP registers/mask value for some specific ASICs. This commit includes it to those ASICs that support it. Signed-off-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-05drm/amd: Add debug mask for subviewport mclk switchAurabindo Pillai1-0/+1
[Why&How] Expose a new dc debug mask enum to force a subviewport memory clock switch to facilitate easy testing. Signed-off-by: Aurabindo Pillai <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-30drm/amdgpu/mes11: update mes interface for acessing registersJack Xiao1-11/+26
Update MES firmware api for accessing registers. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-29drm/amd/amd_shared.h: Add missing doc for PP_GFX_DCS_MASKMauro Carvalho Chehab1-0/+1
This symbol is missing documentation: drivers/gpu/drm/amd/include/amd_shared.h:224: warning: Enum value 'PP_GFX_DCS_MASK' not described in enum 'PP_FEATURE_MASK' Document it. Fixes: 680602d6c2d6 ("drm/amd/pm: enable DCS") Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-23drm/amdgpu: Update mes_v11_api_def.hGraham Sider1-1/+3
Update MES API to support oversubscription without aggregated doorbell for usermode queues. v2: Change oversubscription_no_aggregated_en to is_kfd_process (align with MES) Signed-off-by: Graham Sider <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amd/display: add missing reg defs for DCN3x HUBBUBAurabindo Pillai4-0/+11
[Why&How] The omitted register definition caused call traces like: [ 3.811215] WARNING: CPU: 7 PID: 794 at drivers/gpu/drm/amd/amdgpu/../display/dc/dc_helper.c:120 set_reg_field_values.constprop.0+0xc7/0xe0 [amdgpu] [ 3.811406] Modules linked in: amdgpu(+) drm_ttm_helper ttm iommu_v2 gpu_sched drm_kms_helper cfbfillrect syscopyarea cfbimgblt sysfillrect sysimgblt fb_sys_fops cfbcopyarea drm i2c_piix4 drm_panel_orientation_quirks [ 3.811419] CPU: 7 PID: 794 Comm: systemd-udevd Not tainted 5.16.0-kfd+ #132 [ 3.811422] Hardware name: System manufacturer System Product Name/ROG STRIX B450-F GAMING, BIOS 3003 12/09/2019 [ 3.811425] RIP: 0010:set_reg_field_values.constprop.0+0xc7/0xe0 [amdgpu] [ 3.811615] Code: 08 49 89 51 08 8b 08 48 8d 42 08 49 89 41 08 44 8b 02 48 8d 50 08 0f b6 c9 49 89 51 08 8b 00 45 85 c0 75 b3 0f 0b eb af 5d c3 <0f> 0b e9 48 ff ff ff 49 8b 51 08 eb d0 49 8b 41 08 eb d5 66 0f 1f [ 3.811619] RSP: 0018:ffffb8c1c04cf640 EFLAGS: 00010246 [ 3.811621] RAX: 0000000000000000 RBX: ffff96f2100d8800 RCX: 0000000000000000 [ 3.811623] RDX: 0000000000000000 RSI: 0000000000000001 RDI: ffffb8c1c04cf650 [ 3.811625] RBP: ffffb8c1c04cf640 R08: 000000000000047f R09: ffffb8c1c04cf658 [ 3.811627] R10: ffff96f5161ff000 R11: ffff96f5161ff000 R12: ffff96f204afb9c0 [ 3.811629] R13: 0000000000000000 R14: ffff96f202b94c00 R15: ffffb8c1c04cf718 [ 3.811631] FS: 00007fe07c2e2880(0000) GS:ffff96f5059c0000(0000) knlGS:0000000000000000 [ 3.811634] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 3.811636] CR2: 0000559634ab57b8 CR3: 0000000120674000 CR4: 00000000003506e0 [ 3.811637] Call Trace: [ 3.811640] <TASK> [ 3.811642] generic_reg_update_ex+0x69/0x200 [amdgpu] [ 3.811831] ? _printk+0x58/0x6f [ 3.811836] dcn32_init_crb+0x18f/0x1b0 [amdgpu] [ 3.812031] dcn32_init_hw+0x379/0x6a0 [amdgpu] [ 3.812223] dc_hardware_init+0xba/0x100 [amdgpu] [ 3.812415] amdgpu_dm_init.isra.0.cold+0x166/0x1867 [amdgpu] [ 3.812616] ? dev_vprintk_emit+0x139/0x15d [ 3.812621] ? dev_printk_emit+0x4e/0x65 [ 3.812624] dm_hw_init+0x12/0x30 [amdgpu] [ 3.812820] amdgpu_device_init.cold+0x130d/0x178c [amdgpu] [ 3.813017] ? pci_read_config_word+0x25/0x40 [ 3.813021] amdgpu_driver_load_kms+0x1a/0x130 [amdgpu] [ 3.813178] amdgpu_pci_probe+0x130/0x330 [amdgpu] Fixes: 4f29f9cf092b ("drm/amd: add register headers for DCN32/321") Signed-off-by: Aurabindo Pillai <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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