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2023-08-31drm/amdgpu: add IH CLIENT ID for VPELang Yu1-0/+2
Add Interrupt Handler Client ID for Video Processing Engine. Signed-off-by: Lang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-31drm/amdgpu: add HWID for VPELang Yu1-0/+1
Add HWID for Video Processing Engine. Signed-off-by: Lang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-31drm/amdgpu: add VPE IP BLOCK definitionHuang Rui1-0/+1
Add IP BLOCK for Video Processing Engine. Signed-off-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amdgpu: add VPE 6.1.0 header filesLang Yu2-0/+5946
Add initial headers. (Ray) Update to align with hardware changes. (Lang) Updates (Alex) Signed-off-by: Huang Rui <[email protected]> Signed-off-by: Lang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Add dcn35 register header filesQingqing Zhuo2-0/+68667
[Why & How] Add register headers for DCN35. Signed-off-by: Qingqing Zhuo <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amdgpu: Add umc_info v4_0 structureHawking Zhang1-0/+18
To be used by aqua_vanjaram Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Candice Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amdgpu: add header files for MP 14.0.0Li Ma2-0/+893
This patch will add header files for MP 14.0.0. v2: updates (Alex) Signed-off-by: Li Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amdgpu: add mmhub 3.3.0 headersLang Yu2-0/+8117
Add new headers. v2: updates (Alex) Signed-off-by: Lang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amdgpu: add gc headers for gc 11.5.0Lang Yu2-0/+46531
Add gc_11_5_0 headers. v2: updates (Alex) Signed-off-by: Lang Yu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amdgpu: add nbio 7.11 registersbenl2-0/+67237
Add register headers. v2: Updates (Alex) v3: Updates (Alex) v4: Updates (Alex) Signed-off-by: benl <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amdgpu: update gc_info v2_1 from discoveryLe Ma1-0/+30
Several new fields are exposed in gc_info v2_1 Signed-off-by: Le Ma <[email protected]> Reviewed-by: Shiwu Zhang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amdgpu: update mall info v2 from discoveryLe Ma1-1/+7
Mall info v2 is introduced in ip discovery Signed-off-by: Le Ma <[email protected]> Reviewed-by: Shiwu Zhang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-30drm/amd/display: Enable Replay for static screen use casesBhawanpreet Lakha1-0/+2
- Setup replay config on device init. - Enable replay if feature is enabled (prioritize replay over PSR, since it can be enabled in more usecases) - Add debug masks to enable replay on supported ASICs Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-15drm/amd: Rename AMDGPU_PP_SENSOR_GPU_POWERMario Limonciello1-1/+1
Use the clearer name `AMDGPU_PP_SENSOR_GPU_AVG_POWER` instead. Signed-off-by: Mario Limonciello <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-15drm/amd: Introduce `AMDGPU_PP_SENSOR_GPU_INPUT_POWER`Mario Limonciello1-0/+1
Some GPUs have been overloading average power values and input power values. To disambiguate these, introduce a new `AMDGPU_PP_SENSOR_GPU_INPUT_POWER` and the GPUs that share input power update to use this instead of average power. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2746 Signed-off-by: Mario Limonciello <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-15drm/amd/display: Add some missing register definitionsAurabindo Pillai4-1/+18
[Why&How] Add some missing register definitions and rearrange some others to maintain consistency with related definitions. Acked-by: Stylon Wang <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-09drm/amdgpu: Add pci usage to nbio v7.9Asad Kamal1-0/+8
Add implementation to get pcie usage for nbio v7.9. Signed-off-by: Asad Kamal <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Reviewed-by: Shiwu Zhang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-08-07drm/amdgpu: add ih 6.1 registersBen Li2-0/+1298
Add new registers. v2: updates (Alex) Signed-off-by: Ben Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd/pm: Vangogh: Add new gpu_metrics_v2_4 to acquire gpu_metricsWenyou Yang1-0/+69
To acquire the voltage and current info from gpu_metrics interface, but gpu_metrics_v2_3 doesn't contain them, and to be backward compatible, add new gpu_metrics_v2_4 structure. Reviewed-by: Mario Limonciello <[email protected]> Acked-by: Evan Quan <[email protected]> Signed-off-by: Wenyou Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amd: open brace '{' following struct go on the same lineRan Sun1-4/+2
Fix the checkpatch error as open brace '{' following struct should go on the same line. Signed-off-by: Ran Sun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-25drm/amdkfd: enable cooperative groups for gfx11Jonathan Kim1-1/+3
MES can concurrently schedule queues on the device that require exclusive device access if marked exclusively_scheduled without the requirement of GWS. Similar to the F32 HWS, MES will manage quality of service for these queues. Use this for cooperative groups since cooperative groups are device occupancy limited. Since some GFX11 devices can only be debugged with partial CUs, do not allow the debugging of cooperative groups on these devices as the CU occupancy limit will change on attach. In addition, zero initialize the MES add queue submission vector for MES initialization tests as we do not want these to be cooperative dispatches. Signed-off-by: Jonathan Kim <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-18drm/amdgpu: Add dcdebugmask option to enable DPIA traceStylon Wang1-0/+1
[Why & How] It's useful to be able to enable DPIA trace with dcdebugmask option, especially to debug DPIA issues involved in transition of system power states. This patch adds an option to amdgpu.dcdebugmask to be picked up by amdgpu DM to enable DPIA trace. Signed-off-by: Stylon Wang <[email protected]> Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-07-12drm/amdkfd: add kfd2kgd debugger callbacks for GC v9.4.3Eric Huang1-3/+6
Implement the similarities as GC v9.4.2, and the difference for GC v9.4.3 HW spec, i.e. xcc instance. Signed-off-by: Jonathan Kim <[email protected]> Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Jonathan Kim <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: add the accelerator PCIe classShiwu Zhang1-1/+0
Add the accelerator PCIe class and match the class in amdgpu for 0x1002 devices of that class. From PCI spec: "PCI Code and ID Assignment, r1.9, sec 1, 1.19" Signed-off-by: Shiwu Zhang <[email protected]> Acked-by: Lijo Lazar <[email protected]> Acked-by: Bjorn Helgaas <[email protected]> # pci_ids.h Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdkfd: fix and enable debugging for gfx11Jonathan Kim1-0/+1
There are a couple of fixes required to enable gfx11 debugging. First, ADD_QUEUE.trap_en is an inappropriate place to toggle a per-process register so move it to SET_SHADER_DEBUGGER.trap_en. When ADD_QUEUE.skip_process_ctx_clear is set, MES will prioritize the SET_SHADER_DEBUGGER.trap_en setting. Second, to preserve correct save/restore priviledged wave states in coordination with the trap enablement setting, resume suspended waves early in the disable call. Signed-off-by: Jonathan Kim <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu/discovery: Replace fake flex-arrays with flexible-array membersGustavo A. R. Silva1-3/+3
Zero-length and one-element arrays are deprecated, and we are moving towards adopting C99 flexible-array members, instead. Use the DECLARE_FLEX_ARRAY() helper macro to transform zero-length arrays in a union into flexible-array members. And replace a one-element array with a C99 flexible-array member. Address the following warnings found with GCC-13 and -fstrict-flex-arrays=3 enabled: drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:1009:89: warning: array subscript kk is outside array bounds of ‘uint32_t[0]’ {aka ‘unsigned int[]’} [-Warray-bounds=] drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:1007:94: warning: array subscript kk is outside array bounds of ‘uint64_t[0]’ {aka ‘long long unsigned int[]’} [-Warray-bounds=] drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:1310:94: warning: array subscript k is outside array bounds of ‘uint64_t[0]’ {aka ‘long long unsigned int[]’} [-Warray-bounds=] drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c:1309:57: warning: array subscript k is outside array bounds of ‘uint32_t[0]’ {aka ‘unsigned int[]’} [-Warray-bounds=] This helps with the ongoing efforts to tighten the FORTIFY_SOURCE routines on memcpy() and help us make progress towards globally enabling -fstrict-flex-arrays=3 [1]. This results in no differences in binary output. Link: https://github.com/KSPP/linux/issues/21 Link: https://github.com/KSPP/linux/issues/193 Link: https://github.com/KSPP/linux/issues/300 Link: https://gcc.gnu.org/pipermail/gcc-patches/2022-October/602902.html [1] Reviewed-by: Kees Cook <[email protected]> Signed-off-by: Gustavo A. R. Silva <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: expose debug api for mesJonathan Kim1-1/+20
Similar to the F32 HWS, the RS64 HWS for GFX11 now supports a multi-process debug API. The skip_process_ctx_clear ADD_QUEUE requirement is to prevent the MES from clearing the process context when the first queue is added to the scheduler in order to maintain debug mode settings during queue preemption and restore. The MES clears the process context in this case due to an unresolved FW caching bug during normal mode operations. During debug mode, the KFD will hold a reference to the target process so the process context should never go stale and MES can afford to skip this requirement. Signed-off-by: Jonathan Kim <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: setup hw debug registers on driver initializationJonathan Kim5-0/+101
Add missing debug trap registers references and initialize all debug registers on boot by clearing the hardware exception overrides and the wave allocation ID index. The debugger requires that TTMPs 6 & 7 save the dispatch ID to map waves onto dispatch during compute context inspection. In order to correctly set this up, set the special reserved CP bit by default whenever the MQD is initailized. Signed-off-by: Jonathan Kim <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: add kgd hw debug mode setting interfaceJonathan Kim1-0/+34
Introduce the require KGD debug calls that will execute hardware debug mode setting. Signed-off-by: Jonathan Kim <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: add the accelerator pcie classShiwu Zhang1-0/+1
v2: add the base class id for accelerator (lijo) v3: add the new pci class in amdgpu tree (hawking) Signed-off-by: Shiwu Zhang <[email protected]> Acked-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: Disable interrupt tracker on NBIOv7.9Lijo Lazar1-0/+2
Enabling nBIF interrupt history tracker prevents LCLK deep sleep, hence disable it Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: Add gc v9_4_3 ras error status registersHawking Zhang2-0/+1304
GC v9_4_3 introduces UE|CE_ERR_STATUS_LO|HI to log hardware errors Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: Add vcn/jpeg ras err status registersHawking Zhang2-0/+573
Add new ras error status registers introduced in vcn v4_0_3 to log vcn and jpeg ras error. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: Add mmhub v1_8_0 ras err status registersHawking Zhang2-8/+373
add new ras error status registers introduced in mmhub v1_8_0 to log mmea and mm_cane ras err, including MMEAx_UE|CE_ERR_STATUS_LO|HI MM_CANE_UE|CE_ERR_STATUS_LO|HI Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: Add sdma v4_4_2 ras registersHawking Zhang2-0/+28
SDMA_UE_ERR_STATUS_HI|LO are introduced in v4_4_2 to replace SDMA_EDC_COUNTER/COUNTER2 registers to log SDMA RAS errors Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: add smuio v13_0_3 ip headersHawking Zhang2-0/+605
Add smuio v13_0_3 register offset and shift masks header files v2: update headers (Alex) Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: update ip discovery header to v4Le Ma1-1/+29
version 4 supports 64bit ip base address Signed-off-by: Le Ma <[email protected]> Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: add new vram type for dgpuHawking Zhang1-0/+1
hbm3 will be supported in some dgpu program Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdkfd: Add XCC instance to kgd2kfd interface (v3)Mukul Joshi1-11/+14
Gfx 9 starts to have multiple XCC instances in one device. Add instance parameter to kgd2kfd functions where XCC instance was hard coded as 0. Also, update code to pass the correct instance number when running on a multi-XCC setup. v2: introduce the XCC instance to gfx v11 (Morris) v3: rebase (Alex) Signed-off-by: Amber Lin <[email protected]> Signed-off-by: Mukul Joshi <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Tested-by: Amber Lin <[email protected]> Signed-off-by: Morris Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdkfd: Update MQD management on multi XCC setupMukul Joshi1-6/+24
Update MQD management for both HIQ and user-mode compute queues on a multi XCC setup. MQDs needs to be allocated, initialized, loaded and destroyed for each XCC in the KFD node. v2: squash in fix "drm/amdkfd: Fix SDMA+HIQ HQD allocation on GFX9.4.3" Signed-off-by: Mukul Joshi <[email protected]> Signed-off-by: Amber Lin <[email protected]> Tested-by: Amber Lin <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-06-09drm/amdgpu: add vcn v4_0_3 ip headersHawking Zhang2-0/+12678
Add vcn v4_0_3 register offset adn shift masks header files v2: update headers (Alex) Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-24Revert "drm/amd/display: disable SubVP + DRR to prevent underflow"Aurabindo Pillai1-1/+0
This reverts commit 80c6d6804f31451848a3956a70c2bcb1f07cfcb0. The orignal commit was intended as a workaround to prevent underflow and flickering when using one normal monitor and the other high refresh rate monitor (> 120Hz). This patch is being reverted in favour of a software solution to enable SubVP+DRR Signed-off-by: Aurabindo Pillai <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-13drm/amdgpu: Enable IH retry CAM on GFX9Mukul Joshi2-0/+17
This patch enables the IH retry CAM on GFX9 series cards. This retry filter is used to prevent sending lots of retry interrupts in a short span of time and overflowing the IH ring buffer. This will also help reduce CPU interrupt workload. Signed-off-by: Mukul Joshi <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-04-11drm/amdgpu: add new parameters in v11_structArvind Yadav1-8/+8
Added some new parameters defined for the gfx usermode queues use cases in the v11_mqd_struct. Cc: Alex Deucher <[email protected]> Cc: Christian Koenig <[email protected]> Reviewed-by: Shashank Sharma <[email protected]> Signed-off-by: Arvind Yadav <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-31drm/amd/pm: add sysfs node vclk1 and dclk1Tong Liu011-0/+2
User can check pp_dpm_vclk1 and pp_dpm_dclk1 for DPM frequency of vcn and dcn Signed-off-by: Tong Liu01 <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-31drm/amdgpu: add mmhub v1_8_0 ip headersHawking Zhang2-0/+25629
Add mmhub v1_8_0 register offset and shift masks header files v2: update headers (Alex) Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-31drm/amdgpu: add gc v9_4_3 ip headersHawking Zhang2-0/+37793
Add gc v9_4_3 register offset and shift masks header files v2: update headers (Alex) v3: more updates (Alex) Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-31drm/amdgpu: add osssys v4_4_2 ip headersHawking Zhang2-0/+1258
Add osssys v4_4_2 register offset and shift masks header files v2: update headers (Alex) Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-31drm/amdgpu: add athub v1_8_0 ip headersHawking Zhang2-0/+2218
Add athub v1_8_0 register offset and shift masks header files v2: update headers (Alex) Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-31drm/amdgpu: add nbio v7_9_0 ip headersHawking Zhang2-0/+48902
Add nbio v7_9_0 register offset and shift masks header files v2: update headers (Alex) v3: squash in updates (Alex) Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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