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2017-03-29drm/amdgpu: add SDMA 4.0 register headersAlex Deucher6-0/+5316
These are the System DMA register headers for vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add OSSSYS 4.0 register headersAlex Deucher3-0/+1699
These are the OS Services register headers for vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add NBIO 6.1 register headersAlex Deucher3-0/+159873
These are the Bus IO registers for vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add NBIF 6.1 register headersAlex Deucher3-0/+13240
These are the Bus InterFace registers for vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add MP 9.0 register headersAlex Deucher3-0/+2180
MP is the system management controller on vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add the MMHUB 1.0 register headersAlex Deucher3-0/+13105
Add the MultiMedia Hub registers for vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add the HDP 4.0 register headersAlex Deucher3-0/+927
These are the Host Data Path registers for vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add the GC 9.0 register headersAlex Deucher3-0/+40971
Add the Graphics Core register headers for vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: Add the DCE 12.0 register headersAlex Deucher3-0/+92697
These are the register headers for the Display and Composition Engine on vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: Add ATHUB 1.0 register headersAlex Deucher3-0/+2739
ATHUB is part of the memory controller on soc15 asics. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add vega10_enum.hAlex Deucher1-0/+22531
This adds the register bitfield enums for vega10. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add soc15ip.hAlex Deucher1-0/+1343
This header defines the IP layout for soc15 based SoCs. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add the new atomfirmware interface headerAlex Deucher3-0/+2720
soc15 asics have a new vbios interface. These headers define that interface. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amd/powerplay: add a new register define for APU in VI.Rex Zhu2-0/+3
the ixcurrent_pg_status addr is different between APU and DGPU. Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add new ATIF ACPI methodAlex Deucher1-0/+12
Used for fetching external GPU information. Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add DF MGCG flagHuang Rui1-0/+1
Acked-by: Christian König <[email protected]> Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: add DRM MGCG headerHuang Rui1-0/+1
Acked-by: Christian König <[email protected]> Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: switch ih handling to two levels (v3)Alex Deucher1-9/+10
Newer asics have a two levels of irq ids now: client id - the IP src id - the interrupt src within the IP v2: integrated Christian's comments. v3: fix rebase fail in SI and CIK Signed-off-by: Alex Deucher <[email protected]> Signed-off-by: Ken Wang <[email protected]> Reviewed-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu/gfx8: move CE&DE meta data structure to vi_structs.hXiangliang Yu1-0/+106
Because different HWs have different definition for CE & DE meta data, follow mqd design to move the structures to vi_structs.h. And change the prefix from amdgpu to vi as the structures is only for VI family. Signed-off-by: Xiangliang Yu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29gpu: drm: amd/radeon: Convert printk(KERN_<LEVEL> to pr_<level>Joe Perches1-2/+2
Use a more common logging style. Miscellanea: o Coalesce formats and realign arguments o Neaten a few macros now using pr_<level> Signed-off-by: Joe Perches <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amdgpu: implement PRT for GFX6 v2Christian König1-0/+4
Enable/disable the handling globally for now and print a warning when we enable it for the first time. v2: write to the correct register, adjust bits to that hw generation v3: fix compilation, add the missing register bit definitions Signed-off-by: Christian König <[email protected]> Reviewed-by: Nicolai Hähnle <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-03-29drm/amd/amdgpu: add power profile sysfs entryEric Huang1-0/+14
Add the sysfs entries pp_gfx_power_profile and pp_compute_power_profile which give user a way to set power profile through parameters minimum sclk, minimum mclk, activity threshold, up hysteresis and down hysteresis only when the entry power_dpm_force_performance_level is in default value "auto". It is read and write. Example: echo 500 800 20 0 5 > /sys/class/drm/card0/device/pp_*_power_profile cat /sys/class/drm/card0/device/pp_*_power_profile 500 800 20 0 5 Note: first parameter is sclk in MHz, second is mclk in MHz, third is activity threshold in percentage, fourth is up hysteresis in ms and fifth is down hysteresis in ms. echo set > /sys/class/drm/card0/device/pp_*_power_profile To set power profile state if it exists. echo reset > /sys/class/drm/card0/device/pp_*_power_profile To restore default state and clear previous setting. Signed-off-by: Eric Huang <[email protected]> Acked-by: Rex Zhu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-02-27scripts/spelling.txt: add "aligment" pattern and fix typo instancesMasahiro Yamada1-3/+3
Fix typos and add the following to the scripts/spelling.txt: aligment||alignment I did not touch the "N_BYTE_ALIGMENT" macro in drivers/net/wireless/realtek/rtlwifi/wifi.h to avoid unpredictable impact. I fixed "_aligment_handler" in arch/openrisc/kernel/entry.S because it is surrounded by #if 0 ... #endif. It is surely safe and I confirmed "_alignment_handler" is correct. I also fixed the "controler" I found in the same hunk in arch/openrisc/kernel/head.S. Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Andrew Morton <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
2017-02-27scripts/spelling.txt: add "swith" pattern and fix typo instancesMasahiro Yamada1-1/+1
Fix typos and add the following to the scripts/spelling.txt: swith||switch swithable||switchable swithed||switched swithing||switching While we are here, fix the "update" to "updates" in the touched hunk in drivers/net/wireless/marvell/mwifiex/wmm.c. Link: http://lkml.kernel.org/r/[email protected] Signed-off-by: Masahiro Yamada <[email protected]> Signed-off-by: Andrew Morton <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
2017-02-16drm/amd/powerplay: add kicker flag into smumgrHuang Rui1-0/+1
Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-02-13drm/amdgpu: read hw register to check pg status.Rex Zhu7-1/+12
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-02-08drm/amdgpu: add current_pg_status register define for smu7.1Rex Zhu1-0/+1
Signed-off-by: Rex Zhu <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu: move misc si headers into amdgpuAlex Deucher2-3402/+0
Move these to the amdgpu directory to match what we do for other asics. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu: remove unused header si_reg.hAlex Deucher1-105/+0
All of these are available elsewhere. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu: extend profiling mode.Rex Zhu1-1/+5
in profiling mode, powerplay will fix power state as stable as possible.and disable gfx cg and LBPW feature. profile_standard: as a prerequisite, ensure power and thermal sustainable, set clocks ratio as close to the highest clock ratio as possible. profile_min_sclk: fix mclk as profile_normal, set lowest sclk profile_min_mclk: fix sclk as profile_normal, set lowest mclk profile_peak: set highest sclk and mclk, power and thermal not sustainable profile_exit: exit profile mode. enable gfx cg/lbpw feature. Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu: introduce an interface to get clock gating status dynamicallyHuang Rui1-0/+2
Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amd/powerplay: add profiling mode in dpm levelRex Zhu1-0/+1
In some case, App need to run under max stable clock. so export profiling mode: GFX CG was disabled. and user can select the max stable clock of the device. Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amd/powerplay: Unify dpm level definesRex Zhu1-0/+7
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amdgpu: add cgs interface for enter/exit rlc safe mode.Rex Zhu1-0/+7
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amd/amdgpu: Add DPHY_SCRAM_CNTL register definesHarry Wentland8-0/+50
This is required for DP HBR2 test pattern Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-27drm/amd/amdgpu: Add HDMI_DATA_SCRAMBLE register definitionHarry Wentland2-0/+4
This is required by HDMI 2.0 Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-06drm/amd/powerplay: extend smu's response timeout time.Rex Zhu1-1/+1
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-01-06drm/amd/amdgpu: add Polaris12 support (v3)Junwei Zhang1-0/+1
v2: agd: squash in various fixes v3: agd: squash in: drm/amdgpu: remove unnecessary smc sk firmware for polaris12 Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Ken Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-12-23Merge branch 'drm-next-4.10' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie1-0/+4
into drm-fixes - fix display regression on DCE6/8 - Powergating fixes for GFX8 - amdgpu SI fixes (golden settings, proper rev id setup, etc.) * 'drm-next-4.10' of git://people.freedesktop.org/~agd5f/linux: (21 commits) drm/amdgpu: update tile table for oland/hainan drm/amdgpu: update tile table for verde drm/amdgpu: update rev id for verde drm/amdgpu: update golden setting for verde drm/amdgpu: update rev id for oland drm/amdgpu: update golden setting for oland drm/amdgpu: update rev id for hainan drm/amdgpu: update golden setting for hainan drm/amdgpu: update rev id for pitcairn drm/amdgpu: update golden setting for pitcairn drm/amdgpu: update golden setting/tiling table of tahiti drm/amdgpu: fix cursor setting of dce6/dce8 drm/amdgpu: refine set clock gating for tonga/polaris drm/amdgpu: initialize cg flags for tonga/polaris10/polaris11. drm/amdgpu: add new gfx cg flags. drm/amdgpu: fix pg can't be disabled by PG mask. drm/amdgpu: always initialize gfx pg for gfx_v8.0. drm/amdgpu: enable AMD_PG_SUPPORT_CP in Carrizo/Stoney. drm/amdgpu: fix init save/restore list in gfx_v8.0 drm/amdgpu: fix enable_cp_power_gating in gfx_v8.0. ...
2016-12-15drm/amdgpu: add new gfx cg flags.Rex Zhu1-0/+4
Signed-off-by: Rex Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-12-13Merge tag 'drm-for-v4.10' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds21-0/+54161
Pull drm updates from Dave Airlie: "This is the main pull request for drm for 4.10 kernel. New drivers: - ZTE VOU display driver (zxdrm) - Amlogic Meson Graphic Controller GXBB/GXL/GXM SoCs (meson) - MXSFB support (mxsfb) Core: - Format handling has been reworked - Better atomic state debugging - drm_mm leak debugging - Atomic explicit fencing support - fbdev helper ops - Documentation updates - MST fbcon fixes Bridge: - Silicon Image SiI8620 driver Panel: - Add support for new simple panels i915: - GVT Device model - Better HDMI2.0 support on skylake - More watermark fixes - GPU idling rework for suspend/resume - DP Audio workarounds - Scheduler prep-work - Opregion CADL handling - GPU scheduler and priority boosting amdgfx/radeon: - Support for virtual devices - New VM manager for non-contig VRAM buffers - UVD powergating - SI register header cleanup - Cursor fixes - Powermanagement fixes nouveau: - Powermangement reworks for better voltage/clock changes - Atomic modesetting support - Displayport Multistream (MST) support. - GP102/104 hang and cursor fixes - GP106 support hisilicon: - hibmc support (BMC chip for aarch64 servers) armada: - add tracing support for overlay change - refactor plane support - de-midlayer the driver omapdrm: - Timing code cleanups rcar-du: - R8A7792/R8A7796 support - Misc fixes. sunxi: - A31 SoC display engine support imx-drm: - YUV format support - Cleanup plane atomic update mali-dp: - Misc fixes dw-hdmi: - Add support for HDMI i2c master controller tegra: - IOMMU support fixes - Error handling fixes tda998x: - Fix connector registration - Improved robustness - Fix infoframe/audio compliance virtio: - fix busid issues - allocate more vbufs qxl: - misc fixes and cleanups. vc4: - Fragment shader threading - ETC1 support - VEC (tv-out) support msm: - A5XX GPU support - Lots of atomic changes tilcdc: - Misc fixes and cleanups. etnaviv: - Fix dma-buf export path - DRAW_INSTANCED support - fix driver on i.MX6SX exynos: - HDMI refactoring fsl-dcu: - fbdev changes" * tag 'drm-for-v4.10' of git://people.freedesktop.org/~airlied/linux: (1343 commits) drm/nouveau/kms/nv50: fix atomic regression on original G80 drm/nouveau/bl: Do not register interface if Apple GMUX detected drm/nouveau/bl: Assign different names to interfaces drm/nouveau/bios/dp: fix handling of LevelEntryTableIndex on DP table 4.2 drm/nouveau/ltc: protect clearing of comptags with mutex drm/nouveau/gr/gf100-: handle GPC/TPC/MPC trap drm/nouveau/core: recognise GP106 chipset drm/nouveau/ttm: wait for bo fence to signal before unmapping vmas drm/nouveau/gr/gf100-: FECS intr handling is not relevant on proprietary ucode drm/nouveau/gr/gf100-: properly ack all FECS error interrupts drm/nouveau/fifo/gf100-: recover from host mmu faults drm: Add fake controlD* symlinks for backwards compat drm/vc4: Don't use drm_put_dev drm/vc4: Document VEC DT binding drm/vc4: Add support for the VEC (Video Encoder) IP drm: Add TV connector states to drm_connector_state drm: Turn DRM_MODE_SUBCONNECTOR_xx definitions into an enum drm/vc4: Fix ->clock_select setting for the VEC encoder drm/amdgpu/dce6: Set MASTER_UPDATE_MODE to 0 in resume_mc_access as well drm/amdgpu: use pin rather than pin_restricted in a few cases ...
2016-12-12treewide: Make remaining source files non-executableJoe Perches3-0/+0
.c and .h source files should not be executable, change the permissions to 0644. [ This would normally go through Andrew Morton, but his ancient patch-based toolchain doesn't do permission changes ] Signed-off-by: Joe Perches <[email protected]> Acked-by: David Howells <[email protected]> Signed-off-by: Linus Torvalds <[email protected]>
2016-11-23drm/amd/amdgpu: port of DCE v6 to new headers (v3)Tom St Denis1-0/+12
Port of SI DCE v6 over to new AMDGPU headers. Tested on a Tahiti with GNOME through various hot plugs/rotations/sizes/fullscreen/windowed and staging drm/xf86-video-amdgpu. (v2) Re-factored to remove formatting changes to si_enums.h as well rename various defines. (v3) Rebase on upstream Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amd/amdgpu: add SI defines/registersTom St Denis2-0/+27
Add missing gca MMIO registers and defines necessary for the next patch which re-works a lot of gfx v6 to use the new SI headers. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-11-11drm/amd/amdgpu: Introduction of SI registers (v2)Tom St Denis16-0/+54087
This introduces the SI registers in the amdgpu driver style. v2: squash duplicates fix Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: use same vce state definition in dpm and powerplayRex Zhu1-0/+23
Reviewed-by: Christian König <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu:add MEC_STORAGE ucode id for sriovMonk Liu1-0/+1
for sriov, SMC need MEC_STORAGE reserved in fw bo. Signed-off-by: Monk Liu <[email protected]> Signed-off-by: Frank Min <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu:add callback in cgs for sriov detectFrank Min1-0/+5
Signed-off-by: Frank Min <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu:use smc_index_11 for VIMonk Liu3-0/+6
for VI smc, index_0 to index_8 are all not safe, they may used by BIOS/FW, and index_11 is reserved only for driver. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-14drm/amdgpu: fix amdgpu_need_full_reset (v2)Alex Deucher1-1/+1
IP types are not an index. Each asic may have number and type of IPs. Properly check the the type rather than using the type id as an index. v2: fix all the IPs to not use IP type as an idx as well. Reviewed-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
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