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2018-09-20drm/amdkfd: Change the control stack MTYPE from UC to NC on GFX9Yong Zhao1-1/+1
CWSR fails on Raven if the control stack is MTYPE_UC, which is used for regular GART mappings. As a workaround we map it using MTYPE_NC. The MEC firmware expects the control stack at one page offset from the start of the MQD so it is part of the MQD allocation on GFXv9. AMDGPU added a memory allocation flag just for this purpose. Acked-by: Alex Deucher <[email protected]> Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-08-08Merge branch 'drm-next-4.19' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie1-4/+11
into drm-next Fixes for 4.19: - Fix UVD 7.2 instance handling - Fix UVD 7.2 harvesting - GPU scheduler fix for when a process is killed - TTM cleanups - amdgpu CS bo_list fixes - Powerplay fixes for polaris12 and CZ/ST - DC fixes for link training certain HMDs - DC fix for vega10 blank screen in certain cases From: Alex Deucher <[email protected]> Signed-off-by: Dave Airlie <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2018-07-27drm/amd: Add missing fields in atom_integrated_system_info_v1_11Harry Wentland1-4/+11
This structure needs to align with structure in atomfirmware table. Update it. Signed-off-by: Harry Wentland <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-16drm/amdgpu: Add kfd2kgd.set_compute_idle interfaceFelix Kuehling1-0/+5
This allows automatic switching to the compute power profile depending on compute activity. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Eric Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Oded Gabbay <[email protected]>
2018-07-13drm/amd: Add interrupt source definitions for SOC15 v3.Andrey Grodzovsky9-0/+359
Stop using 'magic numbers' when registering interrupt sources. v2: Switch to kernel style comments. v3: Rebase. Signed-off-by: Andrey Grodzovsky <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd: Add interrupt source definitions for VI v3.Andrey Grodzovsky1-0/+98
Stop using 'magic numbers' when registering interrupt sources. v2: Clean redundant comments. Switch to kernel style comments. v3: Add CP_ECC_ERROR define Signed-off-by: Andrey Grodzovsky <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-11drm/amd: Add gpu reset interfaces between amdgpu and amdkfdShaoyun Liu1-0/+10
Signed-off-by: Shaoyun Liu <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Oded Gabbay <[email protected]>
2018-07-11drm/amdkfd: fix zero reading of VMID and PASID for HawaiiLan Xiao1-0/+5
Upon VM Fault, the VMID and PASID written by HW are zeros in Hawaii. Instead of reading from ih_ring_entry, read directly from the registers. This workaround fix the soft hang issues caused by mishandled VM Fault in Hawaii. Signed-off-by: Lan Xiao <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Oded Gabbay <[email protected]>
2018-07-11drm/amdgpu: save vm fault information for amdkfdshaoyunl1-0/+20
amdgpu save the vm fault related information for KFD usage and keep the copy until KFD read it. Signed-off-by: shaoyun liu <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Oded Gabbay <[email protected]>
2018-07-05drm/amd: Add sphinx documentation for amd_ip_funcsDarren Powell1-18/+27
Signed-off-by: Darren Powell <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/pp: Remove the same struct define in powerplayRex Zhu1-35/+2
delete the same struct define in powerplay, share the struct with display. Acked-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/pp: Export notify_smu_enable_pwe to displayRex Zhu1-3/+4
Display can notify smu to enable pwe after gpu suspend. It is used in case when display resumes from S3 and wants to start audio driver by enabling pwe Acked-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amdgpu: update amd_pcie.h to include gen4 speedsAlex Deucher1-0/+2
Internal header used by the driver to specify pcie gen speeds of the asic and chipset. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/pp: Refine the interface exported to displayRex Zhu1-2/+1
use void * as function parameter type in order for extension. Acked-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/powerplay: smc_dpm_info structure changeEvan Quan1-1/+4
A new member Vr2_I2C_address is added. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amdgpu: Add stutter mode ctrl in module parameterrex zhu1-0/+1
Enable stutter mode can save power in low DRAM use cases including but not limited to productivity application use, web browsing, and video playback. Currently this feature is disabled by default. Make bit 17 in module parameter amdgpu_pp_feature_mask as stutter mode mask, so user can enable/disable this feature easily. Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/pp: Unify powergate_uvd/vce/mmhub to set_powergating_by_smuRex Zhu1-3/+2
Some HW ip blocks need call SMU to enter/leave power gate state. So export common set_powergating_by_smu interface. 1. keep consistent with set_clockgating_by_smu 2. scales easily to powergate other ip(gfx) if necessary Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amdgpu: Rename set_mmhub_powergating_by_smu to powergate_mmhubRex Zhu1-1/+1
In order to keep consistent with powergate_uvd/vce. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-06-15drm/amdgpu: add more jpeg register offset headersBoyuan Zhang1-0/+20
Add more jpeg registers defines that are needed for jpeg ring functions Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-06-13drm/amd/include: Update df 3.6 mask and shift definitionShaoyun Liu1-4/+4
The register field hsas been changed in df 3.6, update to correct setting Signed-off-by: Shaoyun Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-30drm/amdgpu: correct SMU11 SYSPLL0 clock id valuesEvan Quan1-7/+5
The SMU11 SYSPLL0 clock ids were assigned wrong values. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-24drm/amdgpu: Update GFX info structure to match what vega20 usedShaoyun Liu1-1/+2
Update to the latest version from the vbios team. Signed-off-by: Shaoyun Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-24drm/amdgpu: Add CG/PG flags for VCNRex Zhu1-1/+2
Define new clock and powergating flags for VCN block. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-23drm/amdgpu: add new DF 1.7 register defsAlex Deucher2-0/+8
Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu: add df 3.6 headersAlex Deucher3-0/+107
Needed for vega20. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu/vg20:Add IH client ID for the 2nd UVDJames Zhu1-0/+1
For Vega20, there are two UVD hardware. Need add the 2nd IH client ID for the 2nd UVD Hardware. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu/atomfirmware: add new gfx_info data table v2.4 (v2)Alex Deucher1-0/+34
Adds additional gfx configuration data. v2: fix typo Acked-by: Christian König <[email protected]> Reviewed-by: Hawking Zhang <Hawking.Zhang> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amd: Add dce-12.1 gpio aux registers (v2)Roman Li2-0/+164
Updating dce12 register headers by adding dc registers required for potential DP LTTPR support. v2: fix mode change Acked-by: Christian König <[email protected]> Signed-off-by: Roman Li <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amd/include/vg20: adjust VCE_BASE to reuse vce 4.0 header filesJames Zhu1-1/+2
Vega20 uses vce 4.1 engine, all the registers have the same absolute offset with vce 4.0. By adjusting vega20 VCE_BASE, vce 4.1 can reuse vce 4.0 header files. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amd: Add vega20_ip_offset.h headerfile for vega20. (v2)Feifei Xu1-0/+1050
This headerfile contains vega20's ip base addresses. v2: squash in MP1_BASE fix Acked-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-16Merge branch 'drm-next-4.18' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie10-187/+327
into drm-next Main changes for 4.18. I'd like to do a separate pull for vega20 later this week or next. Highlights: - Reserve pre-OS scanout buffer during init for seemless transition from console to driver - VEGAM support - Improved GPU scheduler documentation - Initial gfxoff support for raven - SR-IOV fixes - Default to non-AGP on PowerPC for radeon - Fine grained clock voltage control for vega10 - Power profiles for vega10 - Further clean up of powerplay/driver interface - Underlay fixes - Display link bw updates - Gamma fixes - Scatter/Gather display support on CZ/ST - Misc bug fixes and clean ups [airlied: fixup v3d vs scheduler API change] Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Dave Airlie <[email protected]>
2018-05-15drm/amd: Add BIOS smu_info v3_3 required struct def.Jerry (Fangzhi) Zuo1-2/+168
Signed-off-by: Jerry (Fangzhi) Zuo <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amd: add a new struct in atombios.hEric Huang1-0/+7
Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amd/pp: Print out voltage/clock range in sysfsRex Zhu1-0/+1
when user cat pp_od_clk_voltage add display info about the sclk/mclk/vddc range that user can overdrive output as: OD_SCLK: 0: 300MHz 900mV 1: 400MHz 912mV 2: 500MHz 925mV 3: 600MHz 937mV 4: 700MHz 950mV 5: 800MHz 975mV 6: 900MHz 987mV 7: 1000MHz 1000mV OD_MCLK: 0: 300MHz 900mV 1: 1500MHz 912mV OD_RANGE: SCLK: 300MHz 1200MHz MCLK: 300MHz 1500MHz VDDC: 700mV 1200mV also 1. remove unnecessary whitespace before a quoted newline 2. change unit of frequency Mhz to MHz Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amdgpu: add gfxoff feature maskHuang Rui1-0/+1
Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amdgpu: move PP_FEATURE_MASK to amd_shared headerHuang Rui1-0/+19
It will be used not only for powerplay but also on amdgpu part in future patches. So move it into amd_shared header file. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amd/pp: Remove dead interfaceRex Zhu1-5/+0
Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amd/pp: Remove struct pp_gpu_powerRex Zhu1-7/+0
Currently smu only calculate average gpu power in real time. for vddc/vddci/max power, User need to set start time and end time, firmware can calculate the average vddc/vddci/max power. but the type of return values is not unified. For Vi, return type is uint. For vega, return type is float. so this struct can't be suitable for all asics. Acked-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-04-11drm/amdgpu: add df v1_7 header filesHawking Zhang3-0/+107
Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-04-11drm/amdgpu: remove duplicate cg/pg wrapper functionsRex Zhu1-31/+0
Reviewed-by: Alex Deucher <[email protected]> Acked-by: Christian König<[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-04-11drm/amdgpu: Delete some cgs functionsRex Zhu1-139/+0
Drop cgs wrappers that are no longer used. 1. cgs_rel_firmwar 2. cgs_is_virtualization_enabled 3. cgs_notify_dpm_enabled 4. cgs_atom_get_data_table 5. cgs_atom_get_cmd_table_revs 6. cgs_atom_exec_cmd_table 7. cgs_get_active_displays_info Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-04-11drm/amdgpu: Add CM_TEST_DEBUG regs for DCNHarry Wentland2-3/+24
We'd like to use them for reading DCN debug status. Signed-off-by: Harry Wentland <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-04-10drm/amdgpu: Add doorbell routing info to kgd2kfd_shared_resourcesFelix Kuehling1-0/+15
This is needed for Vega10 and later ASICs to let KFD know which doorbells can be used for SDMA and CP queues respectively. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Oded Gabbay <[email protected]> Signed-off-by: Oded Gabbay <[email protected]>
2018-04-10drm/amd: Update GFXv9 SDMA MQD structureFelix Kuehling1-24/+24
This matches what the HWS firmware expects on GFXv9 chips. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Oded Gabbay <[email protected]> Signed-off-by: Oded Gabbay <[email protected]>
2018-04-10drm/amdgpu: Remove unused interface from kfd2kgd interfaceFelix Kuehling1-5/+0
Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Oded Gabbay <[email protected]> Signed-off-by: Oded Gabbay <[email protected]>
2018-04-03drm/amd/powerplay: Enable ACG SS featureKenneth Feng1-4/+8
Port the atomfirmware.h and populates the updated pptable to SMU.With the new parameters in the new pptable, the ACG SS feature is enabled. Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-03-23drm/amdkfd: Add quiesce_mm and resume_mm to kgd2kfd_callsFelix Kuehling1-0/+6
These interfaces allow KGD to stop and resume all GPU user mode queue access to a process address space. This is needed for handling MMU notifiers of userptrs mapped for GPU access in KFD VMs. Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Oded Gabbay <[email protected]> Signed-off-by: Oded Gabbay <[email protected]>
2018-03-15drm/amdkfd: Add ioctls for GPUVM memory managementFelix Kuehling1-0/+2
v2: * Fix error handling after kfd_bind_process_to_device in kfd_ioctl_map_memory_to_gpu v3: * Add ioctl to acquire VM from a DRM FD v4: * Return number of successful map/unmap operations in failure cases * Facilitate partial retry after failed map/unmap * Added comments with parameter descriptions to new APIs * Defined AMDKFD_IOC_FREE_MEMORY_OF_GPU write-only Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Oded Gabbay <[email protected]>
2018-03-15drm/amdgpu: Add kfd2kgd interface to acquire an existing VMFelix Kuehling1-0/+2
This allows acquiring an existing VM from a render node FD to use it for a compute process. Such VMs get destroyed when the original file descriptor is released. Added a callback from amdgpu_vm_fini to handle KFD VM destruction correctly in this case. v2: * Removed vm->vm_context check in amdgpu_amdkfd_gpuvm_destroy_cb, check vm->process_info earlier instead Signed-off-by: Felix Kuehling <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Oded Gabbay <[email protected]>
2018-03-21drm/amdgpu: Remove wrapper layer of cgs irq handlingRex Zhu2-120/+0
v2: add Vega12 support 1. remove struct cgs_os_ops 2. delete cgs_linux.h 3. refine the irq code for vega10, can fix set pp table failed issue. 4. add common smu irq process function Acked-by: Christian König <[email protected]> Acked-by: Junwei Zhang <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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