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2021-06-04drm/amd/pm: sysfs attrs to read ss powershare (v6)Sathishkumar S1-0/+2
add sysfs attrs to read smartshift APU and DGPU power share. document the sysfs device attributes. V2: change variable/macro name for stapm power limit (Lijo) V3: files to be exposed as sysfs device attributes (Alex) V4: check ret value of sysfs create and remove only if created. V5: add ss attrs in amdgpu_device_attrs and use attr_update (Lijo) V6: all checks for ss support to be in if else if statements. (Lijo) Signed-off-by: Sathishkumar S <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04Merge tag 'amd-drm-next-5.14-2021-06-02' of ↵Dave Airlie4-7/+99
https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.14-2021-06-02: amdgpu: - GC/MM register access macro clean up for SR-IOV - Beige Goby updates - W=1 Fixes - Aldebaran fixes - Misc display fixes - ACPI ATCS/ATIF handling rework - SR-IOV fixes - RAS fixes - 16bpc fixed point format support - Initial smartshift support - RV/PCO power tuning fixes for suspend/resume - More buffer object subclassing work - Add new INFO query for additional vbios information - Add new placement for preemptable SG buffers amdkfd: - Misc fixes radeon: - W=1 Fixes - Misc cleanups UAPI: - Add new INFO query for additional vbios information Useful for debugging vbios related issues. Proposed umr patch: https://patchwork.freedesktop.org/patch/433297/ - 16bpc fixed point format support IGT test: https://lists.freedesktop.org/archives/igt-dev/2021-May/031507.html Proposed Vulkan patch: https://github.com/kleinerm/pal/commit/a25d4802074b13a8d5f7edc96ae45469ecbac3c4 - Add a new GEM flag which is only used internally in the kernel driver. Userspace is not allowed to set it. drm: - 16bpc fixed point format fourcc Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-01drm/amdgpu: Add vbios info ioctl interfaceJiawei Gu1-6/+11
Add AMDGPU_INFO_VBIOS_INFO subquery id for detailed vbios info. Provides a way for the user application to get the VBIOS information without having to parse the binary. It is useful for the user to be able to display in a simple way the VBIOS version in their system if they happen to encounter an issue. V2: Use numeric serial. Parse and expose vbios version string. V3: Remove redundant data in drm_amdgpu_info_vbios struct. V4: 64 bit alignment in drm_amdgpu_info_vbios. v5: squash together all the reverts, etc. (Alex) Signed-off-by: Jiawei Gu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-01drm/amdgpu: support atcs method powershift (v4)Sathishkumar S1-0/+18
add support to handle ATCS method for power shift control. used to communicate dGPU device state to SBIOS. V2: use defined acpi func for checking psc support (Lijo) fix alignment (Shashank) V3: rebased on unified ATCS handling (Alex) V4: rebased on ATPX/ATCS structures global (Alex) Signed-off-by: Sathishkumar S <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-22Merge drm/drm-next into drm-misc-nextThomas Zimmermann10-0/+46501
Backmerging from drm/drm-next to the patches for AMD devices for v5.14. Signed-off-by: Thomas Zimmermann <[email protected]>
2021-05-21drm/amd/include/aldebaran_ip_offset: Mark top-level IP_BASE as __maybe_unusedLee Jones1-1/+1
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../include/aldebaran_ip_offset.h:259:29: warning: ‘XGMI2_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/aldebaran_ip_offset.h:252:29: warning: ‘XGMI1_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/aldebaran_ip_offset.h:245:29: warning: ‘XGMI0_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/aldebaran_ip_offset.h:238:29: warning: ‘WAFL1_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/aldebaran_ip_offset.h:231:29: warning: ‘WAFL0_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/aldebaran_ip_offset.h:161:29: warning: ‘PCIE0_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/aldebaran_ip_offset.h:119:29: warning: ‘L2IMU0_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/aldebaran_ip_offset.h:112:29: warning: ‘L1IMUPCIE0_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/aldebaran_ip_offset.h:105:29: warning: ‘L1IMUIOAGR0_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/aldebaran_ip_offset.h:98:29: warning: ‘IOHC0_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/aldebaran_ip_offset.h:91:29: warning: ‘IOAPIC0_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/aldebaran_ip_offset.h:84:29: warning: ‘IOAGR0_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/aldebaran_ip_offset.h:63:29: warning: ‘FUSE_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/aldebaran_ip_offset.h:49:29: warning: ‘DBGU_IO0_BASE’ defined but not used [-Wunused-const-variable=] drivers/gpu/drm/amd/amdgpu/../include/aldebaran_ip_offset.h:42:29: warning: ‘CLK_BASE’ defined but not used [-Wunused-const-variable=] Cc: Alex Deucher <[email protected]> Cc: "Christian König" <[email protected]> Cc: David Airlie <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Hawking Zhang <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Lee Jones <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-21drm/amdgpu/pm: Update metrics table (v2)David M Nieto1-0/+69
v2: removed static dpm and frequency ranges from table expand metrics table with voltages and frequency ranges Signed-off-by: David M Nieto <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: Add early fini callbackAndrey Grodzovsky1-0/+2
Use it to call disply code dependent on device->drv_data before it's set to NULL on device unplug v5: Move HW finilization into this callback to prevent MMIO accesses post cpi remove. v7: Split kfd suspend from device exit to expdite HW related stuff to amdgpu_pci_remove v8: Squash previous KFD commit into this commit to avoid compile break. Signed-off-by: Andrey Grodzovsky <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-05-19drm/amdgpu: Query correct register for DF hashing on AldebaranMukul Joshi1-0/+3
For Aldebaran, driver needs to query DramMegaBaseAddress to check if DF hashing is enabled. Signed-off-by: Mukul Joshi <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Edit license info for beige goby DC filesAurabindo Pillai4-37/+18
[How] * Add MIT license to all new files as SPDX tag. * Fix copyright year Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Add register definitions for Beige GobyAurabindo Pillai4-0/+45172
[Why&How] Adds registers definitions required for Beige Goby initial support. Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Chris Park <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/amdgpu: initialize IP offset for beige_gobyChengming Gui1-0/+1274
Add ip offset definition for beige_goby and initialize it v2: squash in fixes (Alex) V3: fix permissions on file (Alex) Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: add helper function to query dynamic boot config capHawking Zhang1-0/+1
Check firmware flags to determine whether dynmaic boot config is supported or not. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amdgpu: add judgement when add ip blocks (v2)Likun GAO1-0/+6
Judgement whether to add an sw ip according to the harvest info. v2: fix indentation (Alex) Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19gpu: drm: replace occurrences of invalid characterMauro Carvalho Chehab1-5/+5
There are some places at drm that ended receiving a REPLACEMENT CHARACTER U+fffd ('�'), probably because of some bad charset conversion. Fix them by using what it seems to be the proper character. Acked-by: Randy Dunlap <[email protected]> Signed-off-by: Mauro Carvalho Chehab <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/e606930c73029f16673849c57acac061dd923866.1621412009.git.mchehab+huawei@kernel.org
2021-05-10drm/amdgpu: Enable TCP channel hashing for AldebaranMukul Joshi1-0/+1
Enable TCP channel hashing to match DF hash settings for Aldebaran. Signed-off-by: Mukul Joshi <[email protected]> Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Joseph Greathouse <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-10drm/amd/pm: new gpu_metrics structure for pmfw attached timestampEvan Quan1-0/+62
Supported by some latest ASICs. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-10drm/amd/pm: Add interface to get FW private bufferLijo Lazar1-0/+1
v1: Add new interface to get FW private buffer details v2: Drop domain check v3: Use amdgpu_bo_kmap to get cpu address Signed-off-by: Lijo Lazar <[email protected]> Suggested-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-20drm/amdgpu: only harvest gcea/mmea error status in arcturusHawking Zhang1-0/+16
SDP RdRspStatus/WrRspStatus or first parity error on RdRsp data can cause system fatal error in arcturus. GPU will be freezed in such case. Driver needs to harvest these error information before reset the GPU. Check error type to avoid harvest normal gcea/mmea information. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Stanley Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-15drm/amd: update the atomfirmware header for smu12Xiaojian Du1-0/+41
This patch is to update the atomfirmware header for smu12. v2: remove some unnecessary members Signed-off-by: Xiaojian Du <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amdgpu: add DMUB outbox event IRQ source define/complete/debug flagJude Shih1-0/+2
[Why & How] We use outbox interrupt that allows us to do the AUX via DMUB Therefore, we need to add some irq source related definition in the header files; Signed-off-by: Jude Shih <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: Interface for LTTPR interopWesley Chalmers1-0/+1
[WHY] The logic to toggle LTTPR transparent/non-transparent requires 2 flags provided by BIOS [HOW] Repurpose the interface to get dce caps so both LTTPR querying functions can use them. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: BIOS LTTPR Caps InterfaceWesley Chalmers1-1/+36
[WHY] Some platforms will have LTTPR capabilities forced on by VBIOS flags; the functions added here will access those flags. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Dan Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/amdgpu: Add CP_IB1_BASE_* to gc_10_3_0 headersTom St Denis2-0/+15
Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd: Fix a typo in two different sentencesBhaskar Chowdhury1-2/+2
s/defintion/definition/ .....two different places. Acked-by: Randy Dunlap <[email protected]> Signed-off-by: Bhaskar Chowdhury <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/pm: make DAL communicate with SMU through unified interfacesEvan Quan1-0/+14
No need to have special handlings for swSMU supported ASICs. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/pm: add a new sysfs entry for default power limitEric Huang1-1/+2
Driver doesn't keep the default bootup power limit and expose it to user. As requested we add it in driver. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: update umc_info v3_3 structure for ECCHawking Zhang1-1/+12
new member introduced in umc_info v3_3 to indicate ECC capability Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/pm: add new data in metrics tableKenneth Feng1-0/+7
Export new data in the metrics table for gfx and memory utilization counter, and each hbm temperature as well. v2: change the metrics table version to v1.1 v3: fix the coding style v4: rebase against latest kernel Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdkfd: Check HIQ's MQD for queue preemption statusOak Zeng1-16/+16
MEC firmware can silently fail the queue preemption request without time out. In this case, HIQ's MQD's queue_doorbell_id will be set. Check this field to see whether last queue preemption was successful or not. Signed-off-by: Oak Zeng <[email protected]> Suggested-by: Jay Cornwall <[email protected]> Acked-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/pm: Enable performance determinism on aldebaranLijo Lazar1-0/+1
Performance Determinism is a new mode in Aldebaran where PMFW tries to maintain sustained performance level. It can be enabled on a per-die basis on aldebaran. To guarantee that it remains within the power cap, a max GFX frequency needs to be specified in this mode. A new power_dpm_force_performance_level, "perf_determinism", is defined to enable this mode in amdgpu. The max frequency (in MHz) can be specified through pp_dpm_sclk. The mode will be disabled once any other performance level is chosen. Ex: To enable perf determinism at 900Mhz max gfx clock echo perf_determinism > /sys/bus/pci/devices/.../power_dpm_force_performance_level echo max 900 > /sys/bus/pci/devices/.../pp_dpm_sclk Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdpgu: add ATOM_DGPU_VRAM_TYPE_HBM2E vram typeFeifei Xu1-0/+1
0x61 is assigned to HBM2E in atom_dgpu_vram_type. Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: query aldebaran gfx_config through atomfirmware i/fHawking Zhang1-0/+41
For ASICs that don't support ip discovery feature, query gfx configuration through atomfirmware interface, rather than gpu_info firmware. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amd/pm: Add atom_smc_dpm_info_v4_10 for aldebaranLijo Lazar1-0/+53
Add atom_smc_dpm_info_v4_10 that defines board parameters for aldebaran Signed-off-by: Lijo Lazar <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: update atom_firmware_info_v3_4 (v2)Feifei Xu1-1/+4
v1: Added some pspbl parameters v2: fix fallthrough issue Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Lazar Lijo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: support get_vram_info atomfirmware i/f for aldebaranHawking Zhang1-0/+16
Query vram_type, channel_num, channel_width information through atomfirmware i/f Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: Fix IH client ID naming tableOak Zeng1-0/+1
Client ID 26 is reserved. Add it to the table. Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-23drm/amdgpu: Print the IH client ID name when vm fault happensYong Zhao1-2/+6
This gives more information and improves productivity. Signed-off-by: Yong Zhao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-10drm/amd/include: add ip offset header for aldebaran (v5)Hawking Zhang1-0/+1738
v1: re-use arct ip base offset array for aldebaran (Le) v2: create aldebaran ip base offset array for major ip blocks (Hawking) v3: re-use arct VCN ip base offset array for aldebaran (James) v4: correct MP1 ip base offset array (Hawking) v5: update VCN ip base offset array to aldebaran one (Hawking) Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Le Ma <[email protected]> Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-10drm/amdgpu: add vcn v2_6_0 ip headers (v3)Hawking Zhang2-0/+5997
v1: Add vcn v2_6_0 register offset and shift masks in header files (Hawking) v2: Clean up vcn v2_6_0 registers (Alex) v3: update registers (Alex) Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-10drm/amdgpu: add umc v6_7_0 ip headers (v3)Hawking Zhang2-0/+13416
v1: Add umc v6_7_0 register offset and shift masks in header files (Hawking) v2: Clean up registers (Alex) v3: update registers (Alex) Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-10drm/amdgpu: add thm v13_0_2 ip headers (v3)Hawking Zhang2-0/+1643
v1: Add thm v13_0_2 register offset and shift masks in header files (Hawking) v2: Clean up thm v13_0_2 registers (Alex) v3: update registers (Alex) Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-10drm/amdgpu: add sdma v4_4_0 ip headers (v2)Hawking Zhang2-0/+19146
Add sdma v4_4_0 register offset and shift masks in header files v2: update registers (Alex) Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-10drm/amdgpu: add smuio v13_0_2 ip headers (v3)Hawking Zhang2-0/+1679
v1: Add smuio v13_0_2 register offset and shift masks in header files (Hawking) v2: Clean up smuio v13_0_2 registers (Alex) v3: update registers (Alex) Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-10drm/amdgpu: add mp v13_0_2 ip headers (v3)Hawking Zhang2-0/+892
v1: Add mp v13_0_2 register offset and shift masks in header files (Hawking) v2: Clean up mp v13_0_2 registers (Alex) v3: update registers (Alex) Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-10drm/amdgpu: add mmhub v1_7 ip headers (v3)Hawking Zhang2-0/+37303
v1: Add mmhub v1_7 register offset and shift masks in header files (Hawking) v2: Clean up mmhub v1_7 registers (Alex) v3: Update registers (Alex) Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-10drm/amdgpu: add gc v9_4_2 ip headers (v3)Hawking Zhang2-0/+40632
v1: Add gc v9_4_2 register offset and shift masks in header files (Hawking) v2: Clean up gc v9_4_2 registers (Alex) v3: update registers (Alex) Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-05drm/amd/amdgpu: Add missing BASE_IDX to dcn registerTom St Denis1-1/+1
The register mmOTG1_OTG_BLANK_CONTROL was missing BASE_IDX value. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-05drm/amdgpu: add DMUB trace event IRQ source defineLeo (Hanghong) Ma1-0/+2
[Why & How] We use DMCUB outbox0 interrupt to log DMCUB trace buffer events as Linux kernel traces, so need to add some irq source related defination in the header files; Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Leo (Hanghong) Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-05drm/amd/pm: correct gpu metrics related data structures V3Evan Quan1-0/+112
To make sure they are naturally aligned. Also updating the data type for link_speed/width for future PCIE5 support. V2: define new structures with minor version bumped V3: update data type of energy_accumulator as 64bit and drop unnecessary padding members Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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