aboutsummaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd/include
AgeCommit message (Collapse)AuthorFilesLines
2019-07-31drm/amd/powerplay: add new sensor type for VCN powergate statusEvan Quan1-0/+1
VCN is widely used in new ASICs and different from tranditional UVD and VCE. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-11drm/amd/powerplay: increase the SMU msg response waiting timeEvan Quan1-1/+1
This is expected to fix some mode1 reset failures. And this affects SMU part only as the timeout setting for other parts is controlled by a different macro. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-25drm/amd/powerplay: make athub pg bit configured by pg_flagsHuang Rui1-1/+2
The athub pg features enabling should be indicated by pg_flags. Reported-by: Lijo Lazar <[email protected]> Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display: Create DWB resource for DCN2Charlene Liu2-0/+20
[Description] dcn20 has num_dwb =1 in the res cap, but not created. Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Duke Du <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/mes10.1: add ip block mes10.1 (v2)Jack Xiao1-1/+2
MES takes over the scheduling capability of GFX and SDMA, add MES as a standalone ip. v2: squash in updates (Alex) Acked-by: Hawking Zhang <[email protected]> Signed-off-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/discovery: update definition for struct die_headerXiaojie Yuan1-2/+2
Update to latest spec. Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/discovery: add harvest info data tableXiaojie Yuan1-1/+17
Add support for the harvest tables. Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/discovery: update definitions of table_info and binary_headerXiaojie Yuan1-0/+4
Use the proper definitions. Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amdgpu/discovery: add ip discovery initial supportXiaojie Yuan1-0/+145
The IP discovery table lists is populated by the psp at power on and includes all of the hw details on the board: - List of IPs and MMIO offsets - IP harvest details - IP configuration details v2: prefix struct and function names with 'amdgpu' v3: read table binary from vram using mmMM_INDEX and mmMM_DATA update TABLE_BINARY_MAX_SIZE to 64kb (1 TMR) add 'instance_number' field per ip info consider endianness and replace uint8/16/32_t with u8/16/32 initialize register base addresses initialize adev->gfx.config and adev->gfx.cu_info to replace gpu info fw get major and minor version using a single api don't expose internal data structures in amdgpu_discovery.h v4: RCC_CONFIG_MEMSIZE is in MB units hold mmio_idx_lock while reading ip discovery binary v5: pick out discovery.h as a cross-OS header do structure pointer cast directly consider endianness while using the member of structure convert base addresses to dword at boot up, PSP BL copies ip discovery binary from VBIOS(SPIROM) image to the top of the frame buffer (just below the reserved regions for PSP & SMU). ip discovery data table includes the collection of each ip's identification number, base addresses, version number, and harvest setting placeholder. gc data table includes gfx info structure. Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amd/display: move dcn v1_0 irq source header to ivsrcid/dcn/Hawking Zhang1-0/+0
interrupt source packet definitions for the display block (DCN). Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add irq sources for vcn v2_0 (v2)Hawking Zhang1-0/+32
Add the interrupt source packet definitions. v2: update (Alex) Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add irq sources for sdma v5_0Hawking Zhang2-0/+87
Add the interrupt source packet definitions. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add irq sources for gfx v10_1Hawking Zhang1-0/+53
Add the interrupt source packet definitions. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu/athub2: enable athub2 clock gatingJack Xiao1-0/+2
Enable athub2 clock gating and light sleep Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add flag to support IH clock gatingHawking Zhang1-0/+1
Add new flag for IH (interrupt handler) clockgating. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add new HDP CG flagsHawking Zhang1-0/+2
HDP 5.0 supports SRAM power gating. all the LS (Light Sleep)/ DS (Deep Sleep)/SD (Shut Down) modes are supported. However, only one of these modes can be enabled at one time. There is no dynamic power mode switch support. clock/power gating has to be disabled before making any power mode change. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add v10 structs header (v2)Huang Rui1-0/+1258
Header for CP structures (MQD, etc.) V2: squash in updates Signed-off-by: Huang Rui <[email protected]> Acked-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add navi10 ip offset headerHawking Zhang2-1/+858
Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: atomfirmware.h updates for navi10Hawking Zhang1-8/+180
Updated tables for Navi10. Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add navi10 enums headerHawking Zhang1-0/+22764
Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add SMUIO 11.0 register headersHawking Zhang2-0/+1012
Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add OSS 5.0 register headersHawking Zhang2-0/+1658
Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add MMHUB 2.0 register headersHawking Zhang3-0/+10293
Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add GC 10.1 register headers (v4)Hawking Zhang3-0/+61330
v2: Update regs (Alex) v3: More updates (Alex) v4: more updates (Alex) Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add VCN 2.0 register headersHawking Zhang2-0/+4823
Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add NBIO 2.3 register headersHawking Zhang3-0/+153523
Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add MP 11.0 register headersHawking Zhang1-0/+429
Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add HDP 5.0 register headersHawking Zhang2-0/+876
Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add DCN 2.0 register headersHawking Zhang2-0/+85539
Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add CLK 11.0 register headersHawking Zhang2-0/+71
Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amdgpu: add ATHUB 2.0 register headersHawking Zhang3-0/+3050
Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-05-24drm/amdkfd: Shift sdma_engine_id and sdma_queue_id in mqdOak Zeng3-6/+3
FW of some new ASICs requires sdma mqd size to be not more than 128 dwords. Repurpose the last 2 reserved fields of sdma mqd for driver internal use, so the total mqd size is no bigger than 128 dwords Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-05-24drm/amdgpu: add df perfmon regs and funcs for xgmiJonathan Kim1-0/+18
v6: Squash in warning fix (Colin Ian King) v5: Fix warnings (Alex) v4: fixed mixed delaration and code warnings and minor errors v3: exposing df funcs in amdgpu_df_funcs in amdgpu.h v2: moving permonctl/perfmonctr from default to offset - adding df perfmonctl and perfmonctr registers for df counters - adding df funcs to set perfmonctl and get perfmonctr for df and xgmi counters - exposing df funcs in amdgpu_df_funcs Signed-off-by: Jonathan Kim <[email protected]> Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-05-24drm/amdgpu: add EDC counter registerJames Zhu1-0/+31
Add EDC counter register to support gfx9 gpr EDC workaround to clear all EDC counters. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-05-24drm/amdgpu: Add replay counter defines to NBIO headersKent Russell3-0/+9
Add the PCIE_RX_NUM_NACK and PCIE_RX_NUM_NACK_GENERATED values to the NBIO SMN headers in preparation for exposing the number of PCIe replays via sysfs Signed-off-by: Kent Russell <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-05-24drm/amd/powerplay: expose Vega20 realtime memory utilizationEvan Quan1-0/+1
Enable realtime memory utilization report on Vega20. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-05-24drm/amdkfd: Expose HDP registers to user spaceOak Zeng1-0/+1
Introduce a new memory type (KFD_IOC_ALLOC_MEM_FLAGS_MMIO_REMAP) and expose mmio page of HDP registers to user space through this new memory type. v2: moved remapped hdp regs to adev struct v3: rename the new memory type to ALLOC_MEM_FLAGS_MMIO_REMAP v4: use more generic function name v5: Fail remapped mmio allocation for asics before gfx9 Signed-off-by: Oak Zeng <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-05-24drm/amd/powerplay: support hwmon temperature channel labels V2Evan Quan1-0/+7
Expose temp[1-3]_label hwmon interfaces. While temp2_label and temp3_label are visible for SOC15 dGPUs only. - V2: correct temp1_label as "edge" Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-05-24drm/amd/powerplay: expose current hotspot and memory temperatures V2Evan Quan1-0/+3
Two new hwmon interfaces(temp2_input and temp3_input) are added. They are supported on SOC15 dGPUs only. - V2: correct thermal sensor output Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-04-23drm/amd/include: Add HUBPREQ_DEBUG register offsetsLeo Li1-0/+8
They will be used by DC when runing ASIC-specific HUBP initialization. Signed-off-by: Leo Li <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-04-19drm/amd/include: Add USB_C_TYPE to atom_encoder_cap_defsLeo Li1-0/+1
This is needed by DC to support EDID emulation on USB-C ports. CC: Samson Tam <[email protected]> CC: Harry Wentland <[email protected]> CC: Alex Deucher <[email protected]> Signed-off-by: Leo Li <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-04-19drm/amdgpu: get_fw_version isn't ASIC specificAmber Lin1-16/+0
Method of getting firmware version is the same across ASICs, so remove them from ASIC-specific files and create one in amdgpu_amdkfd.c. This new created get_fw_version simply reads fw_version from adev->gfx than parsing the ucode header. Signed-off-by: Amber Lin <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: remove chashChristian König1-366/+0
Remove the chash implementation for now since it isn't used any more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: update atomfirmware header with ecc related membersHawking Zhang1-0/+53
add new umc_info structures and new firmware_capability defines Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amd/amdgpu: Add ENGINE_CNTL register to vcn10 headersTom St Denis2-0/+7
Signed-off-by: Tom St Denis <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amd/powerplay: add enable_umd_pstate functions for SMU11Chengming Gui1-0/+3
add enable_umd_pstate to support sys interface for SMU11. Signed-off-by: Chengming Gui <[email protected]> Reviewed-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amdgpu: update atomfirmware header for smu11Huang Rui1-7/+37
This patch updates atomfirmware header on smu11 for future use. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-18drm/amdkfd: Optimize out sdma doorbell array in kgd2kfd_shared_resourcesYong Zhao1-2/+2
We can directly calculate sdma doorbell indexes in the process doorbell pages through the doorbell_index structure in amdgpu_device, so no need to cache them in kgd2kfd_shared_resources any more. This alleviates the adaptation needs when new SDMA configurations are introduced. Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-18drm/amdkfd: Fix bugs regarding CP queue doorbell mask on SOC15Yong Zhao1-9/+6
Reserved doorbells for SDMA IH and VCN were not properly masked out when allocating doorbells for CP user queues. This patch fixed that. Signed-off-by: Yong Zhao <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-25drm/amd/powerplay: support retrieving and adjusting dcefclock power levels V2Evan Quan1-0/+1
User can use "pp_dpm_dcefclk" to retrieve and adjust dcefclock power levels. V2: expose this interface for Vega10 and later ASICs only Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.