aboutsummaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd/display
AgeCommit message (Collapse)AuthorFilesLines
2024-06-14drm/amd/display: Add null check to dml21_find_dc_pipes_for_planeDillon Varone1-3/+8
When a phantom stream is in the process of being deconstructed, there could be pipes with no associated planes. In that case, ignore the phantom stream entirely when searching for associated pipes. Cc: [email protected] Reviewed-by: Alvin Lee <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Attempt to avoid empty TUs when endpoint is DPIAMichael Strauss3-1/+75
[WHY] Empty SST TUs are illegal to transmit over a USB4 DP tunnel. Current policy is to configure stream encoder to pack 2 pixels per pclk even when ODM combine is not in use, allowing seamless dynamic ODM reconfiguration. However, in extreme edge cases where average pixel count per TU is less than 2, this can lead to unexpected empty TU generation during compliance testing. For example, VIC 1 with a 1xHBR3 link configuration will average 1.98 pix/TU. [HOW] Calculate average pixel count per TU, and block 2 pixels per clock if endpoint is a DPIA tunnel and pixel clock is low enough that we will never require 2:1 ODM combine. Cc: [email protected] # 6.6+ Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Michael Strauss <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Refactor DCN3X into component folderMounika Adhuri44-61/+304
[why] Move DCN3X files to unique component folder. [how] Create respective component folder in dc, move the DCN3X files into corresponding new folders and made appropriate changes for compilation in Makefiles. Reviewed-by: Martin Leung <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Mounika Adhuri <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: On clock init, maintain DISPCLK freqChris Park2-1/+27
[Why] On init if a display is connected, we need to maintain the DISPCLK frequency Even though DPG_EN=1, the display still requires the correct timing or it could cause audio corruption (if DISPCLK freq is reduced). [How] Read the current DISPCLK freq and request the same value to ensure the timing is valid and unchanged. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Chris Park <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: fix minor coding errors where dml21 phase 5 uses wrong ↵Wenjing Liu1-2/+2
variables There is a coding error which causes incorrect variables to be assigned in DML21 phase 5. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Remove redundant condition in VBA 314 funcIvan Lipski1-9/+0
[WHY] Coverity analysis this conditional code as DEADCODE. The conditional statement is never true since 'MacroTileSizeBytes' is either 256 or 65536. Thus, the code inside is the conditional statement is never reached. [HOW] Removed the conditional statement. Reviewed-by: Aurabindo Pillai <[email protected]> Reviewed-by: Alex Hung <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Remove redundant condition with DEADCODEIvan Lipski1-3/+0
[WHY] Coverity analysis flagged this condition as DEADCODE since the variable 'req128_c' is always false, thus the condition is never true. [HOW] Remove the condition. Reviewed-by: Aurabindo Pillai <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14Revert "drm/amd/display: workaround for oled eDP not lighting up on DCN401"Joshua Aberback3-5/+0
This reverts commit e902dd7f3e3b93a401e1d3c0322cce933e75e809. A proper fix for this issue has been implemented in DMUB FW. So, no need to keep the workaround. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Joshua Aberback <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Add dcn401 DIG fifo enable/disableRelja Vojvodic3-3/+11
[Why] Found while hotplugging MST daisy chain displays. Changing dispclk during this sequence caused SMU hang due to DIG fifo not being disabled correctly (caused by missing functions). [How] Adding disable/enable DIG fifo functions for dcn401 Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Relja Vojvodic <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Enable DCN401 idle optimizations by defaultDillon Varone1-1/+0
[WHY&HOW] Re-enable idle optimizations by default. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: DCN401 full power down in HW init if any link enabledJoshua Aberback2-1/+1
[Why] During HW init, certain operations the driver performs are invalid on enabled hardware in an unknown state (for example, setting all clock values to minimum when the GPU is actively driving a display). There is already code present to call HWSS->power_down during init when any link is enabled in HW, but that function pointer is unpopulated for most asics. We want to enable this codepath for DCN401, as it resolves the issue with being unable to drive certain display configs on adapter re-enable, and we can restore boot optimizations. [How] - add power_down HWSS function for DCN401 - remove debug bit to disable boot optimizations for DCN401 Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Hamza Mahfooz <[email protected]> Signed-off-by: Joshua Aberback <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Disable PHYSYMCLK RCODaniel Miess2-2/+2
[Why] PHYSYMCLK RCO has been found to lead to crashes in some corner cases [How] Disable PHYSYMCLK RCO debug bit Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Daniel Miess <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: [FW Promotion] Release 0.0.221.0Anthony Koo1-1/+60
- Create a general command and fix Replay desync error with general cmd Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Anthony Koo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: 3.2.288Aric Cyr1-1/+1
* FW Release 0.0.221.0 * Fixed missing targets in FAMS2 * Populate hardware_release hook for dcn401 * Disable DMCUB timeout for DCN35 * Move PRIMARY plane zpos higher * Introduce overlay cursor mode * Change dram_clock_latency for dcn35 and dcn351 * DCN401 cursor code update Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Update idle hardmins if uclk or fclk requirement changedDillon Varone1-1/+1
[WHY&HOW] Update the idle hardmin with SMU if either clock changed. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Avoid overflow from uint32_t to uint8_tAlex Hung2-2/+2
[WHAT & HOW] dmub_rb_cmd's ramping_boundary has size of uint8_t and it is assigned 0xFFFF. Fix it by changing it to uint8_t with value of 0xFF. This fixes 2 INTEGER_OVERFLOW issues reported by Coverity. Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Do not override dml2.1 reinitDillon Varone1-3/+4
[WHY&HOW] Reinit should return after completing version 2.1 reinit instead of calling version 2 reinit after. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Fix missed targets in FAMS2+HWFQDillon Varone2-1/+2
[WHY&HOW] Add additional delay factor when considering a safe time to flip for HWFQ to be passed in by the driver. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Add null check for phantom pipes in prepare mcacheDillon Varone1-2/+8
[WHY&HOW] Sometimes this function is called with a partially deconstructed phantom stream toplolgy, and should ignore phantoms with no plane state. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Block SubVP if hardware rotation is used in DML2.1Dillon Varone1-1/+2
[WHY&HOW] SubVP is not supported when hardware rotation is in use. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Explicitly cast v_total to signed in a subtractionAlex Hung1-2/+2
[WHY & HOW] v_total is an uint32_t and subtracting an unsigned to a signed will result in an unsigned which is always >= 0. As a result, the ternary conditions are always true and thus has no effect. This is fixed by casting v_total to signed explicitly. This also avoids v_total subtraction to overflow. This fixes 1 NO_EFFECT, 2 DEADCODE and 2 INTEGER_OVERFLOW issues reported by Coverity. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Remove NO_EFFECT self-assignmentAlex Hung2-8/+0
[WHAT & HOW] The self-assignments have no effects and thus are removed. Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Remove reduntant comparisons by CoverityIvan Lipski2-6/+6
[WHY] Coverity analysis of the Upstream display driver code (amd-staging-drm-next) flagged these three functions as containing 'CONSTANT_EXPRESSION_RESULT' errors, i. e. the conditionals are reduntant since their result is predetermined. fixpt31_32.c: The two flagged 'ASSERT' lines redundant since they are always true: - LONG_MAX equals to the largest 'signed long long' number - res.value is type 'signed long long', So, the condition inside the 'ASSERTS's is always link_dp_training.c: The flagged conditional statement is always false: - 'max_requested.FFE_PRESET.settings.level' is 4 bits, so its max possible value is 15 - 'DP_FFE_PRESET_MAX_LEVEL' equals to 15. So, the conditional statement is always false and the wrapped code never executes. [HOW] Removed lines flagged by Coverity analysis. Reviewed-by: Sun peng Li <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: populate hardware_release hook for dcn401Alvin Lee3-2/+22
[Description] hardare_release() is called when driver is removed. Add the missing hook for DCN401 Reviewed-by: Dillon Varone <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: make ODM segment width of YCbCr422 two pixel alignedWenjing Liu1-4/+11
[why] In YCbCr422 format hardware shares 1 set of chromas CbCr with 2 sets of lumas Y. Therefore each ODM segment needs to be two pixel aligned. The commit adds this missing hardwware requirement into ODM segment width decision logic. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Disable IPS when it is not allowed.JinZe.Xu2-0/+3
[Why&How] Add flag to disable IPS when it is not allowed. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: JinZe.Xu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14Revert "drm/amd/display: Handle HPD_IRQ for internal link"Sung-huai Wang1-15/+9
[How&Why] This reverts commit 239b31bd5c3fef3698440bf6436b2068c6bb08a3. Due to the it effects Replay resync. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Sung-huai Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Remove useless comparison of unsigned int vs. 0Alex Hung8-25/+20
[WHY & HOW] The comparisons of unsigned int with 0 can have no meanings, i.e. unsigned int >= 0 (always true) or unsigned int < 0 (always false), and therefore they are removed. This fixes 12 NO_EFFECT issues reported by Coverity. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Fix uninitialized variables in dcn401Alex Hung1-1/+1
This fixes an UNINIT issue reported by Coverity. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Fix incorrect size calculation for loop in dcn401Alex Hung1-1/+1
[WHY] fe_clk_en and be_clk_sel have size of 4 but sizeof(fe_clk_en) has byte size 16 which is lager than the array size. [HOW] Use ARRAY_SIZE for calculating size. This fixes 2 OVERRUN issues reported by Coverity. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Minor cleanup for DCN401 cursor related codeSridevi Arvindekar2-2/+10
Move pipe_ctx variables to start of the function and add a helpful comment Co-authored-by: Sridevi Arvindekar <[email protected]> Reviewed-by: Ilya Bakoulin <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Sridevi Arvindekar <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Check otg_master pointer before use itRodrigo Siqueira1-7/+15
Coverity highlighted that the parameter otg_master is referenced before the if condition that validates it, which means that the code might have some attempt to access a null pointer. This commit addresses this issue by moving the pointer verification to the beginning of the function and initializing all the values right after it. Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Disable DMCUB timeout for DCN35Nicholas Kazlauskas1-0/+1
[Why] DMCUB can intermittently take longer than expected to process commands. Old ASIC policy was to continue while logging a diagnostic error - which works fine for ASIC without IPS, but with IPS this could lead to a race condition where we attempt to access DCN state while it's inaccessible, leading to a system hang when the NIU port is not disabled or register accesses that timeout and the display configuration in an undefined state. [How] We need to investigate why these accesses take longer than expected, but for now we should disable the timeout on DCN35 to avoid this race condition. Since the waits happen only at lower interrupt levels the risk of taking too long at higher IRQ and causing a system watchdog timeout are minimal. Reviewed-by: Ovidiu Bunea <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: use preferred link settings for dp signal onlyWenjing Liu1-14/+10
[why] We set preferred link settings for virtual signal. However we don't support virtual signal for UHBR link rate. If preferred is set to UHBR link rate, we will allow virtual signal with UHBR link rate which causes system crashes. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: remove ODM combine before bandwidth validationWenjing Liu1-0/+2
[why] DML1 validation code doesn't have the ability to remove ODM combine. It will directly translate currently used ODM combine config into ODM override. If ODM combine is used in the initial state it will only validate the timing if ODM is used. This is not correct for dynamic ODM u se case, as ODM is used as an optimization not a hard requirement. [how] Remove ODM combine in the initial state before bandwidth validation so DML will not translate it into ODM override in the initial bandwidth validation. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: remove dpp pipes on failure to update pipe paramsWenjing Liu1-1/+8
[why] There are cases where update pipe params could fail but dpp pipes are already added to the state. In this case, we should remove dpp pipes so dc state is restored back. If it is not restored, dc state is corrupted after calling this function, so if we call the same interface with the corrupted state again, we may end up programming pipe topology based on a corrupted dc state. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Remove register from DCN35 DMCUB diagnostic collectionNicholas Kazlauskas1-4/+1
[Why] These registers should not be read from driver and triggering the security violation when DMCUB work times out and diagnostics are collected blocks Z8 entry. [How] Remove the register read from DCN35. Reviewed-by: Duncan Ma <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Move PRIMARY plane zpos higherLeo Li2-8/+44
[Why] Compositors have different ways of assigning surfaces to DRM planes for render offloading. It may decide between various strategies: overlay, underlay, or a mix of both (see here for more info: https://gitlab.freedesktop.org/emersion/libliftoff/-/issues/76) One way for compositors to implement the underlay strategy is to assign a higher zpos to the DRM_PRIMARY plane than the DRM_OVERLAY planes, effectively turning the DRM_OVERLAY plane into an underlay plane. Today, amdgpu attaches an immutable zpos of 0 to the DRM_PRIMARY plane. This however, is an arbitrary restriction. DCN pipes are general purpose, and can be arranged in any z-order. To support compositors using this allocation scheme, we can set a non-zero immutable zpos for the PRIMARY, allowing the placement of OVERLAYS (mutable zpos range 0-254) beneath the PRIMARY. [How] Assign a zpos = #no of OVERLAY planes to the PRIMARY plane. Then, clean up any assumptions in the driver of PRIMARY plane having the lowest zpos. v2: Fix typo s/decending/descending/ Reviewed-by: Harry Wentland <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Leo Li <[email protected]> Acked-by: Pekka Paalanen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Introduce overlay cursor modeLeo Li4-122/+389
[Why] DCN is the display hardware for amdgpu. DRM planes are backed by DCN hardware pipes, which carry pixel data from one end (memory), to the other (output encoder). Each DCN pipe has the ability to blend in a cursor early on in the pipeline. In other words, there are no dedicated cursor planes in DCN, which makes cursor behavior somewhat unintuitive for compositors. For example, if the cursor is in RGB format, but the top-most DRM plane is in YUV format, DCN will not be able to blend them. Because of this, amdgpu_dm rejects all configurations where a cursor needs to be enabled on top of a YUV formatted plane. From a compositor's perspective, when computing an allocation for hardware plane offloading, this cursor-on-yuv configuration result in an atomic test failure. Since the failure reason is not obvious at all, compositors will likely fall back to full rendering, which is not ideal. Instead, amdgpu_dm can try to accommodate the cursor-on-yuv configuration by opportunistically reserving a separate DCN pipe just for the cursor. We can refer to this as "overlay cursor mode". It is contrasted with "native cursor mode", where the native DCN per-pipe cursor is used. [How] On each crtc, compute whether the cursor plane should be enabled in overlay mode. If it is, mark the CRTC as requesting overlay cursor mode. Overlay cursor should be enabled whenever there exists a underlying plane that has YUV format, or is scaled differently than the cursor. It should also be enabled if there is no underlying plane, or if underlying planes do not cover the entire CRTC. During DC validation, attempt to enable a separate DCN pipe for the cursor if it's in overlay mode. If that fails, or if no overlay mode is requested, then fallback to native mode. v2: * Update commit message for when overlay cursor should be enabled * Also consider scale and no-underlying-plane case (cursor on crtc bg) * Consider all underlying planes when determinig overlay/native, not just the plane immediately beneath the cursor, as it may not cover the entire CRTC. * Fix typo s/decending/descending/ * Force native cursor on pre-DCN hardware Reviewed-by: Harry Wentland <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Leo Li <[email protected]> Acked-by: Harry Wentland <[email protected]> Acked-by: Pekka Paalanen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: define abm debug interfaceJosip Pavic1-0/+60
[Why & How] Define debug interface to dmub for reading back abm data. Reviewed-by: Anthony Koo <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Josip Pavic <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Refactor function dm_dp_mst_is_port_support_mode()Wayne Lin1-86/+146
[Why] dm_dp_mst_is_port_support_mode() is a bit not following the original design rule and cause light up issue with multiple 4k monitors after mst dsc hub. [How] Refactor function dm_dp_mst_is_port_support_mode() a bit to solve the light up issue. Reviewed-by: Jerry Zuo <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Don't refer to dc_sink in is_dsc_need_re_computeWayne Lin1-8/+4
[Why] When unplug one of monitors connected after mst hub, encounter null pointer dereference. It's due to dc_sink get released immediately in early_unregister() or detect_ctx(). When commit new state which directly referring to info stored in dc_sink will cause null pointer dereference. [how] Remove redundant checking condition. Relevant condition should already be covered by checking if dsc_aux is null or not. Also reset dsc_aux to NULL when the connector is disconnected. Reviewed-by: Jerry Zuo <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: change dram_clock_latency to 34us for dcn35Paul Hsieh1-1/+1
[Why & How] Current DRAM setting would cause underflow on customer platform. Modify dram_clock_change_latency_us from 11.72 to 34.0 us as per recommendation from HW team Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Paul Hsieh <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Change dram_clock_latency to 34us for dcn351Daniel Miess1-1/+1
[Why] Intermittent underflow observed when using 4k144 display on dcn351 [How] Update dram_clock_change_latency_us from 11.72us to 34us Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Daniel Miess <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Correct the defined value for AMDGPU_DMUB_NOTIFICATION_MAXWayne Lin1-1/+1
[Why & How] It actually exposes '6' types in enum dmub_notification_type. Not 5. Using smaller number to create array dmub_callback & dmub_thread_offload has potential to access item out of array bound. Fix it. Reviewed-by: Jerry Zuo <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Defer the setting of link hpd status for usb4/tbtWayne Lin1-8/+0
[Why & How] Link hpd status is set during link detection process via dpia_query_hpd_status(), doesn't need to explicitly set it during outbox irq. Remove it. Reviewed-by: Jerry Zuo <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Adjust debug msg for usb4/tbtWayne Lin1-23/+34
[Why & How] Debug msg for usb4/tbt now is a bit confusing. Adjust it for better reading. Reviewed-by: Jerry Zuo <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Avoid programming DTO if Refclk is 0Chris Park1-0/+4
[Why] Reference clock, either DPREFCLK or DTBCLK can be a value of 0 which then will encounter division by 0. [How] Avoid further calculation and programming if refclk is not populated. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Chris Park <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Disable boot optimization for DCN401Joshua Aberback2-1/+9
[Why] DCN401 currently has an issue re-enabling when pipe splitting is enabled, while the root cause is being investigated we can make sure everything is being reset as a workaround, by disabling boot optimization. [How] - use enable_accelerated_mode instead of init_pipes to fully reset asic Reviewed-by: Alvin Lee <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Joshua Aberback <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-06-14drm/amd/display: Prevent overflow on DTO calculationChris Park1-4/+8
[Why] uint32_t is implicitly converted to uint64_t while multiplication still happens on uint32_t side. This creates digit overflow for large pixel clock which is meant to be retained in uint64_t. [How] Calculate multiplication of units in uint64_t domain instead of uint32_t in DTO parameter clock caculation. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Zaeem Mohamed <[email protected]> Signed-off-by: Chris Park <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.