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2024-07-23drm/amd/display: Fix index out of bounds in DCN30 degamma hardware format ↵Srinivasan Shanmugam1-0/+2
translation This commit addresses a potential index out of bounds issue in the `cm3_helper_translate_curve_to_degamma_hw_format` function in the DCN30 color management module. The issue could occur when the index 'i' exceeds the number of transfer function points (TRANSFER_FUNC_POINTS). The fix adds a check to ensure 'i' is within bounds before accessing the transfer function points. If 'i' is out of bounds, the function returns false to indicate an error. Reported by smatch: drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_cm_common.c:338 cm3_helper_translate_curve_to_degamma_hw_format() error: buffer overflow 'output_tf->tf_pts.red' 1025 <= s32max drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_cm_common.c:339 cm3_helper_translate_curve_to_degamma_hw_format() error: buffer overflow 'output_tf->tf_pts.green' 1025 <= s32max drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_cm_common.c:340 cm3_helper_translate_curve_to_degamma_hw_format() error: buffer overflow 'output_tf->tf_pts.blue' 1025 <= s32max Cc: Tom Chung <[email protected]> Cc: Rodrigo Siqueira <[email protected]> Cc: Roman Li <[email protected]> Cc: Alex Hung <[email protected]> Cc: Aurabindo Pillai <[email protected]> Cc: Harry Wentland <[email protected]> Cc: Hamza Mahfooz <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Tom Chung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Add kdoc entry for 'bs_coeffs_updated' in ↵Srinivasan Shanmugam1-0/+1
dpp401_dscl_program_isharp Fixes the below with gcc W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/dpp/dcn401/dcn401_dpp_dscl.c:961: warning: Function parameter or struct member 'bs_coeffs_updated' not described in 'dpp401_dscl_program_isharp' Fixes: 94beb4ac1b3b ("drm/amd/display: ensure EASF and ISHARP coefficients are programmed together") Cc: Tom Chung <[email protected]> Cc: Rodrigo Siqueira <[email protected]> Cc: Roman Li <[email protected]> Cc: Alex Hung <[email protected]> Cc: Aurabindo Pillai <[email protected]> Cc: Harry Wentland <[email protected]> Cc: Hamza Mahfooz <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: 3.2.293Aric Cyr1-1/+1
Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Reviewed-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: remove unused folderAurabindo Pillai2-23/+0
dc/{dcn401,dcn303} are unused since the files in it got moved under their respective new components location. Hence they are no longer necessary Fixes: 2d62bb450ed1 ("drm/amd/display: Refactor DCN3X into component folder") Reviewed-by: Leo Li <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Remove duplicate HWSS interfacesJoshua Aberback21-45/+22
[Why] Some interface functions are defined in both the public and private HWSS interfaces, which can lead to confusion and runtime issues, therefore the duplicates should be eliminated. [How] - power_down should only be private, because it's only used within HWSS. - update_plane_addr should only be public, as it's used outside HWSS. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Joshua Aberback <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Various DML2 fixes for FAMS2Dillon Varone2-2/+1
The disable fams2 operation was reworked, but some of the old code remained. This commit removes the disable_fams2_drr from the dml2_stream_parameters. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Remove old commentsRodrigo Siqueira2-4/+4
Remove some old comments from DCN32/321. Signed-off-by: Rodrigo Siqueira <[email protected]> Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Check link_res->hpo_dp_link_enc before using itAlex Hung1-0/+5
[WHAT & HOW] Functions dp_enable_link_phy and dp_disable_link_phy can pass link_res without initializing hpo_dp_link_enc and it is necessary to check for null before dereferencing. This fixes 1 FORWARD_NULL issue reported by Coverity. Fixes: 0beca868cde8 ("drm/amd/display: Check link_res->hpo_dp_link_enc before using it") Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Add MST debug message when link detection failsAlex Hung1-1/+4
[WHY & HOW] dc_link_detect returns a boolean value which can be used to print debug messages when it fails. This fixes 1 CHECKED_RETURN issue reported by Coverity. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Hung <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Check top sink only when multiple streams for DP2Sung Joon Kim4-8/+42
[why] When switching from extended to second display only mode, the top remote sink is not removed while the top stream itself is released. This causes DML to think there is no DP2 output encoder because top remote sink does not match with the second stream and disables DTBCLK and causes hang. [how] For DP2.0 MST hubs, only treat 1st remote sink as an encoder only when there are multiple displays connected. Reviewed-by: Michael Strauss <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Fix Potential Null DereferenceGabe Teeger1-3/+3
[what & why] System hang after s4 regression points to code change here. Removing possible NULL dereference. Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Gabe Teeger <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Add helper function to check for non-address fast updatesIlya Bakoulin2-1/+30
[Why/How] Need to identify which fast updates will update more than just the address. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Ilya Bakoulin <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: rename dcn401_soc to dcn4_variant_a_socAurabindo Pillai2-2/+2
To distinguish between different soc with same DCN IP, use variants starting with alphabets Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: rename dcn3/dcn4 to more sound termsAurabindo Pillai12-475/+475
Use more accurate names to refer to the asic architecture. dcn3 in DML actually refers to DCN32 and DCN321, so rename it to dcn32x dcn4 refers to any DCN4x soc., and hence rename dcn4 to dcn4x Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Add source select helper functionsHansen Dsouza1-0/+324
[why & how] Add source select helpers based on DCCG spec Reviewed-by: Daniel Miess <[email protected]> Signed-off-by: Hansen Dsouza <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Check if Mode is Supported Before Returning ResultAustin Zheng1-1/+2
[Why] Even if the mode is not supported dml2_check_mode_supported() would still return true. This causes an unsupported mode to be programmed. [How] Check if the mode is supported or not and return the proper result. Reviewed-by: Chaitanya Dhere <[email protected]> Signed-off-by: Austin Zheng <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: ensure EASF and ISHARP coefficients are programmed togetherSamson Tam1-8/+20
[Why] EASF coefficients are programmed to RAM and then RAM selector is toggled. ISHARP coefficients are programmed after so they will not be in the same RAM block [How] Move ISHARP programming before EASF programming Add flag if ISHARP coefficients are updated. If so, then force EASF coefficients programming Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Samson Tam <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Fix visual confirm bug for SubVPRyan Seto3-6/+31
[Why] Visual confirm was incorrect on dual monitor SubVP setup [How] Adjusted p_state assignment for dual monitor SubVP setup Signed-off-by: Ryan Seto <[email protected]> Reviewed-by: Chaitanya Dhere <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Add RCG helper functionsHansen Dsouza1-0/+307
[why & how] Add standard RCG helpers based on DCCG spec Reviewed-by: Daniel Miess <[email protected]> Reviewed-by: Muhammad Ahmed <[email protected]> Signed-off-by: Hansen Dsouza <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Remove ASSERT if significance is zero in math_ceil2Rodrigo Siqueira1-2/+0
In the DML math_ceil2 function, there is one ASSERT if the significance is equal to zero. However, significance might be equal to zero sometimes, and this is not an issue for a ceil function, but the current ASSERT will trigger warnings in those cases. This commit removes the ASSERT if the significance is equal to zero to avoid unnecessary noise. Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Reviewed-by: Chaitanya Dhere <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Refactoring HPORevalla Hari Krishna7-3/+16
[Why] To refactor HPO files [How] Moved hpo related files to specific hpo folder and update Makefiles. Reviewed-by: Martin Leung <[email protected]> Signed-off-by: Revalla Hari Krishna <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Add private data type for RCGHansen Dsouza1-0/+81
[why & how] Add private data types for better RCG control Reviewed-by: Chris Park <[email protected]> Reviewed-by: Yihan Zhu <[email protected]> Signed-off-by: Hansen Dsouza <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Check for NULL pointerSung Joon Kim1-1/+2
[why & how] Need to make sure plane_state is initialized before accessing its members. Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Reviewed-by: Xi (Alex) Liu <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Remove hardmax usage for dcn401Dillon Varone3-29/+29
[WHY&HOW] Hardmax message will be retired for dcn4, so this removes it. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Add 'pstate_keepout' kdoc entry in 'optc1_program_timing'Srinivasan Shanmugam1-0/+1
Fixes the below with gcc W=1: Function parameter or struct member 'pstate_keepout' not described in 'optc1_program_timing' Cc: Tom Chung <[email protected]> Cc: Rodrigo Siqueira <[email protected]> Cc: Roman Li <[email protected]> Cc: Alex Hung <[email protected]> Cc: Aurabindo Pillai <[email protected]> Cc: Harry Wentland <[email protected]> Cc: Hamza Mahfooz <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Tom Chung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: 3.2.292Aric Cyr1-1/+1
* FW Release 0.0.225.0 * DML2 fixes * Allow display DCC for DCN401 * Refactor DWB, OPP, MPC, MMHUBBUB * Fix dscclk Programming issue on DCN401 Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Remove unused dml2_core_ip_params structRodrigo Siqueira1-78/+0
Acked-by: Jerry Zuo <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Remove unnecessary DSC power gating for DCN401Joshua Aberback1-2/+0
[Why] In some cases during topology changes, a pipe that was used to drive a stream being removed can be re-assigned to drive a different stream. In these cases, DSC power gating is not handled properly, leading to situations where DSC is being setup while power gated. [How] - remove enable_stream_gating and disable_stream_gating for DCN401 Reviewed-by: Wenjing Liu <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Joshua Aberback <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: free bo used for dmub bounding boxAurabindo Pillai1-2/+11
fix a memleak introduced by not removing the buffer object for use with early dmub bounding box value storage Fixes: 234e94555800 ("drm/amd/display: Enable copying of bounding box data from VBIOS DMUB") Reviewed-by: Rodrigo Siqueira <[email protected]> Reviewed-by: Alex Hung <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Add visual confirm for Idle StateDuncan Ma4-0/+8
[Why] Visual Confirm would tell us if it ever entered idle state. [How] Add debug option for IPS visual confirm Reviewed-by: Ovidiu Bunea <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Duncan Ma <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Set Cursor Matrix to bypass instead of Input PlaneDaniel Sa1-12/+2
why: When the cursor disappears/reappears on fullscreen video, there is a short transitional period where the cursor's color matrix is using the same format as the video plane. This sets the cursor to the wrong color momentarily before the UI plane appears, correcting the color. how: Instead of defaulting to using the color space from the input plane, default to bypass mode. Reviewed-by: Nevenko Stupar <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Daniel Sa <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Check stream pointer is initialized before accessingSung Joon Kim1-4/+3
[why & how] We calculate static screen wait frames based on the current timing info in the active stream. If stream is not initialized, then we should skip the calculation and go with the default values. Reviewed-by: Gabe Teeger <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Export additional FAMS2 global configuration options from DMLDillon Varone7-95/+110
[WHY&HOW] Some global configuration options were previously hardcoded in DC, now they are exported by DML and sent to FW. Reviewed-by: Martin Leung <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Refactoring DWB related files from dcn30 FilesMudimela8-4/+10
[Why] To refactor DWB related files from dcn30 Files [How] Moved DWB related files from dcn30 to specific DWB folder and updated Makefiles to fix Compilation. Reviewed-by: Martin Leung <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Mudimela <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: add dmcub support checkFudongwang1-0/+3
[Why & How] For DCN harvest case, if there is no dmcub support, we should return false to avoid bugcheck later. Reviewed-by: Aric Cyr <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Fudongwang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Increase array size of dummy_booleanAlex Hung1-1/+1
[WHY] dml2_core_shared_mode_support and dml_core_mode_support access the third element of dummy_boolean, i.e. hw_debug5 = &s->dummy_boolean[2], when dummy_boolean has size of 2. Any assignment to hw_debug5 causes an OVERRUN. [HOW] Increase dummy_boolean's array size to 3. This fixes 2 OVERRUN issues reported by Coverity. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Check null pointers before multiple usesAlex Hung7-56/+76
[WHAT & HOW] Poniters, such as stream_enc and dc->bw_vbios, are null checked previously in the same function, so Coverity warns "implies that stream_enc and dc->bw_vbios might be null". They are used multiple times in the subsequent code and need to be checked. This fixes 10 FORWARD_NULL issues reported by Coverity. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Check null pointers before usedAlex Hung8-14/+17
[WHAT & HOW] Poniters, such as dc->clk_mgr, are null checked previously in the same function, so Coverity warns "implies that "dc->clk_mgr" might be null". As a result, these pointers need to be checked when used again. This fixes 10 FORWARD_NULL issues reported by Coverity. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Check link_res->hpo_dp_link_enc before using itAlex Hung1-0/+7
[WHAT & HOW] Functions dp_enable_link_phy and dp_disable_link_phy can pass link_res without initializing hpo_dp_link_enc and it is necessary to check for null before dereferencing. This fixes 2 FORWARD_NULL issues reported by Coverity. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Alex Hung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Add P-State Keepout to dcn401 Global SyncDillon Varone20-13/+83
[WHY&HOW] OTG has new functionality to allow P-State relative to VStartup. Keepout region for this should be configured based on DML outputs same as other global sync params. Reviewed-by: Alvin Lee <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: remove dc dependencies from SPL librarySamson Tam17-432/+1646
[Why] Make SPL library dc-independent so it can be reused by other components [How] Create separate set of fixed31_32 calls in SPL Make all inputs and outputs to SPL use primitive types For ratios and inits, return as uint32 from SPL. So add conversion from uint32 back to fixed point in SPL-to-dc translate function Reviewed-by: Relja Vojvodic <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Samson Tam <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Issue with 3 or more mcaches per surfaceNevenko Stupar1-11/+11
[Why & How] Current logic in mcache admissibility check has flaw if calculated number of maches are 3 or more per surface, so sometimes the check may pass when it should fail, and sometimes may fail when it should pass, fix the issue and also adding additional check to make sure that required number of mcaches per surface cannot be higher than number of pipes + 1, used on that surface. Reviewed-by: Chaitanya Dhere <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Nevenko Stupar <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Calculate ODM width using odm slice rect, not recoutAlvin Lee1-4/+4
[Description] There are scenarios where ODM4:1 is used but the surface is entirely outside of the first and last ODM slice. In this case the recout.width for the first and last slice is 0 because there's no overlap with the surface and that ODM slice, but this causes the x_pos for the cursor in this scenario to be calculated incorrectly. Instead we should use the ODM slice width instead of the recout width. Reviewed-by: Nevenko Stupar <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Add blanked streams override to DML2.1Dillon Varone1-0/+7
[WHY] DML2.1 currently has no concept of a "blanked" stream. For cases like DPMS off, things like UCLK p-state is always allowed, so PMO is not required to optimize for it. [HOW] Add flag to DML2.1 display configuration to indicate all streams are blanked, so certain operations and optimizations can be skipped for optimal programming when displays are blanked. Reviewed-by: Chaitanya Dhere <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Fix VRR cannot enableTom Chung1-21/+2
[Why] Sometimes the VRR cannot enable after login to the desktop. User space may call the DRM_IOCTL_MODE_GETCONNECTOR right after the DRM_IOCTL_MODE_RMFB. After calling DRM_IOCTL_MODE_RMFB to remove all the frame buffer and it will cause the driver to disable the crtc and disable the link while calling the link_set_dpms_off(). It will cause the dpcd read failed in amdgpu_dm_update_freesync_caps() while try to get the DP_MSA_TIMING_PAR_IGNORED capability and think the sink side does not support VRR. [How] Use the dpcd_caps.allow_invalid_MSA_timing_param flag instead of reading from dpcd directly. dpcd_caps.allow_invalid_MSA_timing_param flag is updated during HPD. It is safe to replace the original method. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Tom Chung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Refactoring MPCMounika Adhuri10-5/+30
[Why] To refactor MPC files [How] Moved MPC files to respective folders and updated makefiles appropriately. Reviewed-by: Martin Leung <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Mounika Adhuri <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: DML2.1 resynchronizationChaitanya Dhere43-1669/+566
July update for DML2.1 library from hardware team targeting DCN401 Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Chaitanya Dhere <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Do 1-to-1 mapping between OPP and DSC in DML2Sung Joon Kim1-1/+1
[why] To determine which block instance to power-gate, we look at the available pipe resource for both plane and stream. On MPO, DSC3 was falsely powered on even though only 1 stream path was enabled because the resource mapping was not done correctly. [how] Acquire the correct DSC instance to power on / off based on the instance of OPP which determines the backend pipe index. Reviewed-by: Swapnil Patel <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Sung Joon Kim <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Refactoring MMHUBBUBRevalla Hari Krishna4-1/+10
[Why] To refactor MMHUBBUB files [How] Moved mmhubbub files from dcn20 to /mmhubbub/ folder and update makefile to fix compilation. Reviewed-by: Martin Leung <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Revalla Hari Krishna <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-07-23drm/amd/display: Deallocate DML memory if allocation failsChris Park1-2/+8
[Why] When DC state create DML memory allocation fails, memory is not deallocated subsequently, resulting in uninitialized structure that is not NULL. [How] Deallocate memory if DML memory allocation fails. Reviewed-by: Joshua Aberback <[email protected]> Signed-off-by: Jerry Zuo <[email protected]> Signed-off-by: Chris Park <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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