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2024-01-15drm/amd/display: Rework DC Z10 restoreNicholas Kazlauskas3-7/+15
[Why] The call currently does two things: 1. Exits DMCUB from idle optimization if it was in 2. Checks DMCUB scratch register to determine if we need to call DMCUB to do deferred HW restore and then sends the command if it's ready for it. By doing (1) we prevent driver idle from being renotified in the cases where driver had previously allowed DC level idle optimizations via dc_allow_idle_optimizations since it thinks: allow == dc->idle_optimizations_allowed ...and that the operation is a no-op. We want driver idle to be resent at the next opprotunity to do so for video playback cases. [How] Migrate all usecases of dc_z10_restore to only perform (2). Add extra calls to dc_allow_idle_optimizations to handle (1) and also keep SW state matching with when we requested enter/exit of DMCUB idle optimizations. Ensure cursor idle optimizations false always get called when IPS is supported. Further rework/redesign is needed to decide whether we need a separate level of DM allow vs DC allow and when to attempt re-entry. Reviewed-by: Yihan Zhu <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-15drm/amd/display: Enable Panel Replay for static screen use caseTom Chung4-68/+156
[Why] Enable the Panel Replay if eDP panel and ASIC support. (prioritize Panel Replay over PSR) [How] - Setup the Panel Replay config during the device init (prioritize Panel Replay over PSR). - Separate the Replay init function into two functions amdgpu_dm_link_setup_replay() and amdgpu_dm_set_replay_caps() to fix the issue in the earlier commit that cause PSR and Replay enabled at the same time. Reviewed-by: Sun peng Li <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Tom Chung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-15drm/amd/display: Add DP audio BW validationGeorge Shen5-16/+349
[Why] Timings with small HBlank (such as CVT RBv2) can result in insufficient HBlank bandwidth for audio SDP transmission when DSC is active. This will cause some higher bandwidth audio modes to fail. The combination of CVT RBv2 timings + DSC can commonly be encountered in MST scenarios. [How] Add DP audio bandwidth validation for 8b/10b MST and 128b/132b SST/MST cases and filter out modes that cannot be supported with the current timing config. Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: George Shen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-15drm/amd/display: Fix dml2 assigned pipe searchDmytro Laktyushkin1-8/+28
[Why & How] DML2 currently finds assigned pipes in array order rather than the existing linked list order. This results in rearranging pipe order on flip and more importantly otg inst and pipe idx mismatch. This change preserves the order of existing pipes and guarantees the head pipe will have matching otg inst and pipe idx. Reviewed-by: Gabe Teeger <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Dmytro Laktyushkin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-15drm/amd/display: Ensure populate uclk in bb constructionAlvin Lee3-8/+30
[Description] - For some SKUs, the optimal DCFCLK for each UCLK is less than the smallest DCFCLK STA target due to low memory bandwidth. There is an assumption that the DCFCLK STA targets will always be less than one of the optimal DCFCLK values, but this is not true for SKUs that have low memory bandwidth. In this case we need to populate the optimal UCLK for each DCFCLK STA targets as the max UCLK freq. - Also fix a bug in DML where start_state is not assigned and used correctly. Reviewed-by: Samson Tam <[email protected]> Reviewed-by: Chaitanya Dhere <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-15drm/amd/display: Update P010 scaling capCharlene Liu2-14/+13
[Why] Keep the same as previous APU and also insert clock dump Reviewed-by: Ovidiu Bunea <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-15drm/amd/display: Fix DML2 watermark calculationOvidiu Bunea1-7/+7
[Why] core_mode_programming in DML2 should output watermark calculations to locals, but it incorrectly uses mode_lib [How] update code to match HW DML2 Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Reviewed-by: Charlene Liu <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Ovidiu Bunea <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-15drm/amd/display: Clear OPTC mem select on disableIlya Bakoulin2-0/+6
[Why] Not clearing the memory select bits prior to OPTC disable can cause DSC corruption issues when attempting to reuse a memory instance for another OPTC that enables ODM. [How] Clear the memory select bits prior to disabling an OPTC. Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Reviewed-by: Charlene Liu <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Ilya Bakoulin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-15drm/amd/display: Floor to mhz when requesting dpp disp clock changes to SMUWenjing Liu2-4/+41
[Why] SMU uses discrete dpp and disp clock levels. When we submit SMU request for clock changes in Mhz we need to floor the requested value from Khz so SMU will choose the next higher clock level in Khz to set. If we ceil to Mhz, SMU will have to choose the next higher clock level after the ceil, which could result in unnecessarily jumpping to the next level. For example, we request 1911,111Khz which is exactly one of the SMU preset level. If we pass 1912Mhz, SMU will choose 2150,000 khz. If we pass 1911Mhz, SMU will choose 1911,111kHz, which is the expected value. Reviewed-by: Alvin Lee <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-15drm/amd/display: Port DENTIST hang and TDR fixes to OTG disable W/ANicholas Kazlauskas1-12/+9
[Why] We can experience DENTIST hangs during optimize_bandwidth or TDRs if FIFO is toggled and hangs. [How] Port the DCN35 fixes to DCN314. Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Reviewed-by: Charlene Liu <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-15drm/amd/display: Add logging resource checksCharlene Liu3-3/+10
[Why] When mapping resources, resources could be unavailable. Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Reviewed-by: Sung joon Kim <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-15drm/amdgpu: check PS, WS indexAlexander Richards2-2/+2
Theoretically, it would be possible for a buggy or malicious VBIOS to overwrite past the bounds of the passed parameters (or its own workspace); add bounds checking to prevent this from happening. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/3093 Signed-off-by: Alexander Richards <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-15drm/amd/display: Add Replay IPS register for DMUB command tableAlvin Lee1-0/+1
- Introduce a new Replay mode for DMUB version 0.0.199.0 Reviewed-by: Martin Leung <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-15drm/amd/display: Init link enc resources in dc_state only if res_pool presentsDillon Varone1-1/+2
[Why & How] res_pool is not initialized in all situations such as virtual environments, and therefore link encoder resources should not be initialized if res_pool is NULL. Cc: Mario Limonciello <[email protected]> Cc: Alex Deucher <[email protected]> Cc: [email protected] Reviewed-by: Martin Leung <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Dillon Varone <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-15drm/amd/display: Allow IPS2 during ReplayNicholas Kazlauskas3-1/+11
[Why & How] Add regkey to block video playback in IPS2 by default Allow idle optimizations in the same spot we allow Replay for video playback usecases. Avoid sending it when there's an external display connected by modifying the allow idle checks to check for active non-eDP screens. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Alex Hung <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-15drm/amd/display: Fix late derefrence 'dsc' check in 'link_set_dsc_pps_packet()'Srinivasan Shanmugam1-2/+6
In link_set_dsc_pps_packet(), 'struct display_stream_compressor *dsc' was dereferenced in a DC_LOGGER_INIT(dsc->ctx->logger); before the 'dsc' NULL pointer check. Fixes the below: drivers/gpu/drm/amd/amdgpu/../display/dc/link/link_dpms.c:905 link_set_dsc_pps_packet() warn: variable dereferenced before check 'dsc' (see line 903) Cc: [email protected] Cc: Aurabindo Pillai <[email protected]> Cc: Rodrigo Siqueira <[email protected]> Cc: Hamza Mahfooz <[email protected]> Cc: Wenjing Liu <[email protected]> Cc: Qingqing Zhuo <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-15drm/amd/display: Avoid enum conversion warningNathan Chancellor1-2/+3
Clang warns (or errors with CONFIG_WERROR=y) when performing arithmetic with different enumerated types, which is usually a bug: drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_dpia_bw.c:548:24: error: arithmetic between different enumeration types ('const enum dc_link_rate' and 'const enum dc_lane_count') [-Werror,-Wenum-enum-conversion] 548 | link_cap->link_rate * link_cap->lane_count * LINK_RATE_REF_FREQ_IN_KHZ * 8; | ~~~~~~~~~~~~~~~~~~~ ^ ~~~~~~~~~~~~~~~~~~~~ 1 error generated. In this case, there is not a problem because the enumerated types are basically treated as '#define' values. Add an explicit cast to an integral type to silence the warning. Closes: https://github.com/ClangBuiltLinux/linux/issues/1976 Fixes: 5f3bce13266e ("drm/amd/display: Request usb4 bw for mst streams") Signed-off-by: Nathan Chancellor <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-15drm/amd/display: Fix variable deferencing before NULL check in ↵Srinivasan Shanmugam1-4/+7
edp_setup_replay() In edp_setup_replay(), 'struct dc *dc' & 'struct dmub_replay *replay' was dereferenced before the pointer 'link' & 'replay' NULL check. Fixes the below: drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_edp_panel_control.c:947 edp_setup_replay() warn: variable dereferenced before check 'link' (see line 933) Cc: [email protected] Cc: Bhawanpreet Lakha <[email protected]> Cc: Harry Wentland <[email protected]> Cc: Rodrigo Siqueira <[email protected]> Cc: Aurabindo Pillai <[email protected]> Cc: Alex Deucher <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-09drm/amd/display: cleanup inconsistent indenting in amdgpu_dm_colorMelissa Wen1-1/+1
smatch warnings: amdgpu_dm_update_plane_color_mgmt() warn: inconsistent indenting Reported-by: kernel test robot <[email protected]> Closes: https://lore.kernel.org/oe-kbuild-all/[email protected]/ Signed-off-by: Melissa Wen <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-09Revert "drm/amd/display: fix bandwidth validation failure on DCN 2.1"Ivan Lipski1-1/+1
This commit causes dmesg-warn on several IGT tests on DCN 3.1.6: *ERROR* link_enc_cfg_validate: Invalid link encoder assignments - 0x1c Affected IGT tests include: - amdgpu/[amd_assr|amd_plane|amd_hotplug] - kms_atomic - kms_color - kms_flip - kms_properties - kms_universal_plane and some other tests This reverts commit 3a0fa3bc245ef92838a8296e0055569b8dff94c4. Cc: Melissa Wen <[email protected]> Cc: Hamza Mahfooz <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-09drm/amd/display: 3.2.266Aric Cyr1-1/+1
This version brings along following fixes: - Improve z8/z10 support. - Revert some of the VRR optimization. - Improve usb4 when using MST. Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-09drm/amd/display: Dpia hpd status not in sync after S4Meenakshikumar Somasundaram1-14/+22
[Why] Dpia hpd status not in sync causing driver not enabling BW Alloc after S4. [How] Update hpd_status of the link when querying hpd state from dmub in dpia_query_hpd_status(). Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Meenakshikumar Somasundaram <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-09drm/amd/display: Update z8 latencyCharlene Liu1-3/+3
Adjust z8 latency for performance. Reviewed-by: Muhammad Ahmed <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-09Revert "drm/amd/display: Fix conversions between bytes and KB"Daniel Miess1-9/+9
This reverts commit d0f639c5869399bf6dde4d694d5f8c0ab8c0ec46. The previous commit causes failure to light up for 1080p eDP + 8k HDMI panel combo. Reviewed-by: Charlene Liu <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Daniel Miess <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-09drm/amd/display: Request usb4 bw for mst streamsPeichen Huang5-38/+144
[WHY] When usb4 bandwidth allocation mode is enabled, driver need to request bandwidth from connection manager. For mst link, the requested bandwidth should be big enough for all remote streams. [HOW] - If mst link, the requested bandwidth should be the sum of all mst streams bandwidth added with dp MTPH overhead. - Allocate/deallcate usb4 bandwidth when setting dpms on/off. - When doing display mode validation, driver also need to consider total bandwidth of all mst streams for mst link. Reviewed-by: Cruise Hung <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Peichen Huang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-09drm/amd/display: revert "Optimize VRR updates to only necessary ones"Martin Leung5-10/+17
This reverts commit 6e4337f695c25162f0296934152506ad596fcebf. The original commit causes regression in corner case with HDMI at specific timings. Reverting from staging to get the full suite to retest. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Martin Leung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-09drm/amd/display: revert "for FPO & SubVP/DRR config program vmin/max"Martin Leung8-62/+24
This reverts commit 6b2b782ad6a25734ae847d1659bea3f613dbb563. The original commit causes issues with certain features when DRR is disabled, need to revisit this change later after resolving issues with new DRR policy. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Martin Leung <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-09drm/amd/display: Disconnect phantom pipe OPP from OPTC being disabledGeorge Shen2-12/+19
[Why] If an OPP is used for a different OPTC without first being disconnected from the previous OPTC, unexpected behaviour can occur. This also applies to phantom pipes, which is what the current logic missed. [How] Disconnect OPPs from OPTC for phantom pipes before disabling OTG master. Also move the disconnection to before the OTG master disable, since the register is double buffered. Reviewed-by: Dillon Varone <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: George Shen <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-09drm/amd/display: To adjust dprefclk by down spread percentageMartin Tsai7-5/+93
[Why] Panels show corruption with high refresh rate timings when ssc is enabled. [How] Read down-spread percentage from lut to adjust dprefclk. Issues come from S0i3 with this commit has been fixed by SMU. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Martin Tsai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-05drm/amd/display: Allow z8/z10 from driverCharlene Liu1-0/+2
Copy StutterPeriod from DML2 into DML1 StutterPeriod parameter. Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Muhammad Ahmed <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Charlene Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-05drm/amd/display: fix bandwidth validation failure on DCN 2.1Melissa Wen1-1/+1
IGT `amdgpu/amd_color/crtc-lut-accuracy` fails right at the beginning of the test execution, during atomic check, because DC rejects the bandwidth state for a fb sizing 64x64. The test was previously working with the deprecated dc_commit_state(). Now using dc_validate_with_context() approach, the atomic check needs to perform a full state validation. Therefore, set fast_validation to false in the dc_validate_global_state call for atomic check. Cc: [email protected] Fixes: b8272241ff9d ("drm/amd/display: Drop dc_commit_state in favor of dc_commit_streams") Signed-off-by: Melissa Wen <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-05drm/amdgpu: apply the RV2 system aperture fix to RN/CZN as wellAlex Deucher1-2/+6
These chips needs the same fix. This was previously not seen on then since the AGP aperture expanded the system aperture, but this showed up again when AGP was disabled. Reviewed-and-tested-by: Jiadong Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-05drm/amd/display: Move fixpt_from_s3132 to amdgpu_dmHarry Wentland2-15/+15
Other environments don't like the unary minus operator on an unsigned value. Signed-off-by: Harry Wentland <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-05drm/amd/display: Fix recent checkpatch errors in amdgpu_dmHarry Wentland3-6/+5
- Use tabs, not spaces. - Brace and parentheses placement Signed-off-by: Harry Wentland <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-05drm/amd/display: avoid stringop-overflow warnings for dp_decide_lane_settings()Arnd Bergmann2-2/+2
gcc prints a warning about a possible array overflow for a couple of callers of dp_decide_lane_settings() after commit 1b56c90018f0 ("Makefile: Enable -Wstringop-overflow globally"): drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c: In function 'dp_perform_fixed_vs_pe_training_sequence_legacy': drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c:426:25: error: 'dp_decide_lane_settings' accessing 4 bytes in a region of size 1 [-Werror=stringop-overflow=] 426 | dp_decide_lane_settings(lt_settings, dpcd_lane_adjust, | ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ 427 | lt_settings->hw_lane_settings, lt_settings->dpcd_lane_settings); | ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_training_fixed_vs_pe_retimer.c:426:25: note: referencing argument 4 of type 'union dpcd_training_lane[4]' I'm not entirely sure what caused this, but changing the prototype to expect a pointer instead of an array avoids the warnings. Fixes: 7727e7b60f82 ("drm/amd/display: Improve robustness of FIXED_VS link training at DP1 rates") Acked-by: Randy Dunlap <[email protected]> Tested-by: Randy Dunlap <[email protected]> # build-tested Signed-off-by: Arnd Bergmann <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-05drm/amd/display: Fix power_helpers.c codestyleMarcelo Mendes Spessoto Junior1-1/+1
Place define macro expression inside () in power_helpers.c file Signed-off-by: Marcelo Mendes Spessoto Junior <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-05drm/amd/display: Fix hdcp_log.h codestyleMarcelo Mendes Spessoto Junior1-4/+6
Place HDCP_EVENT_TRACE(hdcp, event) macro content inside do while loop to avoid if-else issues in hdcp_log.h file v2: fix up build (Alex) Signed-off-by: Marcelo Mendes Spessoto Junior <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-05drm/amd/display: Fix hdcp2_execution.c codestyleMarcelo Mendes Spessoto Junior1-4/+2
Remove braces for single statement if expressions and change comparison order for hdcp2_execution.c file Signed-off-by: Marcelo Mendes Spessoto Junior <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-05drm/amd/display: Fix hdcp_psp.h codestyleMarcelo Mendes Spessoto Junior1-5/+5
Fix identation inside enum and place expressions in define macros inside () for hdcp_psp.h file Signed-off-by: Marcelo Mendes Spessoto Junior <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-05drm/amd/display: Fix freesync.c codestyleMarcelo Mendes Spessoto Junior1-2/+2
Remove braces for single statement if expression for freesync.c file Signed-off-by: Marcelo Mendes Spessoto Junior <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-05drm/amd/display: Fix hdcp_psp.c codestyleMarcelo Mendes Spessoto Junior1-2/+2
Fix identation for hdcp_psp.c file Signed-off-by: Marcelo Mendes Spessoto Junior <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-05drm/amd/display: Fix hdcp1_execution.c codestyleMarcelo Mendes Spessoto Junior1-2/+2
Remove braces from single statement if expression in hdcp1_execution.c file Signed-off-by: Marcelo Mendes Spessoto Junior <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-05drm/amd/display: Removing duplicate copyright textMarcelo Mendes Spessoto Junior1-28/+0
mod_freesync header file has duplicated copyright boilerplate. Drop the duplicate. Signed-off-by: Marcelo Mendes Spessoto Junior <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-05drm/amd/display: add nv12 bounding boxAlex Deucher1-1/+109
This was included in gpu_info firmware, move it into the driver for consistency with other nv1x parts. Link: https://gitlab.freedesktop.org/drm/amd/-/issues/2318 Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-05drm/amd/display: Fix sending VSC (+ colorimetry) packets for DP/eDP displays ↵Joshua Ashton2-8/+13
without PSR The check for sending the vsc infopacket to the display was gated behind PSR (Panel Self Refresh) being enabled. The vsc infopacket also contains the colorimetry (specifically the container color gamut) information for the stream on modern DP. PSR is typically only supported on mobile phone eDP displays, thus this was not getting sent for typical desktop monitors or TV screens. This functionality is needed for proper HDR10 functionality on DP as it wants BT2020 RGB/YCbCr for the container color space. Cc: [email protected] Cc: Harry Wentland <[email protected]> Cc: Xaver Hugl <[email protected]> Cc: Melissa Wen <[email protected]> Fixes: 15f9dfd545a1 ("drm/amd/display: Register Colorspace property for DP and HDMI") Tested-by: Simon Berz <[email protected]> Tested-by: Xaver Hugl <[email protected]> Signed-off-by: Joshua Ashton <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-03drm/amd/display: Adjust kdoc for 'dcn35_hw_block_power_down' & ↵Srinivasan Shanmugam1-27/+41
'dcn35_hw_block_power_up' Fixes the following gcc with W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/hwss/dcn35/dcn35_hwseq.c:1124: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst Cc: Charlene Liu <[email protected]> Cc: Muhammad Ahmed <[email protected]> Cc: Hamza Mahfooz <[email protected]> Cc: Rodrigo Siqueira <[email protected]> Cc: Aurabindo Pillai <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Srinath Rao <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-03drm/amd/display: Address function parameter 'context' not described in ↵Srinivasan Shanmugam2-2/+3
'dc_state_rem_all_planes_for_stream' & 'populate_subvp_cmd_drr_info' Fixes the following gcc with W=1: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_state.c:524: warning: Function parameter or member 'state' not described in 'dc_state_rem_all_planes_for_stream' drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_state.c:524: warning: Excess function parameter 'context' description in 'dc_state_rem_all_planes_for_stream' drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c:540: warning: Function parameter or member 'context' not described in 'populate_subvp_cmd_drr_info' Suggested-by: Aurabindo Pillai <[email protected]> Cc: Dillon Varone <[email protected]> Cc: Jun Lei <[email protected]> Cc: Hamza Mahfooz <[email protected]> Cc: Aurabindo Pillai <[email protected]> Cc: Rodrigo Siqueira <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Srinath Rao <[email protected]> Signed-off-by: Srinivasan Shanmugam <[email protected]> Reviewed-by: Aurabindo Pillai <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-03drm/amd/display: Add some functions for Panel ReplayTom Chung12-6/+234
[WHY] Prepare for enabling the Panel Replay feature [HOW] - Add some Panel Replay setting functions in DC - Add the Panel Replay resource in dcn35_resource.c - Add debug masks for Panel Replay Tested-by: Daniel Wheeler <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Reviewed-by: Leo Li <[email protected]> Signed-off-by: Tom Chung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-03Re-revert "drm/amd/display: Enable Replay for static screen use cases"Ivan Lipski2-30/+1
This reverts commit 44e60b14d5a72f91fd0bdeae8da59ae37a3ca8e5. Since, it causes a regression in which eDP displays with PSR support, but no Replay support (Sink support <= 0x03), fail to enable PSR and consequently all IGT amd_psr tests fail. So, revert this until a more suitable fix can be found. This got brought back accidently with the backmerge. Acked-by: Leo Li <[email protected]> Signed-off-by: Ivan Lipski <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-01-03drm/amd/display: Fixing stream allocation regressionRelja Vojvodic1-1/+1
For certain dual display configs that had one display using a 1080p mode, the DPM level used to drive the configs regressed from DPM 0 to DPM 3. This was caused by a missing check that should have only limited the pipe segments on non-phantom pipes. This caused issues with detile buffer allocation, which dissallow subvp from being used Tested-by: Daniel Wheeler <[email protected]> Reviewed-by: Dillon Varone <[email protected]> Reviewed-by: Martin Leung <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Relja Vojvodic <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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