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2023-03-15drm/amd/display: Remove OTG DIV register write for Virtual signals.Saaem Rizvi1-1/+1
[WHY] Hot plugging and then hot unplugging leads to k1 and k2 values to change, as signal is detected as a virtual signal on hot unplug. Writing these values to OTG_PIXEL_RATE_DIV register might cause primary display to blank (known hw bug). [HOW] No longer write k1 and k2 values to register if signal is virtual, we have safe guards in place in the case that k1 and k2 is unassigned so that an unknown value is not written to the register either. Cc: [email protected] Cc: Mario Limonciello <[email protected]> Reviewed-by: Samson Tam <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Saaem Rizvi <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-14drm/amd/display: Do not set DRR on pipe CommitWesley Chalmers1-3/+0
[WHY] Writing to DRR registers such as OTG_V_TOTAL_MIN on the same frame as a pipe commit can cause underflow. Cc: [email protected] Cc: Mario Limonciello <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Wesley Chalmers <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-14drm/amd/display: Take FEC Overhead into Timeslot CalculationFangzhi Zuo2-8/+27
8b/10b encoding needs to add 3% fec overhead into the pbn. In the Synapcis Cascaded MST hub, the first stage MST branch device needs the information to determine the timeslot count for the second stage MST branch device. Missing this overhead will leads to insufficient timeslot allocation. Cc: [email protected] Cc: Mario Limonciello <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Fangzhi Zuo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-14drm/amd/display: Add Validate BW for USB4 LinksMustapha Ghaddar2-0/+48
[WHY] To validate the BW used for DPIAs per HostRouter [HOW] Add the Validate function in C source file Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Mustapha Ghaddar <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-14drm/amd/display: Remove OTG DIV register write for Virtual signals.Saaem Rizvi1-1/+1
[WHY] Hot plugging and then hot unplugging leads to k1 and k2 values to change, as signal is detected as a virtual signal on hot unplug. Writing these values to OTG_PIXEL_RATE_DIV register might cause primary display to blank (known hw bug). [HOW] No longer write k1 and k2 values to register if signal is virtual, we have safe guards in place in the case that k1 and k2 is unassigned so that an unknown value is not written to the register either. Cc: [email protected] Cc: Mario Limonciello <[email protected]> Reviewed-by: Samson Tam <[email protected]> Reviewed-by: Alvin Lee <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Saaem Rizvi <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-14drm/amd/display: convert link.h functions to function pointer styleWenjing Liu52-393/+806
[Why & How] All dc subcomponents should call another dc component via function pointers stored in a component structure. This is part of dc coding convention since the beginning. The reason behind this is to improve encapsulation and polymorphism. The function contract is extracted into a single link service structure defined in link.h header file and implemented only in link_factory.c instead of spreading across multiple files in link component file structure. Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-14drm/amd/display: reset the scaler boundary modeZhikai Zhai3-0/+10
[WHY] The VBIOS select the black boundary mode when using auto scale mode. But it doesn't recover if there is no reset. [HOW] Clean the scaler boundary mode to default edge in the manual scale mode. Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Zhikai Zhai <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-14drm/amd/display: Use DPP inst instead of pipe idx for DPP DTO programmingAlvin Lee2-2/+39
[Description] - For pipe harvesting cases we must use DPP inst instead of pipe index for DPP related programming Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-14drm/amd/display: default values for luminance range if they are 0Swapnil Patel1-2/+8
[why] Currently if invalid luminescence range is reported in edid, then the driver doesn't have default range to fallback to. [How] Add default range if, the range is 0. Reviewed-by: Roman Li <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Swapnil Patel <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-14drm/amd/display: Add DSC Support for Synaptics Cascaded MST HubFangzhi Zuo2-0/+31
Traditional synaptics hub has one MST branch device without virtual dpcd. Synaptics cascaded hub has two chained MST branch devices. DSC decoding is performed via root MST branch device, instead of the second MST branch device. Reviewed-by: Hersen Wu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Fangzhi Zuo <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-14drm/amd/display: Write to correct dirty_rectBenjamin Cheng1-3/+3
When FB_DAMAGE_CLIPS are provided in a non-MPO scenario, the loop does not use the counter i. This causes the fill_dc_dity_rect() to always fill dirty_rects[0], causing graphical artifacts when a damage clip aware DRM client sends more than 1 damage clip. Instead, use the flip_addrs->dirty_rect_count which is incremented by fill_dc_dirty_rect() on a successful fill. Fixes: 30ebe41582d1 ("drm/amd/display: add FB_DAMAGE_CLIPS support") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2453 Signed-off-by: Benjamin Cheng <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 6.1.x
2023-03-14drm/amd/display: Fix HDCP failing to enable after suspendBhawanpreet Lakha1-1/+1
[Why] On resume some displays are not ready for HDCP, so they will fail if we start the hdcp authentintication too soon. Add a delay so that the displays can be ready before we start. NOTE: Previoulsy this delay was set to 3 seconds but it was causing issues with compliance, 2 seconds should enough for compliance and the s3 resume case. [How] Change the Delay to 2 seconds. Reviewed-by: Aurabindo Pillai <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Bhawanpreet Lakha <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-13drm/amd/display: use a more accurate check in dm_helpers_dp_read_dpcd()Hamza Mahfooz1-2/+2
We should be checking if drm_dp_dpcd_read() returns the size that we are asking it to read instead of just checking if it is greater than zero. So, compare the return value of drm_dp_dpcd_read() to the requested read size. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-13drm/amd/display: Write to correct dirty_rectBenjamin Cheng1-3/+3
When FB_DAMAGE_CLIPS are provided in a non-MPO scenario, the loop does not use the counter i. This causes the fill_dc_dity_rect() to always fill dirty_rects[0], causing graphical artifacts when a damage clip aware DRM client sends more than 1 damage clip. Instead, use the flip_addrs->dirty_rect_count which is incremented by fill_dc_dirty_rect() on a successful fill. Fixes: 30ebe41582d1 ("drm/amd/display: add FB_DAMAGE_CLIPS support") Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/2453 Signed-off-by: Benjamin Cheng <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-13drm/amd/display: Fix HDCP failing to enable after suspendBhawanpreet Lakha1-1/+1
[Why] On resume some displays are not ready for HDCP, so they will fail if we start the hdcp authentintication too soon. Add a delay so that the displays can be ready before we start. NOTE: Previoulsy this delay was set to 3 seconds but it was causing issues with compliance, 2 seconds should enough for compliance and the s3 resume case. [How] Change the Delay to 2 seconds. Reviewed-by: Aurabindo Pillai <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Bhawanpreet Lakha <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-13drm/amd/display: add sysfs entry to read PSR residency from firmwareShirish S1-0/+20
[Why] Currently there aren't any methods to determine PSR state residency. [How] create a sysfs entry for reading residency and internally hook it up to existing functionality of reading PSR residency from firmware. [Hamza: dropped the link.h include and made checkpatch happy] Signed-off-by: Shirish S <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-13drm/amd/display: Use swap() instead of open coding itJiapeng Chong1-6/+2
Swap is a function interface that provides exchange function. To avoid code duplication, we can use swap function. ./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c:359:57-58: WARNING opportunity for swap(). Reported-by: Abaci Robot <[email protected]> Link: https://bugzilla.openanolis.cn/show_bug.cgi?id=4448 Signed-off-by: Jiapeng Chong <[email protected]> Signed-off-by: Hamza Mahfooz <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-08drm/amd/display: remove unused variable availableTom Rix1-8/+0
With gcc and W=1, there is this error drivers/gpu/drm/amd/amdgpu/../display/dc/link/protocols/link_dp_dpia_bw.c:297:13: error: variable ‘available’ set but not used [-Werror=unused-but-set-variable] 297 | int available = 0; | ^~~~~~~~~ Since available is unused, remove it. Signed-off-by: Tom Rix <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-08drm/amd/display: remove unused variable res_poolTom Rix1-2/+0
With gcc and W=1, there is this error drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_mst_types.c:1214:31: error: variable ‘res_pool’ set but not used [-Werror=unused-but-set-variable] 1214 | struct resource_pool *res_pool; | ^~~~~~~~ Since res_pool is unused, remove it. Signed-off-by: Tom Rix <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-08drm/amd/display: add prefix to amdgpu_dm_crtc.h functionsDavid Tadokoro3-36/+36
Some amdgpu_dm_crtc.h functions didn't have names that indicated where they were declared. To better filter results in debug tools like ftrace, prefix these functions with 'amdgpu_dm_crtc_'. Signed-off-by: David Tadokoro <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-08Revert "drm/amd/display: Pass proper parent for DM backlight device ↵Alex Deucher1-6/+4
registration" This reverts commit d24b77e444bef83155557ebf4c2b3c551f198926. This does not work as expected. Bug: https://gitlab.gnome.org/GNOME/gnome-settings-daemon/-/issues/730 Signed-off-by: Alex Deucher <[email protected]>
2023-03-08drm/amd/display: remove legacy fields of dc_plane_cap structDavid Tadokoro17-36/+0
The fields blends_with_above and blends_with_below of struct dc_plane_cap (defined in dc/dc.h) are boolean and set to true by default. All instances of a dc_plane_cap maintain the default values of both. Also, there is only one if statement that checks those fields and there would be the same effect if it was deleted (assuming that those fields are always going to be true). For this reason, considering both fields as legacy ones, this commit removes them and the aforementioned if statement. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: David Tadokoro <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-08Revert "drm/amdgpu/display: change pipe policy for DCN 2.1"Alex Deucher1-1/+1
This reverts commit fa458eb10dc7218146a84e6d2e072424e64d188a. The issue is no longer present even with this commit present as verified by the original reporter. Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Link: https://gitlab.freedesktop.org/drm/amd/-/issues/1849#note_1759599 Signed-off-by: Rodrigo Siqueira <[email protected]>
2023-03-08drivers/gpu: fix typo in commentHusain Alshehhi1-9/+9
Replace "isntance" with "instance". Signed-off-by: Husain Alshehhi <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-08drm/amd/display: add prefix to amdgpu_dm_plane.h functionsDavid Tadokoro3-23/+23
The amdgpu_dm_plane.h functions didn't have names that indicated where they were declared. To better filter results in debug tools like ftrace, prefix these functions with 'amdgpu_dm_plane_'. Note that we may want to make this same change in other files like amdgpu_dm_crtc.h. Signed-off-by: David Tadokoro <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: Update clock table to include highest clock settingSwapnil Patel1-1/+18
[Why] Currently, the clk manager matches SocVoltage with voltage from fused settings (dfPstate clock table). And then corresponding clocks are selected. However in certain situations, this leads to clk manager not including at least one entry with highest supported clock setting. [How] Update the clk manager to include at least one entry with highest supported clock setting. Reviewed-by: Pavle Kotarac <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Swapnil Patel <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: change several dcn30 variables storage-class-specifier to ↵Tom Rix3-3/+3
static smatch reports these similar problems in dcn30 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_dwb.c:223:25: warning: symbol 'dcn30_dwbc_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_mmhubbub.c:214:28: warning: symbol 'dcn30_mmhubbub_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dcn30/dcn30_mpc.c:1402:24: warning: symbol 'dcn30_mpc_funcs' was not declared. Should it be static? All of these are only used in their definition file, so they should be static Signed-off-by: Tom Rix <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: change several dcn20 variables storage-class-specifier to ↵Tom Rix4-4/+4
static smatch reports these similar problems in dcn20 drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dsc.c:53:24: warning: symbol 'dcn20_dsc_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_dwb.c:304:25: warning: symbol 'dcn20_dwbc_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_mmhubbub.c:300:28: warning: symbol 'dcn20_mmhubbub_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dcn20/dcn20_mpc.c:545:24: warning: symbol 'dcn20_mpc_funcs' was not declared. Should it be static? All of these are only used in their definition file, so they should be static Signed-off-by: Tom Rix <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: change several dcn201 variables storage-class-specifier to ↵Tom Rix3-4/+4
static smatch reports these similar problems in dcn201 drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn201/dcn201_clk_mgr.c:165:22: warning: symbol 'dcn201_funcs' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:77:30: warning: symbol 'dcn201_ip' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_resource.c:139:37: warning: symbol 'dcn201_soc' was not declared. Should it be static? drivers/gpu/drm/amd/amdgpu/../display/dc/dcn201/dcn201_mpc.c:79:24: warning: symbol 'dcn201_mpc_funcs' was not declared. Should it be static? All of these are only used in their definition file, so they should be static Signed-off-by: Tom Rix <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: 3.2.226Aric Cyr1-1/+1
In this new version there are two major changes: 1) Transitioning to the new DC commit sequence There is an extended effort to migrate to the new DC commit sequence that better adheres to the DCN hardware constraints. Most of the code was upstreamed already but not connected to amdgpu_dm, and in this new DC version, our DM finally started to use it for all ASICs. This should improve stability and enable us to improve how pipe split works. 2) Drop old CONFIG_DRM_AMD_DC_DCN in favor of new CONFIG_DRM_AMD_DC_FP For historical reasons, we created CONFIG_DRM_AMD_DC_DCN to isolate FPU-related code to only be used for DCN. Over the years, we lost control over this guard, and it was spread in multiple areas. In this new DC version, there is an effort to remove all unnecessary CONFIG_DRM_AMD_DC_DCN and replace the others for CONFIG_DRM_AMD_DC_FP, which better describes which type of code this guard is intended for. Finally, this version brings along the following: - Enable HostVM based on rIOMMU active - Keep PHY active for dp confi - Improves Z8 - Update clock table - Code and directives clean up Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Aric Cyr <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: Ensure that planes are in the same orderRodrigo Siqueira1-0/+15
The function dc_update_planes_and_stream handles multiple cases where DC needs to remove and add planes in the commit tail phase. After Linux started to use this function, some of the IGT kms_plane started to fail; one good example to illustrate why the new sequence regressed IGT is the subtest plane-position-hole which has the following diagram as a template: +--------------------+ +-----------------------+ | +-----+ | | +-----+ | | | | | | | +-----+ | | | +--+ | ==> | | | | | | | |__| | | +-|---+ | | | | | +-----+ | | | | | +--------------------+ +-----------------------+ (a) Final image (b) Composed image IGT expects image (a) as the final result of two plane compositions as described in figure (b). After the migration to the new sequence, the last plane order is changed, and DC generates the following image: +---------------------+ | +-----+ | | | | | | | | | | +-----+ | | | +---------------------+ Notice that the generated image by DC is different because the small square that should be composed on top of the primary plane is below the primary plane. For this reason, the CRC will mismatch with the expected value. Since the function dc_add_all_planes_for_stream re-append all the new planes back to the dc_validation_set, this commit ensures that the original sequence is maintained. After this change, all CI tests in all ASICs start to pass again. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Suggested-by: Melissa Wen <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: Add wrapper to call planes and stream updateRodrigo Siqueira1-10/+41
[Why & How] This commit is part of a sequence of changes that replaces the commit sequence used in the DC with a new one. As a result of this transition, we moved some specific parts from the commit sequence and brought them to amdgpu_dm. This commit adds a wrapper inside DM that enable our drivers to do any necessary preparation or change before we offload the plane/stream update to DC. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: Use DC_LOG_DC in the trasform pixel functionRodrigo Siqueira1-3/+2
[Why & How] DC now uses a new commit sequence which is more robust since it addresses cases where we need to reorganize pipes based on planes and other parameters. As a result, this new commit sequence reset the DC state by cleaning plane states and re-creating them accordingly with the need. For this reason, the dce_transform_set_pixel_storage_depth can be invoked after a plane state is destroyed and before its re-creation. In this situation and on DCE devices, DC will hit a condition that will trigger a dmesg log that looks like this: Console: switching to colour frame buffer device 240x67 ------------[ cut here ]------------ [..] Hardware name: System manufacturer System Product Name/PRIME X370-PRO, BIOS 5603 07/28/2020 RIP: 0010:dce_transform_set_pixel_storage_depth+0x3f8/0x480 [amdgpu] [..] RSP: 0018:ffffc9000202b850 EFLAGS: 00010293 RAX: ffffffffa081d100 RBX: ffff888110790000 RCX: 000000000000000c RDX: ffff888100bedbf8 RSI: 0000000000001a50 RDI: ffff88810463c900 RBP: 0000000000000000 R08: 0000000000000000 R09: 0000000000000007 R10: 0000000000000001 R11: 0000000000000f00 R12: ffff88810f500010 R13: ffff888100bedbf8 R14: ffff88810f515688 R15: 0000000000000000 FS: 00007ff0159249c0(0000) GS:ffff88840e940000(0000) knlGS:0000000000000000 CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 CR2: 00007ff01528e550 CR3: 0000000002a10000 CR4: 00000000003506e0 Call Trace: <TASK> ? dm_write_reg_func+0x21/0x80 [amdgpu 340dadd3f7c8cf4be11cf0bdc850245e99abe0e8] dc_stream_set_dither_option+0xfb/0x130 [amdgpu 340dadd3f7c8cf4be11cf0bdc850245e99abe0e8] amdgpu_dm_crtc_configure_crc_source+0x10b/0x190 [amdgpu 340dadd3f7c8cf4be11cf0bdc850245e99abe0e8] amdgpu_dm_atomic_commit_tail+0x20a8/0x2a90 [amdgpu 340dadd3f7c8cf4be11cf0bdc850245e99abe0e8] ? free_unref_page_commit+0x98/0x170 ? free_unref_page+0xcc/0x150 commit_tail+0x94/0x120 drm_atomic_helper_commit+0x10f/0x140 drm_atomic_commit+0x94/0xc0 ? drm_plane_get_damage_clips.cold+0x1c/0x1c drm_client_modeset_commit_atomic+0x203/0x250 drm_client_modeset_commit_locked+0x56/0x150 drm_client_modeset_commit+0x21/0x40 drm_fb_helper_lastclose+0x42/0x70 amdgpu_driver_lastclose_kms+0xa/0x10 [amdgpu 340dadd3f7c8cf4be11cf0bdc850245e99abe0e8] drm_release+0xda/0x110 __fput+0x89/0x240 task_work_run+0x5c/0x90 do_exit+0x333/0xae0 do_group_exit+0x2d/0x90 __x64_sys_exit_group+0x14/0x20 do_syscall_64+0x5b/0x80 ? exit_to_user_mode_prepare+0x1e/0x140 entry_SYSCALL_64_after_hwframe+0x44/0xae RIP: 0033:0x7ff016ceaca1 Code: Unable to access opcode bytes at RIP 0x7ff016ceac77. RSP: 002b:00007ffe7a2357e8 EFLAGS: 00000246 ORIG_RAX: 00000000000000e7 RAX: ffffffffffffffda RBX: 00007ff016e15a00 RCX: 00007ff016ceaca1 RDX: 000000000000003c RSI: 00000000000000e7 RDI: 0000000000000000 RBP: 0000000000000000 R08: ffffffffffffff78 R09: 0000000000000000 R10: 0000000000000000 R11: 0000000000000246 R12: 00007ff016e15a00 R13: 0000000000000000 R14: 00007ff016e1aee8 R15: 00007ff016e1af00 </TASK> Since this issue only happens in a transition state on DC, this commit replace BREAK_TO_DEBUGGER with DC_LOG_DC. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: Use dc_update_planes_and_streamRodrigo Siqueira1-15/+15
[Why & How] The old dc_commit_updates_for_stream lacks manipulation for many corner cases where the DC feature requires special attention; as a result, it starts to show its limitation (e.g., the SubVP feature is not supported by it, among other cases). To modernize and unify our internal API, this commit replaces the old dc_commit_updates_for_stream with dc_update_planes_and_stream, which has more features. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: Drop dc_commit_state in favor of dc_commit_streamsRodrigo Siqueira3-54/+3
[Why & How] There are two functions responsible for handling the DC commit state: dc_commit_state and dc_commit_streams. Both have the same goal, but dc_commit_streams surpess dc_commit_state in terms of completeness. For this reason, maintaining these two functions makes maintainability unnecessarily complicated. This commit replaces the old dc_commit_state in favor of dc_commit_streams, and removes the old dc_commit_state. Reviewed-by: Harry Wentland <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: Ensure vmin and vmax adjust for DCERodrigo Siqueira1-2/+3
[Why & How] In the commit 32953485c558 ("drm/amd/display: Do not update DRR while BW optimizations pending"), a modification was added to avoid adjusting DRR if optimized bandwidth is set. This change was only intended for DCN, but one part of the patch changed the code path for DCE devices and caused regressions to the kms_vrr test. To address this problem, this commit adds a modification in which dc_stream_adjust_vmin_vmax will be fully executed in DCE devices. Fixes: 32953485c558 ("drm/amd/display: Do not update DRR while BW optimizations pending") Reviewed-by: Aric Cyr <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Rodrigo Siqueira <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: Pass tg and hubp inst instead of pipe index for SubVPAlvin Lee2-15/+23
[Description] - For pipe harvesting cases, the pipe index does not necessarily match up with the OTG instance, so pass index by OTG Instance instead - For pipe split cases pass HUBP instance, since the split index is only used for HUBP programming - Also check for OPP ID when accessing opp for pipe harvesting cases Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: Enable HostVM based on rIOMMU activeGabe Teeger1-0/+4
[Why] There is underflow and flickering occuring. The underflow stops when hostvm is forced to active. According to policy, hostvm should be enabled if riommu is active, but this is not taken into account when deciding whether to enable hostvm. [What] For DCN314, set hostvm to true if riommu is active. Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Gabe Teeger <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: Pass the right info to drm_dp_remove_payloadWayne Lin1-7/+50
[Why & How] drm_dp_remove_payload() interface was changed. Correct amdgpu dm code to pass the right parameter to the drm helper function. Reviewed-by: Jerry Zuo <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: Update to correct min FCLK when construction BBAlvin Lee5-8/+17
[Description] - For min FCLK, choose the min of 300Mhz and PMFW requirement - Also only apply min DET check in DML for non-UR cases Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alvin Lee <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: Rename DCN config to FPHarry Wentland21-32/+32
[Why & How] The only reason we have the DCN config is for floating point support. Rename it to make that clear and (hopefully) avoid misuse of the config in the future. Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: Drop unnecessary DCN guardsHarry Wentland15-62/+16
[Why & How] DC is littered with many DCN guards that are not needed. Drop them. Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: Drop unnecessary DCN guardsHarry Wentland3-42/+0
[Why] DM is littered with DCN guards leading to frequent breakages on non-DCN builds when new code is added. [How] Remove all guards that are not needed. Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: Keep PHY active for dp configAgustin Gutierrez1-0/+5
[Why] Current hotplug sequence causes temporary hang at the re-entry of the optimized power state. [How] Keep a PHY active when detecting DP signal + DPMS active Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Agustin Gutierrez <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: Simplify register offsetsChris Park5-239/+0
[Why] Runtime initialization of register addresses define duplicate register offsets in resource file, and makes register offsets in sub-block defined for compile time initialization obsolete. [How] Remove obsolete sub block register offsets that is no longer referenced. Reviewed-by: Martin Leung <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Chris Park <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: replace all dc_link function call in link with link functionsWenjing Liu10-40/+46
[why] Link components should not reply on dc_link_exports to access link function in other link components. Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: move dc_link functions in protocols folder to dc_link_exportsWenjing Liu28-81/+486
[why] link component should only have one interface serving dc. [how] We are moving dc_link functions exposed to DM to dc_link_exports and unify link component interface in link.h with function pointer to match the style of other dc component. This is the third step to move dc_link functions under protocols folder to dc_link_exports. Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: link link_dp_dpia_bw.o in makefileWenjing Liu5-612/+68
[Why & How] - We have added link_dp_dpia_bw code but it is not currently added in makefile. We are adding this to makefile so it would be built. - Remove unused dc_link.h Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: move dc_link functions in link root folder to dc_link_exportsWenjing Liu6-10/+40
[why] link component should only have one interface serving dc. [how] We are moving dc_link functions exposed to DM to dc_link_exports and unify link component interface in link.h with function pointer to match the style of other dc component. This is the second step to move dc_link functions under link root folder to dc_link_exports. Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2023-03-07drm/amd/display: move dc_link functions in accessories folder to dc_link_exportsWenjing Liu11-58/+178
[why] link component should only have one interface serving dc. [how] We are moving dc_link functions exposed to DM to dc_link_exports and unify link component interface in link.h with function pointer to match the style of other dc component. This is the first step to move dc_link functions under accessories folder to dc_link_exports. Reviewed-by: Jun Lei <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Wenjing Liu <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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