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2019-01-14drm/amd/display: Start using the new pp_smu interfaceFatemeh Darbehani1-77/+26
[Why] PPLib has impelemented the new pp_smu interface [How] Use the new functions if available instead of the old interface 'set_display_requirement' and 'dcn1_pplib_apply_display_requirements'. Signed-off-by: Fatemeh Darbehani <[email protected]> Reviewed-by: Fatemeh Darbehani <[email protected]> Acked-by: Leo Li <[email protected]> Acked-by: Su Chung <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: 3.2.11Steven Chiu1-1/+1
Signed-off-by: Steven Chiu <[email protected]> Reviewed-by: Yongqiang Sun <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: Compensate for XGMI SS downspread on dprefclkLeo Li6-10/+198
[Why] When XGMI is enabled, we need to adjust the dprefclk according to the WAFL link's spread spectrum info. This is for VG20 (DCE121) only. [How] dce_clk_mgr already stores SS info, currently being used by audio clock. Therefore, patch the clk_mgr's SS info with the xGMI SS info, if xGMI is enabled. For display clock, adjust it during dce12_update_clocks() before calling set_clock(). Since we rely on a mmhub register to reliably determine if xGMI is enabled, the patching step needs to happen after resource_construct() has initialized the hardware sequencer. Signed-off-by: Leo Li <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: Fix driver load crash in amdgpu_dmLeo Li4-24/+35
[Why] This fixes an regression introduced by: drm/amd/display: add stream ID and otg instance in dc_stream_state During driver initialization, a null pointer deref is raised. This is caused by searching for a stream status in the dc->current_state before the dc_state swap happens at the end of dc_commit_state_no_check(). Since the swap has not happened, the dc_state to be swapped in should be searched, and not dc->current_state. [How] Add a function that searches for the stream status within the given dc_state, instead of dc->current_state. Use that before the state swap happens in dc_commit_state_no_check(). Also remove duplicate occurrences of this function in amdgpu_dm.c. Signed-off-by: Leo Li <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: Use local variable instead of caching globalLeo Li1-22/+15
[Why] context->bw.dce.dispclk_khz is being cached into unpatched_clock, then restored at end of function call. This is needlessly complex [How] Instead, use a local patched_clock variable. Leave context->bw.dce.dispclk_khz alone. No functional change is intended. Signed-off-by: David Francis <[email protected]> Signed-off-by: Leo Li <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: Improve logging of validation failures during atomic_checkEric Bernstein5-2/+58
[Why] There are different reasons for Validation failure error during atomic_check [How] Add better logging of the reason for validation failure Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: Use 100 Hz precision for pipe pixel clocksKen Chalmers29-209/+206
[Why] Users would like more accurate pixel clocks, especially for fractional "TV" frame rates like 59.94 Hz. [How] Store and communicate pixel clocks with 100 Hz accuracy from dc_crtc_timing through to BIOS command table setpixelclock call. Signed-off-by: Ken Chalmers <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: Minor code cleanupSivapiriyanKumarasamy1-1/+1
[WHY] There is an extra null check for fs_params in the build_freesync_hdr function detected by Smatch. [HOW] 1) Remove the extra null check since it is checked in the caller. Signed-off-by: SivapiriyanKumarasamy <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: Remove stream_status->linkLeo Li1-5/+0
[Why] It's not being used anywhere. [How] Remove it. Signed-off-by: Leo Li <[email protected]> Reviewed-by: David Francis <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: 3.2.10Steven Chiu1-1/+1
Signed-off-by: Steven Chiu <[email protected]> Reviewed-by: Yongqiang Sun <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: Add backlight pwm debugfsDavid Francis3-2/+70
[Why] ABM enablement testing can be automated if a way of reading target and current hardware backlight is available [How] Expand debugfs interface with two new entries. Hook directly into dc interface. Units are as a fraction of 0x1000 = 100% Use the built-in amdgpu function for creating read-only debugfs files Signed-off-by: David Francis <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: add stream ID and otg instance in dc_stream_stateJun Lei4-0/+21
[why] stream ID allows DMs to avoid memory address comparisons to compare stream equality. otg_instance allows DC to more rigorously define when otg_instance can change. specifically, it is now defined to be only mutable when dc_stream_state changes. This is better than a "get status" function which prevents efficient caching of otherwise very stable information. [how] stream ID follows similar pattern to sink ID, which is already implemented otg_instance is an output which occurs on all dc_stream modification functions Signed-off-by: Jun Lei <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Aric Cyr <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: update DCN dml calcsDmytro Laktyushkin5-113/+11
DV have made updates to DCN dml which we need to pull in Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: Detach backlight from streamDavid Francis4-15/+3
[Why] Backlight is conceptually a property of links, not streams. All backlight programming is done on links, but there is a stream property bl_pwm_level that is used to restore backlight on dpms on and s3 resume. This is unnecessary, as backlight is already restored by hardware with no driver intervention. [How] Remove bl_pwm_level, and the stream argument to set_backlight Signed-off-by: David Francis <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Anthony Koo <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: Remove unused headersImad Syed1-4/+0
They're not being used, so remove them. Signed-off-by: Imad Syed <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: remove sink reference in dc_stream_stateJun Lei19-101/+103
[why] dc_stream_state containing a pointer to sink is poor design. Sink describes the display, and the specifications or capabilities it has. That information is irrelevant for dc_stream_state, which describes hardware state, and is generally used for hardware programming. It could further be argued that dc_sink itself is just a convenience dc provides, and DC should be perfectly capable of programming hardware without any dc_sinks (for example, emulated sinks). [how] Phase 1: Deprecate use of dc_sink pointer in dc_stream. Most references are trivial to remove, but some call sites are risky (such as is_timing_changed) with no obvious logical replacement. These will be removed in follow up change. Add dc_link pointer to dc_stream. This is the typical reason DC really needed sink pointer, and most call sites are replaced with this. DMs also need minor updates, as all 3 DMs leverage stream->sink for some functionality. this is replaced instead by a pointer to private data inside dc_stream_state, which is used by DMs as a quality of life improvment for some key functionality. it allows DMs to set pointers have to their own objects which associate OS objects to dc_stream_states (such as DisplayTarget and amdgpu_dm_connector). Without the private pointer, DMs would be forced to perform a lookup for callbacks. Signed-off-by: Jun Lei <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: David Francis <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: Add debug option to force fclk requestHugo Hu2-0/+5
[Why] So that we can adjust fclk for debugging purposes. [How] Add option to force adjust fclk request to pplib. Signed-off-by: Hugo Hu <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: update bw formula to v252Eric Yang1-9/+34
[why] There was a recent fix in the BW spreadsheet to allow timing with very large vblank. Need to be ported into driver. Signed-off-by: Eric Yang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Dmytro Laktyushkin <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: Fix issue with VLine interrupt not firingKrunoslav Kovac1-16/+9
[Why] We are not correctly handling the wrap around case. VLine interrupt is relative to position of VUpdate interrupt. Both VUpdate interrupt and VLine interrupt could possibly be in front porch or back porch. [How] Fix wraparound case by checking for line number that is greater than the VTOTAL of the OTG timing. In this case, the interrupt should occur on the next frame. Also fix some variable naming and remove some dead code. Signed-off-by: Krunoslav Kovac <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Leo Li <[email protected]> Acked-by: Tony Cheng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: add plane size change check conditionLewis Huang3-1/+9
[Why] Driver didn't check plane size and surface size is mismatch. It will cause pitch data incorrect. [How] Add condition to check is plane change and update surface Signed-off-by: Lewis Huang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: implement dc_init_callbacks to assign callback pointers ↵Wenjing Liu2-1/+11
after dc_create [why] Some components depend on dc to constuct but need to assign callback functions to dc. [how] Instead of assigning dc callback functions in dc_create, decouple the callback init to a standlone function after dc_create. This is currently a no-op. Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: Remove some extra bracesDmytro Laktyushkin1-4/+2
Remove braces around single-line conditionals Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Acked-by: Leo Li <[email protected]> Acked-by: Tony Cheng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: Add pixel clock values to dtn logsFatemeh Darbehani1-3/+6
[Why] To make sure future changes in DAL for SMU msgs will not change the current behaviour and to make sure clock registeres are programmed correctly based on SMU msgs that DAL sends. Signed-off-by: Fatemeh Darbehani <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Leo Li <[email protected]> Acked-by: Yongqiang Sun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: Fix runtime errors for diagnostic testsEric Bernstein8-64/+78
1) Rename and make public definition of input CSC matrix struct. 2) Make wm_read_state() function an interface of hubbub, and check if watermark registers exist before read/write to them. 3) Check if OTG_INTERLACE_CONTROL register exists before updating 4) Add dummy functions for set_input/output_transfer function to avoid errors due to differences in CM registers. 5) Added missing register field definition in header file Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: Expose hubp1_vready_workaround functionEric Bernstein2-1/+3
Expose this function for future use. Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: Add a PP_SMU_VER_MAX enumJun Lei1-1/+2
Signed-off-by: Jun Lei <[email protected]> Reviewed-by: Nevenko Stupar <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: 3.2.09Steven Chiu1-1/+1
Signed-off-by: Steven Chiu <[email protected]> Reviewed-by: Shahin Khayyer <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-11Merge drm/drm-next into drm-misc-nextMaxime Ripard62-1250/+2287
drm-next has been forwarded to 5.0-rc1, and we need it to apply the damage helper for dirtyfb series from Noralf Trønnes. Signed-off-by: Maxime Ripard <[email protected]>
2019-01-10drm/amdgpu/display: Keep malloc ref to MST portLyude Paul1-4/+7
Just like i915 and nouveau, it's a good idea for us to hold a malloc reference to the port here so that we never pass a freed pointer to any of the DP MST helper functions. Also, we stop unsetting aconnector->port in dm_dp_destroy_mst_connector(). There's literally no point to that assignment that I can see anyway. Signed-off-by: Lyude Paul <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: David Airlie <[email protected]> Cc: Jerry Zuo <[email protected]> Cc: Juston Li <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-01-10Merge tag 'drm-misc-next-2019-01-07-1' of ↵Dave Airlie2-10/+2
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 5.1: UAPI Changes: Cross-subsystem Changes: - Turn dma-buf fence sequence numbers into 64 bit numbers Core Changes: - Move to a common helper for the DP MST hotplug for radeon, i915 and amdgpu - i2c improvements for drm_dp_mst - Removal of drm_syncobj_cb - Introduction of an helper to create and attach the TV margin properties Driver Changes: - Improve cache flushes for v3d - Reflection support for vc4 - HDMI overscan support for vc4 - Add implicit fencing support for rockchip and sun4i - Switch to generic fbdev emulation for virtio Signed-off-by: Dave Airlie <[email protected]> [airlied: applied amdgpu merge fixup] From: Maxime Ripard <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20190107180333.amklwycudbsub3s5@flea
2019-01-08drm/amdgpu: Don't fail resume process if resuming atomic state failsLyude Paul1-3/+2
This is an ugly one unfortunately. Currently, all DRM drivers supporting atomic modesetting will save the state that userspace had set before suspending, then attempt to restore that state on resume. This probably worked very well at one point, like many other things, until DP MST came into the picture. While it's easy to restore state on normal display connectors that were disconnected during suspend regardless of their state post-resume, this can't really be done with MST because of the fact that setting up a downstream sink requires performing sideband transactions between the source and the MST hub, sending out the ACT packets, etc. Because of this, there isn't really a guarantee that we can restore the atomic state we had before suspend once we've resumed. This sucks pretty bad, but so far I haven't run into any compositors that this actually causes serious issues with. Most compositors will notice the hotplug we send afterwards, and then reprobe state. Since nouveau and i915 also don't fail the suspend/resume process due to failing to restore the atomic state, let's make amdgpu match this behavior. Better to resume the GPU properly, then to stop the process half way because of a potentially unavoidable atomic commit failure. Eventually, we'll have a real fix for this problem on the DRM level. But we've got some more important low-hanging fruit to deal with first. Signed-off-by: Lyude Paul <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Cc: Jerry Zuo <[email protected]> Cc: <[email protected]> # v4.15+ Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-01-08drm/amdgpu: Don't ignore rc from drm_dp_mst_topology_mgr_resume()Lyude Paul1-9/+23
drm_dp_mst_topology_mgr_resume() returns whether or not it managed to find the topology in question after a suspend resume cycle, and the driver is supposed to check this value and disable MST accordingly if it's gone-in addition to sending a hotplug in order to notify userspace that something changed during suspend. Currently, amdgpu just makes the mistake of ignoring the return code from drm_dp_mst_topology_mgr_resume() which means that if a topology was removed in suspend, amdgpu never notices and assumes it's still connected which leads to all sorts of problems. So, fix this by actually checking the rc from drm_dp_mst_topology_mgr_resume(). Also, reformat the rest of the function while we're at it to fix the over-indenting. Signed-off-by: Lyude Paul <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Cc: Jerry Zuo <[email protected]> Cc: <[email protected]> # v4.15+ Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-01-05Merge tag 'drm-next-2019-01-05' of git://anongit.freedesktop.org/drm/drmLinus Torvalds19-164/+304
Pull drm fixes from Dave Airlie: "Happy New Year, just decloaking from leave to get some stuff from the last week in before rc1: core: - two regression fixes for damage blob and atomic i915 gvt: - Some missed GVT fixes from the original pull amdgpu: - new PCI IDs - SR-IOV fixes - DC fixes - Vega20 fixes" * tag 'drm-next-2019-01-05' of git://anongit.freedesktop.org/drm/drm: (53 commits) drm: Put damage blob when destroy plane state drm: fix null pointer dereference on null state pointer drm/amdgpu: Add new VegaM pci id drm/ttm: Use drm_debug_printer for all ttm_bo_mem_space_debug output drm/amdgpu: add Vega20 PSP ASD firmware loading drm/amd/display: Fix MST dp_blank REG_WAIT timeout drm/amd/display: validate extended dongle caps drm/amd/display: Use div_u64 for flip timestamp ns to ms drm/amdgpu/uvd:Change uvd ring name convention drm/amd/powerplay: add Vega20 LCLK DPM level setting support drm/amdgpu: print process info when job timeout drm/amdgpu/nbio7.4: add hw bug workaround for vega20 drm/amdgpu/nbio6.1: add hw bug workaround for vega10/12 drm/amd/display: Optimize passive update planes. drm/amd/display: verify lane status before exiting verify link cap drm/amd/display: Fix bug with not updating VSP infoframe drm/amd/display: Add retry to read ddc_clock pin drm/amd/display: Don't skip link training for empty dongle drm/amd/display: Wait edp HPD to high in detect_sink drm/amd/display: fix surface update sequence ...
2018-12-25Merge tag 'drm-next-2018-12-14' of git://anongit.freedesktop.org/drm/drmLinus Torvalds91-3039/+4630
Pull drm updates from Dave Airlie: "Core: - shared fencing staging removal - drop transactional atomic helpers and move helpers to new location - DP/MST atomic cleanup - Leasing cleanups and drop EXPORT_SYMBOL - Convert drivers to atomic helpers and generic fbdev. - removed deprecated obj_ref/unref in favour of get/put - Improve dumb callback documentation - MODESET_LOCK_BEGIN/END helpers panels: - CDTech panels, Banana Pi Panel, DLC1010GIG, - Olimex LCD-O-LinuXino, Samsung S6D16D0, Truly NT35597 WQXGA, - Himax HX8357D, simulated RTSM AEMv8. - GPD Win2 panel - AUO G101EVN010 vgem: - render node support ttm: - move global init out of drivers - fix LRU handling for ghost objects - Support for simultaneous submissions to multiple engines scheduler: - timeout/fault handling changes to help GPU recovery - helpers for hw with preemption support i915: - Scaler/Watermark fixes - DP MST + powerwell fixes - PSR fixes - Break long get/put shmemfs pages - Icelake fixes - Icelake DSI video mode enablement - Engine workaround improvements amdgpu: - freesync support - GPU reset enabled on CI, VI, SOC15 dGPUs - ABM support in DC - KFD support for vega12/polaris12 - SDMA paging queue on vega - More amdkfd code sharing - DCC scanout on GFX9 - DC kerneldoc - Updated SMU firmware for GFX8 chips - XGMI PSP + hive reset support - GPU reset - DC trace support - Powerplay updates for newer Polaris - Cursor plane update fast path - kfd dma-buf support virtio-gpu: - add EDID support vmwgfx: - pageflip with damage support nouveau: - Initial Turing TU104/TU106 modesetting support msm: - a2xx gpu support for apq8060 and imx5 - a2xx gpummu support - mdp4 display support for apq8060 - DPU fixes and cleanups - enhanced profiling support - debug object naming interface - get_iova/page pinning decoupling tegra: - Tegra194 host1x, VIC and display support enabled - Audio over HDMI for Tegra186 and Tegra194 exynos: - DMA/IOMMU refactoring - plane alpha + blend mode support - Color format fixes for mixer driver rcar-du: - R8A7744 and R8A77470 support - R8A77965 LVDS support imx: - fbdev emulation fix - multi-tiled scalling fixes - SPDX identifiers rockchip - dw_hdmi support - dw-mipi-dsi + dual dsi support - mailbox read size fix qxl: - fix cursor pinning vc4: - YUV support (scaling + cursor) v3d: - enable TFU (Texture Formatting Unit) mali-dp: - add support for linear tiled formats sun4i: - Display Engine 3 support - H6 DE3 mixer 0 support - H6 display engine support - dw-hdmi support - H6 HDMI phy support - implicit fence waiting - BGRX8888 support meson: - Overlay plane support - implicit fence waiting - HDMI 1.4 4k modes bridge: - i2c fixes for sii902x" * tag 'drm-next-2018-12-14' of git://anongit.freedesktop.org/drm/drm: (1403 commits) drm/amd/display: Add fast path for cursor plane updates drm/amdgpu: Enable GPU recovery by default for CI drm/amd/display: Fix duplicating scaling/underscan connector state drm/amd/display: Fix unintialized max_bpc state values Revert "drm/amd/display: Set RMX_ASPECT as default" drm/amdgpu: Fix stub function name drm/msm/dpu: Fix clock issue after bind failure drm/msm/dpu: Clean up dpu_media_info.h static inline functions drm/msm/dpu: Further cleanups for static inline functions drm/msm/dpu: Cleanup the debugfs functions drm/msm/dpu: Remove dpu_irq and unused functions drm/msm: Make irq_postinstall optional drm/msm/dpu: Cleanup callers of dpu_hw_blk_init drm/msm/dpu: Remove unused functions drm/msm/dpu: Remove dpu_crtc_is_enabled() drm/msm/dpu: Remove dpu_crtc_get_mixer_height drm/msm/dpu: Remove dpu_dbg drm/msm: dpu: Remove crtc_lock drm/msm: dpu: Remove vblank_requested flag from dpu_crtc drm/msm: dpu: Separate crtc assignment from vblank enable ...
2018-12-20drm/amd/display: Fix MST dp_blank REG_WAIT timeoutJerry (Fangzhi) Zuo1-2/+2
Need to blank stream before deallocate MST payload. [drm:generic_reg_wait [amdgpu]] *ERROR* REG_WAIT timeout 10us * 3000 tries - dce110_stream_encoder_dp_blank line:944 ------------[ cut here ]------------ WARNING: CPU: 0 PID: 2201 at /var/lib/dkms/amdgpu/18.50-690240/build/amd/amdgpu/../display/dc/dc_helper.c:249 generic_reg_wait+0xe7/0x160 [amdgpu] Call Trace: dce110_stream_encoder_dp_blank+0x11c/0x180 [amdgpu] core_link_disable_stream+0x40/0x230 [amdgpu] ? generic_reg_update_ex+0xdb/0x130 [amdgpu] dce110_reset_hw_ctx_wrap+0xb7/0x1f0 [amdgpu] dce110_apply_ctx_to_hw+0x30/0x430 [amdgpu] ? dce110_apply_ctx_for_surface+0x206/0x260 [amdgpu] dc_commit_state+0x2ba/0x4d0 [amdgpu] amdgpu_dm_atomic_commit_tail+0x297/0xd70 [amdgpu] ? amdgpu_bo_pin_restricted+0x58/0x260 [amdgpu] ? wait_for_completion_timeout+0x1f/0x120 ? wait_for_completion_interruptible+0x1c/0x160 commit_tail+0x3d/0x60 [drm_kms_helper] drm_atomic_helper_commit+0xf6/0x100 [drm_kms_helper] drm_atomic_connector_commit_dpms+0xe5/0xf0 [drm] drm_mode_obj_set_property_ioctl+0x14f/0x250 [drm] drm_mode_connector_property_set_ioctl+0x2e/0x40 [drm] drm_ioctl+0x1e0/0x430 [drm] ? drm_mode_connector_set_obj_prop+0x70/0x70 [drm] ? ep_read_events_proc+0xb0/0xb0 ? ep_scan_ready_list.constprop.18+0x1e6/0x1f0 ? timerqueue_add+0x52/0x80 amdgpu_drm_ioctl+0x49/0x80 [amdgpu] do_vfs_ioctl+0x90/0x5f0 SyS_ioctl+0x74/0x80 do_syscall_64+0x74/0x140 entry_SYSCALL_64_after_hwframe+0x3d/0xa2 ---[ end trace 3ed7b77a97d60f72 ]--- Signed-off-by: Jerry (Fangzhi) Zuo <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Acked-by: Harry Wentland <[email protected]> Acked-by: Alex Deucher <[email protected]> Tested-by: Lyude Paul <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2018-12-20drm/amd/display: validate extended dongle capsWenjing Liu1-1/+2
[why] Some dongle doesn't have a valid extended dongle caps, but we still set the extended dongle caps to be valid. This causes validation fails for all timing. [how] If no dp_hdmi_max_pixel_clk is provided, don't use extended dongle caps. Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Abdoulaye Berthe <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-20drm/amd/display: Use div_u64 for flip timestamp ns to msNicholas Kazlauskas1-1/+4
Resolves __udivdi3 missing errors when building for i386. Fixes: 6378ef012ddc ("drm/amd/display: Add below the range support for FreeSync") Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: Optimize passive update planes.Yongqiang Sun1-3/+0
[Why] passive update planes still spends a litte more time on some cases. [How] Remove unnecessary trace which involving in some register read. Disable debug output for release build. Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: verify lane status before exiting verify link capWenjing Liu2-119/+127
[why] DP LL CTS1.4 4.3.2.1 test failure. [how] The failure is caused by not handling DP link loss hpd short pusle during set mode. The change is to read link status before set mode link training. If link is lost, re-verify link caps. Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: Fix bug with not updating VSP infoframeSivapiriyanKumarasamy1-1/+2
[WHY] Currently, when the VSP infopacket is rebuilt in DM, it is not updated when being programmed in encoder. [HOW] Add new VSP case for update_info_frame Signed-off-by: SivapiriyanKumarasamy <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Krunoslav Kovac <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: Add retry to read ddc_clock pinPaul Hsieh1-6/+17
[WHY] On customer board, there is one pluse (1v , < 1ms) on DDC_CLK pin when plug / unplug DP cable. Driver will read it and config DP to HDMI/DVI dongle. [HOW] If there is a real dongle, DDC_CLK should be always pull high. Try to read again to recovery this special case. Retry times = 3. Need additional 3ms to detect DP passive dongle(3 failures) Signed-off-by: Paul Hsieh <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: Don't skip link training for empty dongleEric Yang1-2/+16
[Why] Skipping initial link training will result in no verified link cap for mode enumeration. Some versions of the BIOS seem to have PHY programming sequence issue as well if initial link training is skipped, resulting in a softlock in BIOS command table. [How] Identify the empty dongle hotplug case, and still do initial link training. Signed-off-by: Eric Yang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: Wait edp HPD to high in detect_sinkDale Zhao1-0/+3
[Why] In 99% user case, edp will be post by vbios. In 1% / current case: Lenovo don't light up edp panel in vbios post stage, vbios won't be lit up. Thus in dal when we init DCN 10 hw, we power up edp, then we start detect_sink, but internal time is too short, when we detect it, HPD is still low, so we don't detect the edp, and edp shows black. [How] When we init hw, we wait edp HPD to high after power up edp. Signed-off-by: Dale Zhao <[email protected]> Reviewed-by: Eric Yang <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: fix surface update sequenceDmytro Laktyushkin1-2/+4
An earlier change added update of interdependent dlg/ttu params for pipes not being updated in the current call. The code fails to check if the other pipes are actually active yet causing an assert. This change adds a check for surface presence on the pipes before updating the interdepenednt params. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Nikola Cornij <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: fix YCbCr420 blank colorEric Yang2-1/+19
[Why] YCbCr420 packing format uses two chanels for luma, and 1 channel for both chroma component. Our previous implementation did not account for this and results in every other pixel having very high luma value, showing greyish color instead of black. YCbCr444 = <Y1, Cb1, Cr1>; <Y2, Cb2, Cr2> ..... YCbCr420 = <Y1, Y2, Cb1>; <Y3, Y4, Cr1> ..... [How] Program the second channel with the black color value for luma as well. Signed-off-by: Eric Yang <[email protected]> Reviewed-by: Hugo Hu <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: Warn instead of error on REG_WAIT timeoutDavid Francis1-2/+2
[Why] DC warns when a REG_WAIT takes a while and full-on errors with stack dump on REG_WAIT timeout. Most of the time it isn't a real issue. [How] Make DC cool its jets - taking a while is a debug message (because it is not something that normal users should need to be aware of), and timeouts are warnings (because it technically shouldn't happen, but it's not a big deal if it does) Signed-off-by: David Francis <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: move AYCrCb8888 format to video sectionDmytro Laktyushkin1-1/+1
This is a dual channel format and should be treated like other video formats Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: Don't log error if we have no connectorsHarry Wentland1-4/+0
[Why] In certain configurations, such as PX configs or some Vega20 parts DC gets created without connectors. [How] Drop the dm_error print when no connectors. Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: Add functionality to get XGMI SS infoLeo Li2-0/+16
[Why] When XGMI is enabled, the DP reference clock needs to be adjusted according to the XGMI spread spectrum percentage and mode. But first, we need the ability to fetch this info. [How] Within the BIOS parser, Read from vBIOS when XGMI SS info is requested. In addition, diags build uses include_legacy/atomfirmware.h for the smu_info_v3_3 table headers. Update that as well. Signed-off-by: Leo Li <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Tony Cheng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-12-18drm/amd/display: Add DCE_VERSION_12_1 enum for Vega 20Leo Li6-1/+10
[Why] We'll need a way to differentiate Vega 20 in DC [How] Add a DCE_VERSION_12_1 enum, which will be returned as the DC version if the ASIC used is a Vega 20. Signed-off-by: Leo Li <[email protected]> Reviewed-by: David Francis <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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