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2020-11-04drm/amd/display: fix psr panel lightupRoman Li1-1/+1
[Why] The change for correct asic type check caused a psr regression due to incorrect chip family id for Raven. [How] Use correct family id. Signed-off-by: Roman Li <roman.li@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amdgpu/display: fix warnings when CONFIG_DRM_AMD_DC_DCN is not setAlex Deucher1-1/+4
Properly protect the relevant code with CONFIG_DRM_AMD_DC_DCN. Fixes: 0b08c54bb7a3 ("drm/amd/display: Fix the display corruption issue on Navi10") Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd: fix typoesBernard Zhao1-1/+1
Fix typoes. Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Bernard Zhao <bernard@vivo.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: fix the NULL pointer that missed set_disp_pattern_generator ↵Huang Rui1-0/+1
callback This patch is to fix the NULL pointer that missed set_disp_pattern_generator callback on DCN301 [ 505.054167] BUG: kernel NULL pointer dereference, address: 0000000000000000 [ 505.054176] #PF: supervisor instruction fetch in kernel mode [ 505.054181] #PF: error_code(0x0010) - not-present page [ 505.054185] PGD 0 P4D 0 [ 505.054199] Oops: 0010 [#1] SMP NOPTI [ 505.054211] CPU: 6 PID: 1306 Comm: modprobe Tainted: G W OE 5.9.0-rc5-custom #1 [ 505.054216] Hardware name: AMD Chachani-VN/Chachani-VN, BIOS WCH0A29N_RAPV16.FD 10/29/2020 [ 505.054225] RIP: 0010:0x0 [ 505.054234] Code: Bad RIP value. [ 505.054239] RSP: 0018:ffffb88541c66f60 EFLAGS: 00010206 [ 505.054245] RAX: 0000000000000000 RBX: ffff912836070000 RCX: 0000000000000003 [ 505.054248] RDX: 000000000000000c RSI: ffff9128365001e8 RDI: ffff912836070000 [ 505.054252] RBP: ffffb88541c66fd8 R08: 0000000000000002 R09: ffffb88541c66fa2 [ 505.054265] R10: 0000000000009580 R11: 0000000000000008 R12: ffff9128365001e8 [ 505.054272] R13: 000000000000000c R14: 0000000000000438 R15: ffff9128a48bd000 [ 505.054279] FS: 00007f09f999f540(0000) GS:ffff9128b3f80000(0000) knlGS:0000000000000000 [ 505.054284] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 505.054288] CR2: ffffffffffffffd6 CR3: 00000002db98c000 CR4: 0000000000350ee0 [ 505.054291] Call Trace: [ 505.055024] dcn20_blank_pixel_data+0x148/0x260 [amdgpu] [ 505.055730] dcn20_enable_stream_timing+0x381/0x47c [amdgpu] [ 505.056641] dce110_apply_ctx_to_hw+0x337/0x577 [amdgpu] [ 505.056667] ? put_object+0x2f/0x40 [ 505.057329] dc_commit_state+0x4b3/0x9d0 [amdgpu] [ 505.058030] amdgpu_dm_atomic_commit_tail+0x405/0x1ec6 [amdgpu] [ 505.058053] ? update_stack_state+0x103/0x170 [ 505.058071] ? __module_text_address+0x12/0x60 Signed-off-by: Huang Rui <ray.huang@amd.com> Tested-by: Changfeng <Changfeng.Zhu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amdgpu: apply dm_pp_notify_wm_clock_changes() for Polaris onlyEvan Quan1-1/+6
Will expand it to other ASICs after verified. Signed-off-by: Evan Quan <evan.quan@amd.com> Acked-and-tested-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: Tune min clk values for MPO for RVPratik Vishwakarma1-3/+27
[Why] Incorrect values were resulting in flash lines when MPO was enabled and system was left idle. [How] Increase min clk values only when MPO is enabled and display is active to not affect S3 power. Signed-off-by: Pratik Vishwakarma <Pratik.Vishwakarma@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: fix recout calculation for left side clipDmytro Laktyushkin1-0/+4
Recout calculation does not corrrectly handle plane clip rect that extends beyond the left most border of stream source rect. This change adds handling by truncating the invisible clip rect. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Hersen Wu <hersenxs.wu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: 3.2.110Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: [FW Promotion] Release 0.0.40Anthony Koo1-2/+9
[Header Changes] - Add command for retrieving PSR residency - Add command for forcing PSR static Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: Add missing pflip irqBhawanpreet Lakha1-2/+2
If we have more than 4 displays we will run into dummy irq calls or flip timout issues. Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: set hdcp1 wa re-auth delay to 200msJake Wang1-1/+1
[Why] Fail and restart timing for HDCP1 retry occurs too quickly. This would cause some MST monitors to show black screen. [How] Adjusted timing of fail and restart to 200ms. Signed-off-by: Jake Wang <haonan.wang2@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: Revert HUBP blank behaviour for nowJoshua Aberback2-26/+3
[Why] Commit "Blank HUBP during pixel data blank for DCN30 v2" modifies HW behaviour during blank, which might have OS dependencies. We need to assess the impact on amdgpu_dm and only re-enable HUBP blanking when all necessary changes are understood. [How] - revert functional changes - leave architectural changes intact Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: WA to ensure MUX chip gets SUPPORTED_LINK_RATES of eDPDale Zhao1-0/+10
[Why] Customer make a request to add this WA by driver. Some MUX chips will power down with eDP 1.4 panel and lose previous supported link rates(DPCD 0x010) in customer's hybrid-GPU designs. As a result, during sleep resuming and screen turns on from idle, link training will be performed incorrectly and eDP will flicker or black screen. These MUX chips need source to read DPCD 0x010 again during LKT so that it can restore supported link rates of panel. For driver side, supported link rate set is fetched when link detection, no need to update but just read again as WA. [How] Read DPCD 0x010 again during link training for eDP 1.4. Signed-off-by: Dale Zhao <dale.zhao@amd.com> Reviewed-by: Wenjing Liu <Wenjing.Liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: Calculate CRC on specific frame regionWayne Lin3-3/+15
[why] Currently, we only support calculating CRC on whole frame. We want to extend the capability to calculate CRC on specific frame area. [how] Calculate CRC on specific area once it's specified from the input parameter. Signed-off-by: Wayne Lin <Wayne.Lin@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: Do not warn NULL dc_sink if forcing connectorVictor Lu1-1/+2
[why] There is a DRM_ERROR when the dc_sink is NULL and there should not be this warning when the connector is forced. [how] Do not warn if dc_sink is NULL if the connector is forced. Signed-off-by: Victor Lu <victorchengchi.lu@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: Blank HUBP during pixel data blank for DCN30 v2Joshua Aberback9-108/+100
[Why] Prior commit "Blank HUBP during pixel data blank for DCN30" missed the call to set_disp_pattern_generator from set_crtc_test_pattern, which re-exposed the issue for which we initially blocked active-only p-state switching. [How] - remove dcn30_blank_pixel_data, set dcn30 back to dcn20 version - new hwss funciton set_disp_pattern_generator - dcn20 version just calls opp_set_disp_pattern_generator - dcn30 version implements the HUBP blank Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: Reset flip_immediate to topmost planeAlvin Lee1-0/+3
[Why] When checking if we want to disable GSL or not, we should reset flip_immediate to be the flip type of the topmost plane before looping through the other planes. [How] Set flip_immediate to be the flip type of the topmost plane before looping through the other planes. Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: Update connector on DSC property changeEryk Brol3-1/+130
[Why] We want to trigger atomic check on connector when DSC debugfs properties are changed. The previous method was reverted because it accessed connector properties unsafely and would also heavily impact performance. [How] Add a flag for forcing DSC update in CRTC state and add connector to the state if the flag is set. Signed-off-by: Eryk Brol <eryk.brol@amd.com> Reviewed-by: Nicholas Kazlauskas <Nicholas.Kazlauskas@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: correct eDP T9 delayHugo Hu3-13/+17
[Why] The current end of T9 delay is relay on polling sink status by DPCD. But the polling for sink status change after NoVideoStream_flag set to 0. [How] Add function edp_add_delay_for_T9 to add T9 delay. Move the sink status polling after blank. Signed-off-by: Hugo Hu <hugo.hu@amd.com> Reviewed-by: Charlene Liu <Charlene.Liu@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: Add OPTC memory low power supportJacky Liao4-10/+32
[Why] The OPTC memory blocks should be powered down when they are not in use. This will reduce power consumption. [How] 1. Set ODM_MEM_UNASSIGNED_PWR_MODE to shutdown memory when unassigned 2. Set ODM_MEM_VBLANK_PWR_MODE to light sleep mode when in vblank 3. Added a debug option to allow this behaviour to be turned off 4. Restructured debug options to use a bitfield in a way that's more clear Signed-off-by: Jacky Liao <ziyu.liao@amd.com> Reviewed-by: Eric Yang <eric.yang2@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: Update panel registerChris Park1-1/+1
[Why] Incorrect panel register settings are applied for power sequence because the register macro is not defined in resource. [How] Implement same register space to future resource files. Signed-off-by: Chris Park <Chris.Park@amd.com> Reviewed-by: Joshua Aberback <Joshua.Aberback@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: fail instead of div by zero/bugcheckAshley Thomas3-0/+7
[why] If pbn_per_slot is 0, fail instead of dividing by zero and bugchecking. [how] Check for zero divisor before division operation. Signed-off-by: Ashley Thomas <Ashley.Thomas2@amd.com> Reviewed-by: Wyatt Wood <Wyatt.Wood@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: 3.2.109Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <aric.cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: Blank HUBP during pixel data blank for DCN30Joshua Aberback4-2/+87
[Why] There are some timings for which we support p-state switching in active, but not in blank. There was a previous issue where a timing that had active-only support would hang a p-state request when we were in an extended blanking period. The workaround for that issue was to block active-only p-state switching, but that resulted in a lack of p-state support for some common timings such as 1440p60. We want to fix that issue properly by un-blocking p-state requests while the display is blanked, so that we can re-enable active-only p-state switching. [How] - new version of blank_pixel_data for DCN30 - call hubp->set_blank from dcn30_blank_pixel_data - blank every hubp in the mpcc tree, and odm tree - on blank enable, wait until the next frame before blanking HUBP Signed-off-by: Joshua Aberback <joshua.aberback@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: stop top_mgr when type change to non-MST during s3Lewis Huang1-0/+8
[Why] Driver keeps the invalid information cause report the incorrect monitor which save in remote sink to OS [How] When connector type change from MST to non-MST, stop the topology manager. Signed-off-by: Lewis Huang <Lewis.Huang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: [FW Promotion] Release 0.0.39Anthony Koo1-2/+2
Signed-off-by: Anthony Koo <Anthony.Koo@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: Keep GSL for full updates with planes that flip VSYNCAlvin Lee1-0/+19
[Why] When enabling PIP in Heaven, the PIP planes are VSYNC flip and is also the top-most pipe. In this case GSL will be disabled because we only check immediate flip for the top pipe. However, the desktop planes are still flip immediate so we should at least keep GSL on until the full update. [How] Check each pipe in the tree to see if any planes are flip immediate. Maintain the GSL lock if yes, and take it down after when unlocking if any planes are flipping VSYNC. Keeping GSL on with VSYNC + flip immediate planes causes corruption. Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Reviewed-by: Aric Cyr <Aric.Cyr@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: Force prefetch mode to 0Isabel Zhang1-1/+3
[Why] On APU should be always using prefetch mode 0. Currently, sometimes prefetch mode 1 is being used causing system to hard hang due to minTTUVBlank being too low. [How] Any ASIC running DCN21 will by default allow self refresh and mclk switch. This sets both min and max prefetch mode to 0 by default. Signed-off-by: Isabel Zhang <isabel.zhang@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: only check available pipe to disable vbios mode.Yongqiang Sun1-1/+5
[Why & How] 1. only need to check first ODM pipe. 2. Only need to check eDP which is on. Signed-off-by: Yongqiang Sun <yongqiang.sun@amd.com> Reviewed-by: Tony Cheng <Tony.Cheng@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: Add MPC memory shutdown support for DCN3Jacky Liao3-3/+63
[Why] The MPC memory blocks in DCN3 should be powered down completely when they are not in use. This will reduce power consumption. [How] This commits changes behaviour for dcn3 and does the following: 1. Write to MPC_RMU<X>_LOW_PWR_MODE and MPCC_OGAM_MEM_LOW_PWR_MODE to automatically shut down memory when not in use 2. mpc3_power_on_shaper_3dlut and mpc3_power_on_ogam_lut are called to disable force power on when configuration finishes 3. Added a debug option to allow this behaviour to be turned off Signed-off-by: Jacky Liao <ziyu.liao@amd.com> Reviewed-by: Jun Lei <Jun.Lei@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-02drm/amd/display: Fix compilation errorTao.Huang3-6/+6
[Why] The C standard does not specify whether an enum is signed or unsigned. In the function prototype, one of the argument is defined as an enum but its declaration was unit32_t. Fix this by changing the function argument to enum in the declaration. Signed-off-by: Tao.Huang <Tao.Huang@amd.com> Signed-off-by: Florin Iucha <florin.iucha@amd.com> Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Acked-by: Qingqing Zhuo <qingqing.zhuo@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-11-01drm/amdgpu: fix build_coefficients() argumentArnd Bergmann1-1/+1
gcc -Wextra warns about a function taking an enum argument being called with a bool: drivers/gpu/drm/amd/amdgpu/../display/modules/color/color_gamma.c: In function 'apply_degamma_for_user_regamma': drivers/gpu/drm/amd/amdgpu/../display/modules/color/color_gamma.c:1617:29: warning: implicit conversion from 'enum <anonymous>' to 'enum dc_transfer_func_predefined' [-Wenum-conversion] 1617 | build_coefficients(&coeff, true); It appears that a patch was added using the old calling conventions after the type was changed, and the value should actually be 0 (TRANSFER_FUNCTION_SRGB) here instead of 1 (true). Fixes: 55a01d4023ce ("drm/amd/display: Add user_regamma to color module") Reviewed-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-30drm/amd/display: Clean up GFX9 tiling_flags path.Bas Nieuwenhuizen1-67/+7
We're unconditionally using modifiers internally for GFX9+ now. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-30drm/amd/display: Expose modifiers.Bas Nieuwenhuizen1-1/+338
This expose modifier support on GFX9+. Only modifiers that can be rendered on the current GPU are added. This is to reduce the number of modifiers exposed. The HW could expose more, but the best mechanism to decide what to expose without an explosion in modifiers is still to be decided, and in the meantime this should not regress things from pre-modifiers and does not risk regressions as we make up our mind in the future. v2: - Added comment that D on Raven is only valid for 64bpp and will be filtered based on format later. - Removed D tiling modes that weren't useful for 64bpp on GFX10+. v4: Add AMDGPU_FAMILY_VGH case. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-30drm/amd/display: Add formats for DCC with 2/3 planes.Bas Nieuwenhuizen1-0/+96
For DCC we will use 2/3 planes to avoid X rendering to the frontbuffer with DCC compressed images. To make this work with the core KMS validation we need to add extra formats with the extra planes. However, due to flexibility we set bpp = 0 for the extra planes and do the validation ourselves. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-30drm/amd/display: Set DC options from modifiers.Bas Nieuwenhuizen1-7/+95
This sets the DC tiling options from the modifier, if modifiers are used for the FB. This patch by itself does not expose the support yet though. There is not much validation yet to limit the scope of this patch, but the current validation is at the same level as the BO metadata path. v2: Add modifier check to should_reset_plane. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-30drm/amd/display: Refactor surface tiling setup.Bas Nieuwenhuizen1-103/+119
Prepare for inserting modifiers based configuration, while sharing a bunch of DCC validation & initializing the device-based configuration. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-30drm/amd/display: Store tiling_flags in the framebuffer.Bas Nieuwenhuizen2-63/+12
This moves the tiling_flags to the framebuffer creation. This way the time of the "tiling" decision is the same as it would be with modifiers. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-30drm/amd/display: Honor the offset for plane 0.Bas Nieuwenhuizen1-5/+9
With modifiers I'd like to support non-dedicated buffers for images. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Cc: stable@vger.kernel.org # 5.1.0 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-30drm/amd/display: Do not silently accept DCC for multiplane formats.Bas Nieuwenhuizen1-1/+1
Silently accepting it could result in corruption. Signed-off-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-30drivers: amdgpu: Correct spelling defalut to default in commentBhaskar Chowdhury1-1/+1
Correct spelling in one of the comment. s/defalut/default/p Signed-off-by: Bhaskar Chowdhury <unixbhaskar@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-30drm/amdgpu: fix incorrect enum typeArnd Bergmann1-2/+2
core_link_write_dpcd() returns enum dc_status, not ddc_result: display/dc/core/dc_link_dp.c: In function 'dp_set_panel_mode': display/dc/core/dc_link_dp.c:4237:11: warning: implicit conversion from 'enum dc_status' to 'enum ddc_result' [-Wenum-conversion] Avoid the warning by using the correct enum in the caller. Fixes: 0b226322434c ("drm/amd/display: Synchronous DisplayPort Link Training") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-30drm/amd/display: remove unneeded semicolonTom Rix2-2/+2
A semicolon is not needed after a switch statement. Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-30drm/amd/display: remove useless if/elseZou Wei1-7/+4
Fix the following coccinelle report: ./drivers/gpu/drm/amd/display/dc/calcs/dce_calcs.c:1367:3-5: WARNING: possible condition with no effect (if == else) Both branches are the same, so remove the if/else altogether. Fixes: 81875979f0b2 ("drm/amd/display: Remove extra pairs of parentheses in dce_calcs.c") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zou Wei <zou_wei@huawei.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-30drm/amdgpu/display: remove dal_cmd_tbl_helper_dcn2_get_table2Alex Deucher2-43/+0
It's unused and identical to dal_cmd_tbl_helper_dce112_get_table2. Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-30drm/amdgpu/display: remove DRM_AMD_DC_GREEN_SARDINEAlex Deucher5-20/+0
No need for a separate config option at this point. Reviewed-by: Luben Tuikov <luben.tuikov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-30drm/amd/display: allow 18 bit dp output on DCN3Dmytro Laktyushkin2-15/+1
We need this to pass dp compliance. Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com> Reviewed-by: Chris Park <Chris.Park@amd.com> Reviewed-by: Nikola Cornij <nikola.cornij@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-30drm/amdgpu/display: fix indentation in defer_delay_converter_wa()Alex Deucher1-7/+7
Fixes this warning: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_ddc.c: In function ‘defer_delay_converter_wa’: drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_ddc.c:285:2: warning: this ‘if’ clause does not guard... [-Wmisleading-indentation] 285 | if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_0080E1 && | ^~ drivers/gpu/drm/amd/amdgpu/../display/dc/core/dc_link_ddc.c:291:3: note: ...this statement, but the latter is misleadingly indented as if it were guarded by the ‘if’ 291 | if (link->dpcd_caps.branch_dev_id == DP_BRANCH_DEVICE_ID_006037 && | ^~ Reviewed-by: Evan Quan <evan.quan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-27drm/amdgpu/display: re-add surface size calculation in dcn30_hwseq.cAlex Deucher1-0/+15
This is required for MALL. Was accidently removed in PSR update. Fixes: 48e48e598478 ("drm/amd/display: Disable idle optimization when PSR is enabled") Fixes: 52f2e83e2fe5 ("drm/amdgpu/display: add MALL support (v2)") Acked-by: Slava Abramov <slava.abramov@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2020-10-27drm/amd/display: correct asic type check V2Evan Quan5-7/+16
Check chip family also to avoid wrong identification. V2: use the correct macro without AMDGPU prefix Signed-off-by: Evan Quan <evan.quan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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