aboutsummaryrefslogtreecommitdiff
path: root/drivers/gpu/drm/amd/display
AgeCommit message (Collapse)AuthorFilesLines
2021-06-15drm/amd/display: Partition DPCD address space and break up transactionsWesley Chalmers1-2/+85
[WHY] SCR for DP 2.0 spec says that multiple LTTPRs must not be accessed in a single AUX transaction. There may be other places in future where breaking up AUX accesses is necessary. [HOW] Partition the entire DPCD address space into blocks. When an incoming AUX request spans multiple blocks, break up the request into multiple requests. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Do not count I2C DEFERs with AUX DEFERsWesley Chalmers1-1/+2
[WHY] DP 2.0 SCR specifies that "A DPTX shall distinguish I2C_DEFER|AUX_ACK from AUX_DEFER. AUX retries due to I2C_DEFER are not counted as part of minimum 7 retires (sic) upon AUX_DEFER’s" Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: 7 retries + 50 ms timeout on AUX DEFERWesley Chalmers1-3/+15
[WHY] DP 2.0 SCR specifies that TX devices must retry at least 7 times when receiving an AUX DEFER reply from RX. In addition, the specification states that the TX shall not retry indefinitely, and gives a suggestive timeout interval of 50ms. [HOW] Keep retrying until both 7 or more retries have been made, and the 50ms interval has passed. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Rename constantWesley Chalmers1-3/+3
[WHY] 7 is the minimum number of retries TX must attempt on an AUX DEFER, not the maximum. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Enforce DPCD Address rangesWesley Chalmers11-45/+162
[WHY] Some DPCD addresses, notably LTTPR Capability registers, are expected to be read all together in a single DPCD transaction. Rather than force callers to read registers they don't need, we want to quietly extend the addresses read, and only return back the values the caller asked for. This does not affect DPCD writes. [HOW] Create an additional layer above AUX to perform 'checked' DPCD transactions. Iterate through an array of DPCD address ranges that are marked as being contiguous. If a requested read falls within one of those ranges, extend the read to include the entire range. After DPCD has been queried, copy the requested bytes into the caller's data buffer, and deallocate all resources used. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Improve logic for is_lttpr_presentWesley Chalmers1-2/+1
[WHY] DP specifies that an LTTPR device is only present if PHY_REPEATER_CNT is 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, or 0x01. All other values should be considered no LTTPRs present. [HOW] Function dp_convert_to_count already does this check. Use it to determine if PHY_REPEATER_CNT is a valid LTTPR count. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Always write repeater mode regardless of LTTPRWesley Chalmers1-4/+3
[WHY] SCR for DP2.0 requires that LT be performed with PHY_REPEATER_MODE programmed to 0x55 (Transparent) whenever PHY_REPEATER_CNT is any value other than 0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, or 0x01. [HOW] Write Non-Transparent (0xAA) to PHY_REPEATER_MODE when LTTPRs detected and Non-Transparent is requested. Write Transparent in all other cases. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Set LTTPR Transparent Mode after read link capWesley Chalmers1-2/+3
[WHY] SCR for DP 2.0 Spec states that a DPTX shall put LTTPRs into Transparent mode after reading LTTPR Capability registers on HPD. The wording of the SCR is somewhat ambiguous as to whether Transparent mode must be set explicity, or is implicitly set on LTTPR capability read. Explicitly setting Transparent mode after LTTPR capability read should cover all cases. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Read LTTPR caps first on bootupWesley Chalmers3-0/+8
[WHY] SCR for DP 2.0 requires that LTTPR caps be read first on hotplug. For the sake of consistency, this should also be the case on bootup. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Move LTTPR cap read into its own functionWesley Chalmers1-34/+41
[WHY] We want LTTPR capabilities to be readable from more places than just retrieve_link_cap Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Read LTTPR caps first on hotplugWesley Chalmers1-32/+33
[WHY] A new SCR for the DP2.0 spec requires that LTTPR caps be the first thing read from DPCD upon hotplug. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: move psr dm interface to separate filesRoman Li4-137/+205
[Why] Improve the maintain/read abilities of dm code. [How] Create amdgpu_dm_psr.c/h files. Move psr function from amdgpu_dm.c Signed-off-by: Roman Li <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: 3.2.140Aric Cyr1-1/+1
This version brings along following fixed: - LTTPR improvements - Backlight improvements - eDP hotplug detection Signed-off-by: Aric Cyr <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: [FW Promotion] Release 0.0.70Anthony Koo1-2/+2
Signed-off-by: Anthony Koo <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Updated variable name.David Galiffi1-6/+6
[Why] Fixed spelling error. [How] Changed "currnet_setting" to "current_setting". Signed-off-by: David Galiffi <[email protected]> Reviewed-by: Wesley Chalmers <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Change swizzle visual confirm reference pipePo-Ting Chen1-5/+5
[Why] To change the swizzle visual confirm reference pipe from top pipe to bottom pipe due to bottom pipe information would be more important for multiple overlay case. Signed-off-by: Po-Ting Chen <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: dp mst detection code refactorWenjing Liu2-96/+70
[why] Move mst start top mgr in dc_link_detect layer. Remove unused same_dpcd variable. Move PEAK_FACTOR_X1000 and LINK_TRAINING_MAX_VERIFY_RETRY to the proper header for defining dc link internal constant. Signed-off-by: Wenjing Liu <[email protected]> Reviewed-by: George Shen <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: tune backlight ramping profilesJosip Pavic1-10/+10
[Why & How] Tune backlight ramping profiles for each Vari-Bright level to suit customer preferences Signed-off-by: Josip Pavic <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: add config option for eDP hotplug detectionYi-Ling Chen2-4/+7
[Why] Some custom platforms use eDP hotplug events to notify panel capability changes that should be reported [How] Add a DC config option that unblocks eDP hotplug events Signed-off-by: Yi-Ling Chen <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: add DMUB registers to crash dump diagnostic data.Ashley Thomas11-9/+238
[WHY] Ability to triage DMCUB is improved with availability of certain dmub registers not currently captured in crash dump diagnostic data. [HOW] Add dmub registers to diagnostic data collection. Thanks Nicholas Kazlauskas for awesome input on this! Signed-off-by: Ashley Thomas <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-15drm/amd/display: Remove unnecessary blank linesDmytro Laktyushkin1-2/+0
cleanup Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Anson Jacob <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-11drm/amd/display: Verify Gamma & Degamma LUT sizes in amdgpu_dm_atomic_checkMark Yacoub3-6/+40
For each CRTC state, check the size of Gamma and Degamma LUTs so unexpected and larger sizes wouldn't slip through. TEST: IGT:kms_color::pipe-invalid-gamma-lut-sizes v2: fix assignments in if clauses, Mark's email. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Mark Yacoub <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-11drm/amd/display: add dummy PG callback for beige gobyAurabindo Pillai3-0/+7
[Why&How] PG registers are absent in beige goby, so programming these registers generate call trace. Fix this by adding a dummy function in dcn303 initialization function which prevents writing to non existant registers. Fixes: cd6d421e3d1ad5 ("drm/amd/display: Initial DC support for Beige Goby") Signed-off-by: Aurabindo Pillai <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-10drm: display: Remove duplicated argument in dcn31Wan Jiabing1-2/+2
Fix the following coccicheck warning: ./drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c: 3539:12-42: duplicated argument to && or || ./drivers/gpu/drm/amd/display/dc/dml/dcn31/display_mode_vba_31.c: 5677:87-123: duplicated argument to && or || Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Wan Jiabing <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-10drm: display: Remove duplicate include in dce110Wan Jiabing1-1/+0
Fix the following checkincludes.pl warning: ./drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c 35 #include "dce110_hw_sequencer.h" 69 #include "dce110_hw_sequencer.h" Reviewed-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Wan Jiabing <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-10drm/amd/display: use ARRAY_SIZE for base60_refresh_ratesJiapeng Chong1-1/+1
Use ARRAY_SIZE instead of dividing sizeof array with sizeof an element. Clean up the following coccicheck warning: ./drivers/gpu/drm/amd/display/dc/core/dc_resource.c:448:47-48: WARNING: Use ARRAY_SIZE. Reported-by: Abaci Robot <[email protected]> Signed-off-by: Jiapeng Chong <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-10drm/amd/display: Fix duplicate included clk_mgr.hJiapeng Chong1-1/+0
Clean up the following includecheck warning: ./drivers/gpu/drm/amd/display/dc/dcn31/dcn31_hwseq.c: clk_mgr.h is included more than once. No functional change. Reported-by: Abaci Robot <[email protected]> Signed-off-by: Jiapeng Chong <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-10Merge tag 'amd-drm-next-5.14-2021-06-09' of ↵Dave Airlie134-442/+20234
https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.14-2021-06-09: amdgpu: - SR-IOV fixes - Smartshift updates - GPUVM TLB flush updates - 16bpc fixed point display fix for DCE11 - BACO cleanups and core refactoring - Aldebaran updates - Initial Yellow Carp support - RAS fixes - PM API cleanup - DC visual confirm updates - DC DP MST fixes - DC DML fixes - Misc code cleanups and bug fixes amdkfd: - Initial Yellow Carp support radeon: - memcpy_to/from_io fixes UAPI: - Add Yellow Carp chip family id Used internally in the kernel driver and by mesa Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-10Merge tag 'drm-misc-next-2021-06-09' of ↵Dave Airlie1-3/+2
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 5.14: UAPI Changes: * drm/panfrost: Export AFBC_FEATURES register to userspace Cross-subsystem Changes: * dma-buf: Fix debug printing; Rename dma_resv_*() functions + changes in callers; Cleanups Core Changes: * Add prefetching memcpy for WC * Avoid circular dependency on CONFIG_FB * Cleanups * Documentation fixes throughout DRM * ttm: Make struct ttm_resource the base of all managers + changes in all users of TTM; Add a generic memcpy for page-based iomem; Remove use of VM_MIXEDMAP; Cleanups Driver Changes: * drm/bridge: Add TI SN65DSI83 and SN65DSI84 + DT bindings * drm/hyperv: Add DRM driver for HyperV graphics output * drm/msm: Fix module dependencies * drm/panel: KD53T133: Support rotation * drm/pl111: Fix module dependencies * drm/qxl: Fixes * drm/stm: Cleanups * drm/sun4i: Be explicit about format modifiers * drm/vc4: Use struct gpio_desc; Cleanups * drm/vgem: Cleanups * drm/vmwgfx: Use ttm_bo_move_null() if there's nothing to copy * fbdev/mach64: Cleanups * fbdev/mb862xx: Use DEVICE_ATTR_RO Signed-off-by: Dave Airlie <[email protected]> From: Thomas Zimmermann <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/YMBw3DF2b9udByfT@linux-uq9g
2021-06-08drm/amd/display: 3.2.139Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: [FW Promotion] Release 0.0.69Wyatt Wood1-2/+2
Signed-off-by: Wyatt Wood <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Add swizzle visual confirm modePo-Ting Chen5-1/+29
[Why] To support a new visual confirm mode: swizzle to show the specific color at the screen border according to different surface swizzle mode. Currently we only support the Linear mode with red color. Signed-off-by: Po-Ting Chen <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: force CP to DESIRED when removing displayDingchen (David) Zhang1-1/+14
[WHY] - Commit from userspace could cause link stream to disable and hdcp auth to reset when the HDCP has already been enabled at the moment. CP should fall back to DESIRED from ENABLED in such cases. - This change was previously reverted due to a regression caused, which has now been cleared. [HOW] In hdcp display removal, change CP to DESIRED if at the moment CP is ENABLED before the auth reset and removal of linked list element. Signed-off-by: Dingchen (David) Zhang <[email protected]> Signed-off-by: Qingqing Zhuo <[email protected]> Reviewed-by: Rodrigo Siqueira <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Updates for ODM Transition TestEric Bernstein1-1/+0
[Why] There is an assert in cases where transition from ODM 2:1 to ODM 1:1 (bypass) [How] Remove assert since this case is now valid. Update diags tests for ODM transitions. Signed-off-by: Eric Bernstein <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Revert "Disconnect non-DP with no EDID"Roy Chan1-18/+0
[Why] Found a use case (IPKVM) that DP-VGA active dongle does not return any EDID and the mentioned commit broke it. [How] This reverts "Disconnect non-DP with no EDID" Signed-off-by: Roy Chan <[email protected]> Reviewed-by: Chris Park <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Add debugfs entry for dsc passthroughFangzhi Zuo2-1/+50
[Why & How] Add debugfs entry to force dsc decoding at PCON when DSC capable external RX is connected. In such case, it is free to test DSC decoding at external RX or at PCON. Signed-off-by: Fangzhi Zuo <[email protected]> Reviewed-by: Hersen Wu <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Fix crash during MPO + ODM combine mode recalculationAric Cyr1-0/+5
[Why] When calculating recout width for an MPO plane on a mode that's using ODM combine, driver can calculate a negative value, resulting in a crash. [How] For negative widths, use zero such that validation will prune the configuration correctly and disallow MPO. Signed-off-by: Aric Cyr <[email protected]> Reviewed-by: Krunoslav Kovac <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Fix off-by-one error in DMLWesley Chalmers1-7/+7
[WHY] For DCN30 and later, there is no data in DML arrays indexed by state at index num_states. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Set DISPCLK_MAX_ERRDET_CYCLES to 7Wesley Chalmers1-1/+1
[WHY] DISPCLK_MAX_ERRDET_CYCLES must be 7 to prevent connection loss when changing DENTIST_DISPCLK_WDIVIDER from 126 to 127 and back. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Add interface for ADD & DROP PIXEL RegistersWesley Chalmers8-8/+101
[WHY] HW has handed down a new sequence that requires access to these registers. v2: squash in DCN3.1 fixes (Alex) Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Add Interface to set FIFO ERRDET SW OverrideWesley Chalmers6-3/+41
[WHY] HW has handed down a new sequence which requires access to the FIFO ERRDET SW Override register. Signed-off-by: Wesley Chalmers <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: 3.2.138Aric Cyr1-1/+1
Signed-off-by: Aric Cyr <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: [FW Promotion] Release 0.0.68Anthony Koo1-6/+3
Signed-off-by: Anthony Koo <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Change default policy for MPO with multidisplayAric Cyr4-4/+4
[Why] Rearranging pipes with multiple displays and multiple planes cannot be done atomically and requires a much improved sequence to deal with it. [How] To workaround such issues, prefer avoid pipe-split policy for multidisplay scenarios. Signed-off-by: Aric Cyr <[email protected]> Reviewed-by: Krunoslav Kovac <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Release MST resources on switch from MST to SSTVladimir Stempen1-0/+2
[why] When OS overrides training link training parameters for MST device to SST mode, MST resources are not released and leak of the resource may result crash and incorrect MST discovery during following hot plugs. [how] Retaining sink object to be reused by SST link and releasing MST resources. Signed-off-by: Vladimir Stempen <[email protected]> Reviewed-by: Wenjing Liu <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Enable PSR Residency for multiple panelsMikita Lipski3-6/+12
[why] Allow specifying which panel to take PSR Residency measurements from. [how] Pass panel instance to DMUB through GPINT in the upper 8 bits of the parameter. Signed-off-by: Mikita Lipski <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Return last used DRR VTOTAL from DCJayendran Ramani12-6/+75
[How] Add call to get the last used VTOTAL from DC Signed-off-by: Jayendran Ramani <[email protected]> Reviewed-by: Anthony Koo <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Remove unused definition of DMUB SET_CONFIGMeenakshikumar Somasundaram1-4/+0
[Why & How] SET_CONFIG transactions with DMUB is not used and removed. Signed-off-by: Meenakshikumar Somasundaram <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Update scaling settings on modesetRoman Li1-1/+2
[Why] We update scaling settings when scaling mode has been changed. However when changing mode from native resolution the scaling mode previously set gets ignored. [How] Perform scaling settings update on modeset. Signed-off-by: Roman Li <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-08drm/amd/display: Support mappable encoders when transmitting training patterns.Jimmy Kizito1-1/+10
[Why & How] Add support for transmitting training pattern sequences for links whose encoders have been dynamically assigned. Signed-off-by: Jimmy Kizito <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Stylon Wang <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
Powered by cgit, Gruvboxed by Blaster4385.