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2021-07-01drm/amd/display: fix null pointer access in gpu resetGuchun Chen1-2/+2
During GPU reset, when receiving a DMCUB OUTBUX0 interrupt, DAL code will set it to be OUTBOX interrupt and sets hw interrupt. However, OUTBOX interrupt is not registered yet, so a NULL pointer access will be executed. Call Trace: dal_irq_service_set+0x30/0x90 [amdgpu] dc_interrupt_set+0x24/0x30 [amdgpu] amdgpu_dm_set_dmub_outbox_irq_state+0x22/0x30 [amdgpu] amdgpu_irq_update+0x77/0xa0 [amdgpu] amdgpu_irq_gpu_reset_resume_helper+0x67/0xa0 [amdgpu] amdgpu_do_asic_reset+0x219/0x260 [amdgpu] amdgpu_device_gpu_recover.cold+0x8c5/0xb64 [amdgpu] amdgpu_debugfs_gpu_recover_show+0x2c/0x60 [amdgpu] seq_read_iter+0xc2/0x450 ? do_anonymous_page+0x22c/0x3b0 seq_read+0xf9/0x140 full_proxy_read+0x5c/0x90 vfs_read+0xaa/0x190 ksys_read+0x67/0xe0 __x64_sys_read+0x1a/0x20 Fixes: effbf6ca7eafda ("drm/amdgpu/display: remove an old DCN3 guard") Signed-off-by: Guchun Chen <[email protected]> Reviewed-and-tested-by: Evan Quan <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-22drm/amdgpu/display: fold DRM_AMD_DC_DCN3_1 into DRM_AMD_DC_DCNAlex Deucher2-5/+0
No need for a separate flag now that DCN3.1 is not in bring up. Fold into DRM_AMD_DC_DCN like previous DCN IPs. Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amd/display: Add DCN3.1 IRQ managerNicholas Kazlauskas3-0/+480
Add IRQ services for DCN3.1 to handle hardware generated interrupts. Acked-by: Huang Rui <[email protected]> Signed-off-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Edit license info for beige goby DC filesAurabindo Pillai2-40/+4
[How] * Add MIT license to all new files as SPDX tag. * Fix copyright year Signed-off-by: Aurabindo Pillai <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-19drm/amd/display: Initial DC support for Beige GobyAurabindo Pillai3-0/+321
[Why&How] Add Beige Goby (DCN303) resource, irq service, & dmub loader. v2: fix nbio include (Alex) Signed-off-by: Chris Park <[email protected]> Signed-off-by: Aurabindo Pillai <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-10drm/amd/display: Support for DMUB AUXJude Shih1-9/+9
[WHY] To process AUX transactions with DMUB using inbox1 and outbox1 mail boxes. [How] 1) Added inbox1 command DMUB_CMD__DP_AUX_ACCESS to issue AUX commands to DMUB in dc_process_dmub_aux_transfer_async(). DMUB processes AUX cmd with DCN and sends reply back in an outbox1 message triggering an outbox1 interrupt to driver. 2) In existing driver implementation, AUX commands are processed synchronously by configuring DCN reg. But in DMUB AUX, driver sends an inbox1 message and waits for a conditional variable (CV) which will be signaled by outbox1 ISR. 3) DM will retrieve Outbox1 message and send back reply to upper layer and complete the AUX command Signed-off-by: Jude Shih <[email protected]> Reviewed-by: Hanghong Ma <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Wayne Lin <[email protected]> Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: add DMCUB trace irq support for DCN302Guchun Chen1-0/+30
Otherwise, below errors will be found on DIMGREY_CAVEFISH with DCN302. Error log observed in driver load: [drm:amdgpu_dm_irq_register_interrupt [amdgpu]] *ERROR* DM_IRQ: invalid irq_source: 0! Error observed in mode1_rest sequence: [ 27.265920] #PF: supervisor read access in kernel mode [ 27.265941] #PF: error_code(0x0000) - not-present page [ 27.265956] PGD 0 P4D 0 [ 27.265967] Oops: 0000 [#1] SMP NOPTI [ 27.265979] CPU: 0 PID: 1360 Comm: cat Tainted: G W 5.11.0-99b3786c1770 #20210323 [ 27.266005] Hardware name: System manufacturer System Product Name/PRIME Z390-A, BIOS 1401 11/26/2019 [ 27.266033] RIP: 0010:dal_irq_service_ack+0x25/0x60 [amdgpu] [ 27.266203] Code: 5d 5d c3 66 90 0f 1f 44 00 00 55 83 fe 61 48 89 e5 77 27 89 f0 48 8d 04 40 48 c1 e0 04 48 03 47 08 74 17 48 8b 50 28 48 89 c6 <48> 8b 52 08 48 85 d2 74 20 e8 1d 64 45 c9 5d c3 89 f2 48 c7 c7 f0 [ 27.266248] RSP: 0018:ffffa115824a3c08 EFLAGS: 00010082 [ 27.266270] RAX: ffffffffc0942c10 RBX: ffffffffc0942c10 RCX: 0000000000000000 [ 27.266288] RDX: 0000000000000000 RSI: ffffffffc0942c10 RDI: ffff88d509cba7a0 [ 27.266312] RBP: ffffa115824a3c08 R08: 0000000000000000 R09: 0000000000000001 [ 27.266335] R10: ffffa115824a3b20 R11: ffffa115824a3b58 R12: ffff88d509cba7a0 [ 27.266353] R13: 0000000000000000 R14: 0000000000000000 R15: 0000000000000246 [ 27.266377] FS: 00007fb3e2438580(0000) GS:ffff88d50dc00000(0000) knlGS:0000000000000000 [ 27.266402] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 27.266417] CR2: 0000000000000008 CR3: 000000083e5ac006 CR4: 00000000003706f0 [ 27.266441] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 27.266464] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 27.266483] Call Trace: [ 27.266491] dal_irq_service_set+0x31/0x80 [amdgpu] [ 27.266639] dc_interrupt_set+0x24/0x30 [amdgpu] [ 27.266775] amdgpu_dm_set_dmub_trace_irq_state+0x22/0x30 [amdgpu] [ 27.266920] amdgpu_irq_update+0x57/0xa0 [amdgpu] [ 27.267030] amdgpu_irq_gpu_reset_resume_helper+0x64/0xa0 [amdgpu] [ 27.267135] amdgpu_do_asic_reset+0x211/0x420 [amdgpu] [ 27.267232] amdgpu_device_gpu_recover+0x517/0xa70 [amdgpu] [ 27.267325] gpu_recover_get+0x2e/0x60 [amdgpu] [ 27.267421] simple_attr_read+0x6b/0x130 [ 27.267441] debugfs_attr_read+0x49/0x70 [ 27.267454] full_proxy_read+0x5c/0x90 [ 27.267474] vfs_read+0xa1/0x190 [ 27.267486] ksys_read+0xa7/0xe0 [ 27.267501] __x64_sys_read+0x1a/0x20 [ 27.267521] do_syscall_64+0x37/0x80 [ 27.267541] entry_SYSCALL_64_after_hwframe+0x44/0xa9 [ 27.267562] RIP: 0033:0x7fb3e2356142 Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Leo (Hanghong) Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-04-09drm/amd/display: Log DMCUB trace buffer eventsLeo (Hanghong) Ma2-2/+52
[Why] We want to log DMCUB trace buffer events as Linux kernel traces. [How] Register an IRQ handler for DMCUB outbox0 interrupt in amdgpu_dm, and log the messages in the DMCUB tracebuffer to a new DMCUB TRACE_EVENT as soon as we receive the outbox0 IRQ from DMCUB FW. Tested-by: Daniel Wheeler <[email protected]> Signed-off-by: Leo (Hanghong) Ma <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Solomon Chiu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-03-26Merge tag 'amd-drm-next-5.13-2021-03-23' of ↵Daniel Vetter4-0/+133
https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.13-2021-03-23: amdgpu: - Debugfs cleanup - Various cleanups and spelling fixes - Flexible array cleanups - Initial AMD Freesync HDMI - Display fixes - 10bpc dithering improvements - Display ASSR support - Clean up and unify powerplay and swsmu interfaces - Vangogh fixes - Add SMU gfx busy queues for RV/PCO - PCIE DPM fixes - S0ix fixes - GPU metrics data fixes - DCN secure display support - Backlight type override - Add initial support for Aldebaran - RAS fixes - Prime fixes for A+A systems - Reset fixes - Initial resource cursor support - Drop legacy IO BAR requirements - Various power fixes amdkfd: - MMU notifier fixes - APU fixes radeon: - Debugfs cleanups - Flexible array cleanups UAPI: - amdgpu: Add a new INFO ioctl interface to query video capabilities rather than hardcoding them in userspace. This allows us to provide fine grained asic capabilities (e.g., if a particular part is bandwidth limited, we can limit the capabilities). Proposed userspace: https://gitlab.freedesktop.org/leoliu/drm/-/commits/info_video_caps https://gitlab.freedesktop.org/leoliu/mesa/-/commits/info_video_caps - amdkfd: bump the driver version. There was a problem with reporting some RAS features on older versions of the driver. Proposed userspace: https://github.com/RadeonOpenCompute/ROCT-Thunk-Interface/commit/7cdd63475c36bb9f49bb960f90f9a8cdb7e80a21 Danvet: A bunch of conflicts all over, but it seems to compile ... I did put the call to dc_allow_idle_optimizations() on a single line since it looked a bit too jarring to be left alone. Signed-off-by: Daniel Vetter <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-03-23drm/amd/display: Support vertical interrupt 0 for all dcn ASICWayne Lin4-0/+137
[Why] When CONFIG_DRM_AMD_SECURE_DISPLAY is enabled, it will try to register vertical interrupt 0 for specific task. Currently, only dcn10 have defined relevant info for vertical interrupt 0. If we enable CONFIG_DRM_AMD_SECURE_DISPLAY for other dcn ASIC, will get DC_IRQ_SOURCE_INVALID while calling dc_interrupt_to_irq_source() and cause pointer errors. [How] Add support of vertical interrupt 0 for all dcn ASIC. v2: squash in build fix (Alex) Signed-off-by: Wayne Lin <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Acked-by: Solomon Chiu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-22drm/amd/display: Add vupdate_no_lock interrupts for DCN2.1Rodrigo Siqueira1-0/+22
When run igt@kms_vrr in a device that uses DCN2.1 architecture, we noticed multiple failures. Furthermore, when we tested a VRR demo, we noticed a system hang where the mouse pointer still works, but the entire system freezes; in this case, we don't see any dmesg warning or failure messages kernel. This happens due to a lack of vupdate_no_lock interrupt, making the userspace wait eternally to get the event back. For fixing this issue, we need to add the vupdate_no_lock interrupt in the interrupt list. Signed-off-by: Rodrigo Siqueira <[email protected]> Acked-by: Bindu Ramamurthy <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2021-02-22drm/amd/display: Add vupdate_no_lock interrupts for DCN2.1Rodrigo Siqueira1-0/+22
When run igt@kms_vrr in a device that uses DCN2.1 architecture, we noticed multiple failures. Furthermore, when we tested a VRR demo, we noticed a system hang where the mouse pointer still works, but the entire system freezes; in this case, we don't see any dmesg warning or failure messages kernel. This happens due to a lack of vupdate_no_lock interrupt, making the userspace wait eternally to get the event back. For fixing this issue, we need to add the vupdate_no_lock interrupt in the interrupt list. Signed-off-by: Rodrigo Siqueira <[email protected]> Acked-by: Bindu Ramamurthy <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-02-09drm/amd/display: Add otg vertical interrupt0 support in DCN1.0Wayne Lin1-0/+31
[Why & How] On DCN1.0, need otg vertical line interrupt to get appropriate timing to achieve specific feature request. Add otg vertical interrupt0 support for registers which operation is vertical sensitive. Signed-off-by: Wayne Lin <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-13drm/amd/display/dc/irq/irq_service: Make local function staticLee Jones1-1/+1
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/../display/dc/irq/irq_service.c:82:31: warning: no previous prototype for ‘find_irq_source_info’ [-Wmissing-prototypes] Cc: Harry Wentland <[email protected]> Cc: Leo Li <[email protected]> Cc: Alex Deucher <[email protected]> Cc: "Christian König" <[email protected]> Cc: David Airlie <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Mauro Rossi <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Lee Jones <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-11-13drm/amd/display: Add missing pflip irq for dcn2.0Alex Deucher1-2/+2
If we have more than 4 displays we will run into dummy irq calls or flip timout issues. Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-11-04drm/amdgpu: fold CONFIG_DRM_AMD_DC_DCN3* into CONFIG_DRM_AMD_DC_DCN (v3)Alex Deucher3-6/+2
Avoids confusion in configurations. v2: fix build when CONFIG_DRM_AMD_DC_DCN is disabled v3: rebase on latest code Reviewed-by: Luben Tuikov <[email protected]> (v1) Signed-off-by: Alex Deucher <[email protected]>
2020-11-02drm/amd/display: Add missing pflip irqBhawanpreet Lakha1-2/+2
If we have more than 4 displays we will run into dummy irq calls or flip timout issues. Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Qingqing Zhuo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-10-12drm/amd/display: Add support for DCN302 (v2)Bhawanpreet Lakha3-0/+387
- add DCN302 resource, irq service, dmub loader, - handle DC_VERSION_DCN_3_02 - define DCN302 power gating functions - handle DCN302 in GPIO files - define I2C regs - add CONFIG_DRM_AMD_DC_DCN3_02 guard v2: rebase fixes (Alex) Signed-off-by: Joshua Aberback <[email protected]> Signed-off-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-27drm/amd/display: dc/irq: add support for DCE6 (v4)Mauro Rossi4-0/+449
[Why] irq service requires changes for DCE6 support [How] (v1) DCE6 targets are added replicating existing DCE8 implementation. due to missing CRTC_VERTICAL_INTERRUPT0_CONTROL registers/masks, dce/dce_8_0_{d,sh_mask}.h used instead of dce/dce_6_0_{d,sh_mask}.h (v2) DCE6 headers used adding the necessary vblank irq registers (INT_MASK and VBLANK_STATUS) and vblank irq masks as implemented in amdgpu driver. Add vblank_irq_info_funcs_dce60 with .set and .ack as per commit b10d51f ("drm/amd/display: Add interrupt entries for VBLANK isr.") and use it in vblank_int_entry(reg_num) macro definition (v3) updated due to following kernel 5.3 commit: 4fc4dca ("drm/amd: drop use of drmp.h in os_types.h") (v4) updated due to following kernel 5.6 commit: d9e3267 ("drm/amd/display: cleanup of construct and destruct funcs") Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Mauro Rossi <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-10drm/amd/display: Use VUPDATE_NO_LOCK instead of VUPDATE for dcn30Nicholas Kazlauskas1-10/+18
[Why] Soft hangs occur when FreeSync is engaged since we utilize VUPDATE (which doesn't fire when holding the pipe lock) to send back vblank events when FreeSync is active. [How] The alternative (working) interrupt source for this mechanism is VUPDATE_NO_LOCK. We already use this all other DCN revisions so align dcn30 with those as well. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-01drm/amd/display: Add DCN3 IRQBhawanpreet Lakha3-0/+431
Add IWQ services for DCN3, This allows us to create/init and manage irqs for DCN3 Signed-off-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-12-05drm/amd/display: rename core_dc to dcAnthony Koo1-2/+2
[Why] First, to make code more consistent Second, to get rid of those scenario where we create a second local pointer to dc when it's already passed in. [How] Rename core_dc to dc Remove duplicate local pointers to dc Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-19drm/amd/display: cleanup of construct and destruct funcsAnthony Koo6-12/+12
[Why] Too many construct functions which makes searching difficult, especially on some debuggers. [How] Append all construct and destruct functions with dcn number and object type to make each construct function name unique Signed-off-by: Anthony Koo <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Rodrigo Siqueira <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-13drm/amd/display: rename DCN1_0 kconfig to DCNBhawanpreet Lakha2-2/+2
Since dcn20 and dcn21 are under dcn1 it doesnt make sense to have it named dcn1. Change it to "dcn" to make it generic Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-13drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_1 flagBhawanpreet Lakha1-2/+0
[Why] DCN21 is stable enough to be build by default. So drop the flags. [How] Remove them using the unifdef tool. The following commands were executed in sequence: $ find -name '*.c' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DCN2_1 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_1 '{}' ';' $ find -name '*.h' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DCN2_1 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_1 '{}' ';' In addition: * Remove from kconfig, and replace any dependencies with DCN1_0. * Remove from any makefiles. * Fix and cleanup Renoir definitions in dal_asic_id.h * Expand DCN1 ifdef to include DCN21 code in the following files: * clk_mgr/clk_mgr.c: dc_clk_mgr_create() * core/dc_resources.c: dc_create_resource_pool() * gpio/hw_factory.c: dal_hw_factory_init() * gpio/hw_translate.c: dal_hw_translate_init() Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-11-13drm/amd/display: Drop CONFIG_DRM_AMD_DC_DCN2_0 and DSC_SUPPORTEDBhawanpreet Lakha1-2/+0
[Why] DCN2 and DSC are stable enough to be build by default. So drop the flags. [How] Remove them using the unifdef tool. The following commands were executed in sequence: $ find -name '*.c' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';' $ find -name '*.h' -exec unifdef -m -DCONFIG_DRM_AMD_DC_DSC_SUPPORT -DCONFIG_DRM_AMD_DC_DCN2_0 -UCONFIG_TRIM_DRM_AMD_DC_DCN2_0 '{}' ';' In addition: * Remove from kconfig, and replace any dependencies with DCN1_0. * Remove from any makefiles. * Fix and cleanup NV defninitions in dal_asic_id.h * Expand DCN1 ifdef to include DCN2 code in the following files: * clk_mgr/clk_mgr.c: dc_clk_mgr_create() * core/dc_resources.c: dc_create_resource_pool() * dce/dce_dmcu.c: dcn20_*lock_phy() * dce/dce_dmcu.c: dcn20_funcs * dce/dce_dmcu.c: dcn20_dmcu_create() * gpio/hw_factory.c: dal_hw_factory_init() * gpio/hw_translate.c: dal_hw_translate_init() Signed-off-by: Leo Li <[email protected]> Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-08-29drm/amd/display: Add Renoir irq_services (v2)Bhawanpreet Lakha3-0/+418
Provides the interface to configure display interrrupts on renoir. v2: rebase fix (Alex) Acked-by: Harry Wentland <[email protected]> Signed-off-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-08-15drm/amd/display: Register VUPDATE_NO_LOCK interrupts for DCN2Nicholas Kazlauskas1-10/+18
[Why] These are needed to send back DRM vblank events in the case where VRR is on. Without the interrupt enabled we're deferring the events into the vblank queue and userspace is left waiting forever to get back the events they need. Found using igt@kms_vrr - the test fails immediately due to vblank timeout. [How] Register them the same way we're handling it for DCN1. This fixes igt@kms_vrr for DCN2. Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: David Francis <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-25Merge branch 'drm-next' into drm-next-5.3Alex Deucher6-0/+12
Backmerge drm-next and fix up conflicts due to drmP.h removal. Signed-off-by: Alex Deucher <[email protected]>
2019-06-22drm/amd/display: Add vupdate interrupt sources to NV10hersen wu1-0/+12
[WHY] linux upstream already has interrupt vupdate for freesync in dcn10. dcn20 interrupt shares the same source code as dcn10. but dcn20 interrupt translator does not add vupdate interrupt. this cause index of vupdate aarray be negative which causes crash. [HOW] add vupdate into dc interrupt transltor Signed-off-by: hersen wu <[email protected]> Reviewed-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-21drm/amd/display: Add DCN2 IRQ handlingHarry Wentland3-0/+405
Add support to program DCN2 IRQ handling Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-20drm/amd/display: move dcn v1_0 irq source header to ivsrcid/dcn/Hawking Zhang1-1/+1
interrupt source packet definitions for the display block (DCN). Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-06-10drm/amd: drop use of drmp.h in os_types.hSam Ravnborg5-0/+10
Drop use of the deprecated drmP.h from display/dc/os_types.h Fix all fallout after this change. Most of the fixes was adding a missing include of vmalloc.h. Signed-off-by: Sam Ravnborg <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Cc: "Christian König" <[email protected]> Cc: "David (ChunMing) Zhou" <[email protected]> Cc: David Airlie <[email protected]> Cc: Daniel Vetter <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-04-03drm/amd/display: In VRR mode, do DRM core vblank handling at end of vblank. (v2)Mario Kleiner4-13/+47
In VRR mode, proper vblank/pageflip timestamps can only be computed after the display scanout position has left front-porch. Therefore delay calls to drm_crtc_handle_vblank(), and thereby calls to drm_update_vblank_count() and pageflip event delivery, to after the end of front-porch when in VRR mode. We add a new vupdate irq, which triggers at the end of the vupdate interval, ie. at the end of vblank, and calls the core vblank handler function. The new irq handler is not executed in standard non-VRR mode, so vblank handling for fixed refresh rate mode is identical to the past implementation. v2: Implement feedback by Nicholas and Paul Menzel. Signed-off-by: Mario Kleiner <[email protected]> Acked-by: Harry Wentland <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-08-21Revert "drm/amdgpu/display: Replace CONFIG_DRM_AMD_DC_DCN1_0 with CONFIG_X86"Leo (Sunpeng) Li2-2/+2
This reverts commit 8624c3c4dbfe24fc6740687236a2e196f5f4bfb0. We need CONFIG_DRM_AMD_DC_DCN1_0 to guard code that is using fp math. Acked-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Leo (Sunpeng) Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-19drm/amdgpu/display: Replace CONFIG_DRM_AMD_DC_DCN1_0 with CONFIG_X86Michel Dänzer2-2/+2
Allowing CONFIG_DRM_AMD_DC_DCN1_0 to be disabled on X86 was an opportunity for display with Raven Ridge accidentally not working. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: off by one in find_irq_source_info()Dan Carpenter1-1/+1
The ->info[] array has DAL_IRQ_SOURCES_NUMBER elements so this condition should be >= instead of > or we could read one element beyond the end of the array. Fixes: 4562236b3bc0 ("drm/amd/dc: Add dc display driver (v2)") Signed-off-by: Dan Carpenter <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-03-05drm/amd/display: Don't blow up if TG is NULL in dce110_vblank_setHarry Wentland1-1/+1
Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Roman Li <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-03-05drm/amd/display: Clean up formatting in irq_service_dce110.cHarry Wentland1-36/+26
Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Roman Li <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-03-05drm/amd/display: define DC_LOGGER for loggerBhawanpreet Lakha2-12/+9
Created a DC_LOGGER define. This is used to pass the logger into the macros. Anywhere we need to use the logger we need to define DC_LOGGER Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-03-05drm/amd/display: Use MACROS instead of dm_loggerBhawanpreet Lakha2-8/+8
Created MACROS for all log levels. Also Replaced usage of dm_logger_write to the defined MACROS Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/dc: include new ip and ip_offset headersHawking Zhang2-2/+4
Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-19BackMerge tag 'v4.15-rc4' into drm-nextDave Airlie1-0/+21
Linux 4.15-rc4 Daniel requested it to fix some messy conflicts.
2017-12-06drm/amd/include:cleanup raven1 dcn header files.Feifei Xu1-2/+2
Cleanup asic_reg/raven1/DCN folder.Remove unused dcn_1_0_default.h. Signed-off-by: Feifei Xu <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup vega10 header files.Feifei Xu2-2/+2
Remove asic_reg/vega10 folder. Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-06drm/amd/include:cleanup vega10 dce header files.Feifei Xu1-2/+2
Cleanup asic_reg/vega10/DC folder.Remove dce_12_0_default.h. Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-12-04drm/amdgpu: add license to MakefilesAlex Deucher1-0/+21
Was missing license text. Acked-by: Harry Wentland <[email protected]> Acked-by: Felix Kuehling <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-29amdgpu/dc: fix construct return values on irq service.Dave Airlie6-45/+22
This just removes more unused return/errors paths. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-28amdgpu/dc: add static to construct functionDave Airlie1-1/+1
There was a global construct symbol in the module symbols, kill it. Signed-off-by: Dave Airlie <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2017-09-28drm/amd/display: Use kernel alloc/freeHarry Wentland5-9/+13
Abstractions are frowned upon. cocci script: virtual context virtual patch virtual org virtual report @@ expression ptr; @@ - dm_alloc(ptr) + kzalloc(ptr, GFP_KERNEL) @@ expression ptr, size; @@ - dm_realloc(ptr, size) + krealloc(ptr, size, GFP_KERNEL) @@ expression ptr; @@ - dm_free(ptr) + kfree(ptr) v2: use GFP_KERNEL, not GFP_ATOMIC. add cocci script Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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