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path: root/drivers/gpu/drm/amd/display/dc/calcs
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2019-05-31drm/amd/display: fix crash on setmode when mode is close to bw limitSu Sung Chung1-2/+13
[why] during It's possible to call dcn_validate_bandwidth with no plane. In that case, as we are only intersted in if output timing is supported or not, even if we cannot support native resolution, we still want to support lower resolution if it is valid [how] if there exist no surface, make viewport/rec_out size at max 1080p. It is already known that 1080p x 6(max # of pipes) is supported, so if we fail validation, it is because of the stream Signed-off-by: Su Sung Chung <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-05-31drm/amd/display: fix calculation of total_data_read_bandwidthSu Sung Chung1-1/+38
[why] by adding fast_validate flag, we are skipping some portion of dcn_validate_bandwidth code that is not necessary for mode validation. However we have a bug where it does not calculate v->total_data_read_bandwidth, which is one of the factors determines the result of the validation, and therefore report false positive during mode validation. [how] add calculation of v->total_data_read_bandwidth outside of the region that is guarded by fast_validate flag Signed-off-by: Su Sung Chung <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-05-31drm/amd/display: make clk mgr soc specificEric Yang2-2/+2
[Why] First step of refactoring clk mgr to better handle different ways of handling clock operations. Clock operation policies are soc specific and not just DCN vesion specific. It is not a hw resource, should not be in the resource pool. [How] Change clock manager creation to be based on HW internal ID, rename clock manager members to be more clear. Move clock manager out of resource. Signed-off-by: Eric Yang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-04-15drm/amd/display: Add profiling tools for bandwidth validationJoshua Aberback1-0/+18
[Why] We used this change to investigate the performance of bandwidth validation, it will be useful to have if we need to investigate further. [How] We use performance counter tick numbers to profile performance, they live at dc->debug.bw_val_profile (set .enable in debugger to turn on measuring). Signed-off-by: Joshua Aberback <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <Bhawanpreet [email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-04-15drm/amd/display: Add fast_validate parameterJoshua Aberback1-2/+4
Add a fast_validate parameter in dc_validate_global_state for future use Signed-off-by: Joshua Aberback <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <Bhawanpreet [email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-04-03drm/amd/display: Fix multi-thread writing to 1 stateAidan Wood1-49/+49
[Why] Multiple threads were writing back to one global VBA in DC resulting in multiple threads overwriting eachother's data [How] Add an instance of DML (which contains VBA) to each context and change all calls that used dc->dml to use context->dml. Created a seperate copy constructor for linux in a case where there is no access to DC. Signed-off-by: Aidan Wood <[email protected]> Reviewed-by: Jun Lei <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-04-03Merge branch 'drm-next-5.2' of git://people.freedesktop.org/~agd5f/linux ↵Dave Airlie1-44/+54
into drm-next amdgpu: - Switch to HMM for userptr (reverted until HMM fixes land) - New experimental SMU 11 replacement for powerplay for vega20 (not enabled by default) - Initial RAS support for vega20 - BACO support for vega12 - BACO fixes for vega20 - Rework IH handling for page fault and retry interrupts - Cleanly split CPU and GPU paths for GPUVM updates - Powerplay fixes - XGMI fixes - Rework how DC interacts with atomic for planes - Clean up and simplify DC/Powerplay interfaces - Misc cleanups and bug fixes amdkfd: - Switch to HMM for userptr (reverted until HMM fixes land) - Add initial RAS support - MQD fixes ttm: - Unify DRM_FILE_PAGE_OFFSET handling - Account for kernel allocations in kernel zone only - Misc cleanups Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-03-27drm/amd/display: Populate macro_tile_size field for dmlJoshua Aberback1-40/+48
Create a functions to return swizzle types for dml Signed-off-by: Joshua Aberback <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-27drm/amd/display: add preferred pipe split logicJun Lei1-1/+1
[why] existing logic finds "first free pipe from 5 -> 0" to split this will cause certain sequences to require DC to move an MPCC from one tree to another, which is unsupported this leads to blackscreen to mitigate this problem, we will always try to acquire the "preferred" pipe, and each pipe has a unique preferred pipe this means we avoid most of the scenarios where pipe splitting leads to moving MPCC from one tree to another Signed-off-by: Jun Lei <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amd/display: fix up reference clock abstractionsJun Lei1-1/+1
[why] "reference clock" is a very overloaded variable in DC and causes confusion as there are multiple sources of reference clock, which may be different values incorrect input values to DML will cause DCHUB to be programmed improperly and lead to hard to debug underflow issues [how] instead of using ref clock everywhere, specify WHICH ref clock: - xtalin - dccg refclk - dchub refclk these are all distinct values which may not be equal Signed-off-by: Jun Lei <[email protected]> Reviewed-by: Yongqiang Sun <[email protected]> Acked-by: David Francis <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-19drm/amd/display: Add pp_smu null pointer checkCharlene Liu1-2/+4
res_pool->pp_smu may be NULL. Check before use Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Krunoslav Kovac <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-06drm/amd/display: don't call dm_pp_ function from an fpu blockHarry Wentland1-2/+6
Powerplay functions called from dm_pp_* functions tend to do a mutex_lock which isn't safe to do inside a kernel_fpu_begin/end block as those will disable/enable preemption. Rearrange the dm_pp_get_clock_levels_by_type_with_voltage calls to make sure they happen outside of kernel_fpu_begin/end. Cc: [email protected] Acked-by: Alex Deucher <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-03-05drm/amd/display: PPLIB HookupJun Lei1-1/+1
[Why] Make dml and integration with pplib clearer. [How] Change the way the dml formula is initialized to make its values more clear. Restructure DC interface with pplib into rv_funcs. Cap clocks received from pplib. Signed-off-by: Jun Lei <[email protected]> Signed-off-by: Eryk Brol <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-02-06drm/amdgpu/display: fix compiler errors [-Werror,-Wparentheses-equality]Pratik Vishwakarma1-1/+1
Remove extraneous parentheses around the comparison to silence this warning Signed-off-by: Pratik Vishwakarma <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-29Revert "drm/amd/display: add -msse2 to prevent Clang from emitting libcalls ↵Alex Deucher1-1/+1
to undefined SW FP routines" This reverts commit 10117450735c7a7c0858095fb46a860e7037cb9a. Causes a crash. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=109487 Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 4.19
2019-01-25drm/amd/display: add -msse2 to prevent Clang from emitting libcalls to ↵[email protected]1-1/+1
undefined SW FP routines arch/x86/Makefile disables SSE and SSE2 for the whole kernel. The AMDGPU drivers modified in this patch re-enable SSE but not SSE2. Turn on SSE2 to support emitting double precision floating point instructions rather than calls to non-existent (usually available from gcc_s or compiler_rt) floating point helper routines. Link: https://gcc.gnu.org/onlinedocs/gccint/Soft-float-library-routines.html Link: https://github.com/ClangBuiltLinux/linux/issues/327 Cc: [email protected] # 4.19 Reported-by: S, Shirish <[email protected]> Reported-by: Matthias Kaehlcke <[email protected]> Suggested-by: James Y Knight <[email protected]> Suggested-by: Nathan Chancellor <[email protected]> Signed-off-by: Nick Desaulniers <[email protected]> Tested-by: Guenter Roeck <[email protected]> Tested-by: Matthias Kaehlcke <[email protected]> Tested-by: Nathan Chancellor <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: Use 100 Hz precision for pipe pixel clocksKen Chalmers2-10/+10
[Why] Users would like more accurate pixel clocks, especially for fractional "TV" frame rates like 59.94 Hz. [How] Store and communicate pixel clocks with 100 Hz accuracy from dc_crtc_timing through to BIOS command table setpixelclock call. Signed-off-by: Ken Chalmers <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: update DCN dml calcsDmytro Laktyushkin1-7/+0
DV have made updates to DCN dml which we need to pull in Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Eric Bernstein <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: remove sink reference in dc_stream_stateJun Lei1-1/+1
[why] dc_stream_state containing a pointer to sink is poor design. Sink describes the display, and the specifications or capabilities it has. That information is irrelevant for dc_stream_state, which describes hardware state, and is generally used for hardware programming. It could further be argued that dc_sink itself is just a convenience dc provides, and DC should be perfectly capable of programming hardware without any dc_sinks (for example, emulated sinks). [how] Phase 1: Deprecate use of dc_sink pointer in dc_stream. Most references are trivial to remove, but some call sites are risky (such as is_timing_changed) with no obvious logical replacement. These will be removed in follow up change. Add dc_link pointer to dc_stream. This is the typical reason DC really needed sink pointer, and most call sites are replaced with this. DMs also need minor updates, as all 3 DMs leverage stream->sink for some functionality. this is replaced instead by a pointer to private data inside dc_stream_state, which is used by DMs as a quality of life improvment for some key functionality. it allows DMs to set pointers have to their own objects which associate OS objects to dc_stream_states (such as DisplayTarget and amdgpu_dm_connector). Without the private pointer, DMs would be forced to perform a lookup for callbacks. Signed-off-by: Jun Lei <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: David Francis <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-01-14drm/amd/display: update bw formula to v252Eric Yang1-9/+34
[why] There was a recent fix in the BW spreadsheet to allow timing with very large vblank. Need to be ported into driver. Signed-off-by: Eric Yang <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Dmytro Laktyushkin <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-11-05drm/amd/display: Retiring set_display_requirements in dm_pp_smu.h - part4Fatemeh Darbehani1-16/+16
[Why] In DCN we want direct DC to SMU calls, with minimal interference from pplib. The reason for each pp_smu interface mapping to 1 SMU message is so we can have the sequencing of different SMU message in DC and shared across different OS's. This will also simplify debugging as DAL owns this interaction and there's no confusion about division of ownership. [How] Part 4: Change clock units so they match the values PPLib sends to SMU. Signed-off-by: Fatemeh Darbehani <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-26drm/amd/display: program v_update and v_ready with proper fieldSu Sung Chung2-10/+10
[WHY] There are two different variables used to calculate v_update and v_ready, one for validation and the other for performance parameter calculation. Before the variable for validation was used which caused underflow on 1080edp with vsr enabled [HOW] program v_update and v_ready with the variables for performance parameter calculation Signed-off-by: Su Sung Chung <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-09-14drm/amd/display: Fix 3D stereo issues.Charlene Liu2-3/+8
We were not providing the correct pixel clocks to DML for marks calculation. Signed-off-by: Charlene Liu <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-08-27drm/amd/display: Move PME to function pointer call semanticsJun Lei1-0/+7
[why] Legacy IRI style is not linux friendly. [how] New function pointer call semantics will be used for all future PPLIB/DAL interfaces, and also some existing will be refactored. This change defines how the new function pointer structures will look, as well as implements Signed-off-by: Jun Lei <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Bhawanpreet Lakha <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-08-21Revert "drm/amdgpu/display: Replace CONFIG_DRM_AMD_DC_DCN1_0 with CONFIG_X86"Leo (Sunpeng) Li1-1/+1
This reverts commit 8624c3c4dbfe24fc6740687236a2e196f5f4bfb0. We need CONFIG_DRM_AMD_DC_DCN1_0 to guard code that is using fp math. Acked-by: Alex Deucher <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Leo (Sunpeng) Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-24drm/amd/display: separate dc_debug into dc_debug_options and dc_debug dataJun Lei1-1/+1
[why] confusing as to which part of debug is informational, and which part causes behavioral change Signed-off-by: Jun Lei <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Leo Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-19drm/amdgpu/display: Replace CONFIG_DRM_AMD_DC_DCN1_0 with CONFIG_X86Michel Dänzer1-1/+1
Allowing CONFIG_DRM_AMD_DC_DCN1_0 to be disabled on X86 was an opportunity for display with Raven Ridge accidentally not working. Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: dcc always on for bw calculations on ravenDmytro Laktyushkin1-1/+18
Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Charlene Liu <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-13drm/amd/display: Convert remaining loggers off dc_loggerNicholas Kazlauskas2-8/+7
- Removed dal/dm/dc loggers from linux, switched to kernel prints - Modified functions that used these directly to use macros - dc_logger support is completely dropped from Linux Signed-off-by: Nicholas Kazlauskas <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: Allow option to use worst-case watermarkTony Cheng1-1/+22
use worse case watermark (consider both DCC and VM) to keep golden consistent regardless of DCC Signed-off-by: Tony Cheng <[email protected]> Reviewed-by: Aric Cyr <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: remove dcn1 watermark sets b, c and dDmytro Laktyushkin1-1/+20
Currently dcn1 will not switch between watermark sets so we can save time by not calculating 3 extra sets. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: fix dcn1 watermark range reportingDmytro Laktyushkin1-84/+18
Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: clean rq/dlg/ttu reg structs before calculationsDmytro Laktyushkin1-0/+4
Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: get rid of cur_clks from dcn_bw_outputDmytro Laktyushkin1-14/+14
Cleans up dcn_bw_output to only contain calculated info, actual programmed values will now be stored in respective blocks. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Nikola Cornij <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: Introduce pp-smu raven functionsMikita Lipski1-2/+2
DM powerplay calls for DCN10 allowing to bypass PPLib and call directly to the SMU functions. Signed-off-by: Mikita Lipski <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: move clock programming from set_bandwidth to dccgDmytro Laktyushkin1-1/+1
This change moves dcn clock programming(with exception of dispclk) into dccg. This should have no functional effect. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: redesign dce/dcn clock voltage update requestDmytro Laktyushkin1-11/+11
The goal of this change is to move clock programming and voltage requests to a single function. As of this change only dce is affected. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-07-05drm/amd/display: replace clocks_value struct with dc_clocksDmytro Laktyushkin1-17/+17
This will avoid structs with duplicate information. Also removes pixel clock voltage request. This has no effect since pixel clock does not affect dcn voltage and this function only matters for dcn. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amd/display: get rid of 32.32 unsigned fixed pointDmytro Laktyushkin2-27/+27
32.32 is redundant, 31.32 does everything we use 32.32 for Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu/display: remove VEGAM config optionAlex Deucher1-4/+0
Leftover from bringup. No need to keep it around for upstream. Reviewed-by: Harry Wentland <[email protected]> Reviewed-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-15drm/amd/display: Implement VEGAM device IDs in DCJerry (Fangzhi) Zuo1-0/+9
Implement device IDs for VEGAM Signed-off-by: Jerry (Fangzhi) Zuo <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-04-11drm/amd/display: Fill calcs date from stream src/dst if availableJun Lei1-0/+13
We would otherwise fallback to the timing, which would always give us identity. Signed-off-by: Jun Lei <[email protected]> Reviewed-by: Wesley Chalmers <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-04-11drm/amd/display: Correct print types in DC_LOGSBhawanpreet Lakha1-37/+37
Correct the types used for printing in logs. This is needed for adding dynamic printing (LINUX), otherwise we get warnings. Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-04-11drm/amd/display: Adding stutter entry wm to dce bw structMikita Lipski1-2/+109
Adding the stutter_entry_wm object to dce_bw_output struct and populating it with bw calculations data Signed-off-by: Mikita Lipski <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-04-11drm/amd/display: Add debug prints for bandwidth calculationsBhawanpreet Lakha2-0/+585
Using the three functions we can print the dceip, vbios and data struct for bandwidth calculations. This is useful for debugging bandwidth calculation issues without a debugger Signed-off-by: Bhawanpreet Lakha <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-04-11drm/amd/display: fix Polaris 12 bw bounding boxDmytro Laktyushkin1-2/+119
Signed-off-by: Dmytro Laktyushkin <[email protected]> Signed-off-by: Harry Wentland <[email protected]> Reviewed-by: Bhawanpreet Lakha <[email protected]> Acked-by: Harry Wentland <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-03-14drm/amd/display: clean up dcn pplib notification callDmytro Laktyushkin1-3/+1
We have unused variables being populated when notifying pplib. This change amends that. Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-03-14drm/amd/display: update dce_calcs to latest versionDmytro Laktyushkin1-56/+104
Bw spreadsheet was updated while dce_calcs was not Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-03-14drm/amd/display: Set disp clk in a safe way to avoid over high dpp clk. (v2)Yongqiang Sun1-0/+19
Increase clock, if current dpp div is 0 and request dpp div is 1, request clk is higher than maximum dpp clk as per dpm table. set dispclk to the value of maximum supported dpp clk set div to 1 set dispclk to request value. Decrease clock, currrent dpp div is 1 and request dpp div is 0, current clk is higher than maximum dpp clk as per dpm table. set dispclk to the value of maximum supported dpp clk set div to 0 set dispclk to request value. v2: squash in !DCN build fix Signed-off-by: Yongqiang Sun <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Reviewed-by: Dmytro Laktyushkin <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-03-05drm/amd/display: fix dcn1 dppclk when min dispclk patch appliesDmytro Laktyushkin1-1/+1
Applying min dispclk patch would result in incorrect dppclk divider without this change Signed-off-by: Dmytro Laktyushkin <[email protected]> Reviewed-by: Tony Cheng <[email protected]> Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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