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2022-07-13drm/amdgpu: Check BO's requested pinning domains against its preferred_domainsLeo Li1-0/+4
When pinning a buffer, we should check to see if there are any additional restrictions imposed by bo->preferred_domains. This will prevent the BO from being moved to an invalid domain when pinning. For example, this can happen if the user requests to create a BO in GTT domain for display scanout. amdgpu_dm will allow pinning to either VRAM or GTT domains, since DCN can scanout from either or. However, in amdgpu_bo_pin_restricted(), pinning to VRAM is preferred if there is adequate carveout. This can lead to pinning to VRAM despite the user requesting GTT placement for the BO. v2: Allow the kernel to override the domain, which can happen when exporting a BO to a V4L camera (for example). Signed-off-by: Leo Li <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2022-07-13drm/amdgpu/gfx11: add aggregated doorbell supportJack Xiao1-11/+71
Port aggregated doorbell support to gfx11. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-13drm/amdgpu/sdma6: add aggregated doorbell supportJack Xiao1-23/+57
Port aggregated doorbell support to sdma6. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-13drm/amdgpu/mes: ring aggregatged doorbell when mes queue is unmappedLe Ma4-34/+137
Ring aggregated doorbel to make unmapped queue scheduled in mes firmware. Signed-off-by: Le Ma <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-13drm/amdgpu/mes11: initialize aggregated doorbellJack Xiao1-1/+57
Allocate and enable aggregated doorbell. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-13drm/amdgpu/mes: init aggregated doorbellLe Ma3-6/+70
Allocate and enable aggregated doorbell. Signed-off-by: Le Ma <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-13drm/amdgpu: support reset flag set for gpu resetLikun Gao9-27/+74
Move reset_context out of gpu recover function to make it configurable for different reset purpose. For the reset way of call gpu_recovery sysfs, force to use full reset method. Otherwise, try soft reset by default if the related ASIC supportted, if soft reset failed, will use full reset. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-13drm/amdgpu: support SDMA soft recovery for sdma v6Likun Gao1-14/+37
Support SDMA soft reset for SDMA v6. V3: use ib test to check soft reset. V4: squash in unused variable fix (Alex) Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-13drm/amdgpu: enable soft reset for gfx 11Likun Gao1-1/+7
Enable soft reset for gfx 11. V2: enable both gfx v11.0.0 and gfx v11.0.2. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-13drm/amdgpu: support gfx soft reset for gfx v11Likun Gao1-49/+132
Support GFX soft reset for gfx v11. V3: use ib test check soft reset. V4: squash in unused variable fix (Alex) Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-12drm/amdgpu/mes: set correct mes ring ready flagJack Xiao2-0/+6
Set corresponding ready flag for mes ring when enable or disable mes ring. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-12drm/amdgpu: Remove one duplicated ef removalxinhui pan1-6/+0
That has been done in BO release notify. Signed-off-by: xinhui pan <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-12drm/amdgpu/gmc10: adjust gart size for parts that support S/G displayAlex Deucher1-3/+14
For GMC 10 parts which support scatter/gather display (display from system memory), we should allocate a larger gart size to better handler larger displays. This mirrors what we already do for GMC 9 parts. v2: fix typo (Alex) Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-12drm/amdgpu/mes: fix bo va unmap issue in mesJack Xiao2-3/+60
Need reserve buffers before unmap mes ctx bo va. v2: fix removal of dma_resv_excl_fence() (Alex) v3: fix dma_resv_usage (Alex) Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-08drm/amdgpu/mes: fix mes submission in atomic contextJack Xiao4-85/+50
For some cases (accessing registers, unmap legacy queue), it needs access mes in atomic context. Use spinlock to protect agaist mes ring buffer race condition. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-05drm/amdgpu/display: disable prefer_shadow for generic fb helpersAlex Deucher5-5/+10
Seems to break hibernation. Disable for now until we can root cause it. Fixes: 087451f372bf ("drm/amdgpu: use generic fb helpers instead of setting up AMD own's.") Bug: https://bugzilla.kernel.org/show_bug.cgi?id=216119 Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-05drm/amdgpu: keep fbdev buffers pinned during suspendAlex Deucher1-4/+21
Was dropped when we converted to the generic helpers. Fixes: 087451f372bf ("drm/amdgpu: use generic fb helpers instead of setting up AMD own's.") Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-05drm/amdpgu/debugfs: Simplify some exit pathsAndré Almeida1-65/+42
To avoid code repetition, unify the function exit path when possible. No functional changes. Acked-by: Christian König <[email protected]> Signed-off-by: André Almeida <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-05drm/amdgpu/mes: Fix an error handling path in amdgpu_mes_self_test()Jianglei Nie1-1/+3
if amdgpu_mes_ctx_alloc_meta_data() fails, we should call amdgpu_vm_fini() to handle amdgpu_vm_init(). Add a new lable before amdgpu_vm_init() and goto this lable when amdgpu_mes_ctx_alloc_meta_data() fails. Signed-off-by: Jianglei Nie <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-05drm/amdgpu/mes11: fix to unmap legacy queueJack Xiao1-5/+4
MES fw updated to support unmapping legacy gfx/compute queue. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-05drm/amdgpu: skip whole ras bad page framework on sriovStanley.Yang1-1/+1
It should not init whole ras bad page framework on sriov guest side due to it is handled on host side. Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-05drm/amdgpu: Only send ras feature for gfx blockStanley.Yang1-16/+20
GFX is the only IP block that RAS TA needs to program the hardware when receiving enable_feature command. Changed from V1: remove amdgpu_ras_need_send_ras_feature inline function, use GFX RAS block check directly. Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-07-05drm/amdkfd: simplify vm_validate_pt_pd_bosLang Yu2-14/+8
We don't need to validate and map root PD specially here, it would be validated and mapped by amdgpu_vm_validate_pt_bos if it is evicted. The special case is when turning a GFX VM to a compute VM, if vm_update_mode changed, we should make sure root PD gets mapped. So just map root PD after updating vm->update_funcs in amdgpu_vm_make_compute whether the vm_update_mode changed or not. v3: - Add some comments suggested by Christian. v2: - Don't rename vm_validate_pt_pd_bos and make it public. Signed-off-by: Lang Yu <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-30drm/amdkfd: Add user queue eviction restore SMI eventPhilip Yang2-5/+9
Output user queue eviction and restore event. User queue eviction may be triggered by svm or userptr MMU notifier, TTM eviction, device suspend and CRIU checkpoint and restore. User queue restore may be rescheduled if eviction happens again while restore. Signed-off-by: Philip Yang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-30Revert "drm/amdgpu/gmc11: avoid cpu accessing registers to flush VM"Jack Xiao1-50/+1
This reverts commit 8748de873fedf4d55bdd99bbb738ee7ddf329792 since drv enabled mes to access registers. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-30drm/amdgpu: enable mes to access registers v2Jack Xiao4-1/+16
Enable mes to access registers. v2: squash mes sched ring enablement flag Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-30drm/amdgpu/mes: add mes register access interfaceJack Xiao1-1/+131
Add mes register access routines: 1. read register 2. write register 3. wait register 4. write and wait register Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-30drm/amdgpu/mes11: add mes11 misc opJack Xiao1-0/+53
Add misc op commands in mes11. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-30drm/amdgpu: add common interface for mes misc opJack Xiao1-0/+46
Add common interface for mes misc op, including accessing register interface. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-29drm/amdgpu: fix documentation warningAlex Deucher1-1/+1
Fixes this issue: drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:5094: warning: expecting prototype for amdgpu_device_gpu_recover_imp(). Prototype was for amdgpu_device_gpu_recover() instead Fixes: cf727044144d ("drm/amdgpu: Rename amdgpu_device_gpu_recover_imp back to amdgpu_device_gpu_recover") Reviewed-by: Kent Russell <[email protected]> Reported-by: Stephen Rothwell <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-29drm/amd/display: expose additional modifier for DCN32/321Aurabindo Pillai1-2/+1
[Why&How] Some userspace expect a backwards compatible modifier on DCN32/321. For hardware with num_pipes more than 16, we expose the most efficient modifier first. As a fall back method, we need to expose slightly inefficient modifier AMD_FMT_MOD_TILE_GFX9_64K_R_X after the best option. Also set the number of packers to fixed value as required per hardware documentation. This value is cached during hardware initialization and can be read through the base driver. Signed-off-by: Aurabindo Pillai <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-29drm/amd: Load TA firmware for DCN321/DCN32Aurabindo Pillai1-0/+6
[Why&How] TA firmware is needed to enable HDCP. Changes in v2: Load separate firmware for PSP 13.0.0 Signed-off-by: Aurabindo Pillai <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-29drm/amdgpu: Fix typos in amdgpu_stop_pending_resetsKent Russell1-2/+2
Change amdggpu to amdgpu and pedning to pending Signed-off-by: Kent Russell <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-28drm/amdgpu: Follow up change to previous drm scheduler change.Andrey Grodzovsky4-11/+29
Align refcount behaviour for amdgpu_job embedded HW fence with classic pointer style HW fences by increasing refcount each time emit is called so amdgpu code doesn't need to make workarounds using amdgpu_job.job_run_counter to keep the HW fence refcount balanced. Also since in the previous patch we resumed setting s_fence->parent to NULL in drm_sched_stop switch to directly checking if job->hw_fence is signaled to short circuit reset if already signed. Signed-off-by: Andrey Grodzovsky <[email protected]> Tested-by: Yiqing Yao <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-28drm/amdgpu: Prevent race between late signaled fences and GPU reset.Andrey Grodzovsky3-0/+23
Problem: After we start handling timed out jobs we assume there fences won't be signaled but we cannot be sure and sometimes they fire late. We need to prevent concurrent accesses to fence array from amdgpu_fence_driver_clear_job_fences during GPU reset and amdgpu_fence_process from a late EOP interrupt. Fix: Before accessing fence array in GPU disable EOP interrupt and flush all pending interrupt handlers for amdgpu device's interrupt line. v2: Switch from irq_get/put to full enable/disable_irq for amdgpu Signed-off-by: Andrey Grodzovsky <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-28drm/amdgpu: Add put fence in amdgpu_fence_driver_clear_job_fencesAndrey Grodzovsky1-1/+3
This function should drop the fence refcount when it extracts the fence from the fence array, just as it's done in amdgpu_fence_process. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-28drm/amdgpu: Remove useless amdgpu_display_freesync_ioctl() declarationLeslie Shi1-2/+0
Signed-off-by: Leslie Shi <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-28drm/amdgpu: add mc wptr addr support for mesJack Xiao4-3/+18
MES requires mc wptr address for usermode queues. Export bo gart address for mc wptr address. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-28drm/amdgpu: update GFX11 cs settingsEvan Quan1-149/+158
Update GFX11 cs related settings. Signed-off-by: Evan Quan <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-23drm/amdkfd: Fix spelling mistake "mechanim" -> "mechanism"Colin Ian King1-1/+1
There is a spelling mistake in a pr_debug message. Fix it. Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-23Revert "drm/amdgpu/display: set vblank_disable_immediate for DC"Alex Deucher1-0/+1
This reverts commit 92020e81ddbeac351ea4a19bcf01743f32b9c800. This causes stuttering and timeouts with DMCUB for some users so revert it until we understand why and safely enable it to save power. Bug: https://gitlab.freedesktop.org/drm/amd/-/issues/1887 Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: Nicholas Kazlauskas <[email protected]>
2022-06-23drm/amdgpu: drop unexpected word 'for' in commentsJiang Jian1-1/+1
there is an unexpected word 'for' in the comments that need to be dropped file - drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c line - 245 * position and also advance the position for for Vega10 changed to: * position and also advance the position for Vega10 Signed-off-by: Jiang Jian <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-23drm/amdgpu: Update mes_v11_api_def.hGraham Sider3-0/+4
Update MES API to support oversubscription without aggregated doorbell for usermode queues. v2: Change oversubscription_no_aggregated_en to is_kfd_process (align with MES) Signed-off-by: Graham Sider <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-23drm/amdkfd: Enable GFX11 usermode queue oversubscriptionGraham Sider3-0/+57
Starting with GFX11, MES requires wptr BOs to be GTT allocated/mapped to GART for usermode queues in order to support oversubscription. In the case that work is submitted to an unmapped queue, MES must have a GART wptr address to determine whether the queue should be mapped. This change is accompanied with changes in MES and is applicable for MES_API_VERSION >= 2. v3: - Use amdgpu_vm_bo_lookup_mapping for wptr_bo mapping lookup - Move wptr_bo refcount increment to amdgpu_amdkfd_map_gtt_bo_to_gart - Remove list_del_init from amdgpu_amdkfd_map_gtt_bo_to_gart - Cleanup/fix create_queue wptr_bo error handling v4: - Add MES version shift/mask defines to amdgpu_mes.h - Change version check from MES_VERSION to MES_API_VERSION - Add check in kfd_ioctl_create_queue before wptr bo pin/GART map to ensure bo is a single page. Signed-off-by: Graham Sider <[email protected]> Acked-by: Alex Deucher <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Philip Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-23drm/amdgpu: Fetch MES scheduler/KIQ versionsGraham Sider2-0/+15
Store MES scheduler and MES KIQ version numbers in amdgpu_mes for GFX11. Signed-off-by: Graham Sider <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Jack Xiao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-23drm/amdgpu: To flush tlb for MMHUB of RAVEN seriesRuili Ji1-1/+2
amdgpu: [mmhub0] no-retry page fault (src_id:0 ring:40 vmid:8 pasid:32769, for process test_basic pid 3305 thread test_basic pid 3305) amdgpu: in page starting at address 0x00007ff990003000 from IH client 0x12 (VMC) amdgpu: VM_L2_PROTECTION_FAULT_STATUS:0x00840051 amdgpu: Faulty UTCL2 client ID: MP1 (0x0) amdgpu: MORE_FAULTS: 0x1 amdgpu: WALKER_ERROR: 0x0 amdgpu: PERMISSION_FAULTS: 0x5 amdgpu: MAPPING_ERROR: 0x0 amdgpu: RW: 0x1 When memory is allocated by kfd, no one triggers the tlb flush for MMHUB0. There is page fault from MMHUB0. v2:fix indentation v3:change subject and fix indentation Signed-off-by: Ruili Ji <[email protected]> Reviewed-by: Philip Yang <[email protected]> Reviewed-by: Aaron Liu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-22drm/amdgpu/vcn: fix no previous prototype warningRuijing Dong1-1/+1
Declare 'static', as the function is not intended to be used outside of this translation unit. Fixes: 4ed49c954e35 ("drm/amdgpu/vcn: add unified queue ib test") Reported-by: kernel test robot <[email protected]> Reviewed-by: James Zhu <[email protected]> Signed-off-by: Ruijing Dong <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amdgpu: vm - drop unexpected word "the" in the commentsJiang Jian1-1/+1
there is an unexpected word "the" in the comments that need to be dropped file: drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c line: 57 * the kernel tells the the ring what VMID to use for that command changed to * the kernel tells the ring what VMID to use for that command Signed-off-by: Jiang Jian <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amdgpu: fix adev variable used in amdgpu_device_gpu_recover()Alex Deucher1-1/+1
Use the correct adev variable for the drm_fb_helper in amdgpu_device_gpu_recover(). Noticed by inspection. Fixes: 087451f372bf ("drm/amdgpu: use generic fb helpers instead of setting up AMD own's.") Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2022-06-21drm/amdgpu: Drop CONFIG_BACKLIGHT_CLASS_DEVICE ifdefsHans de Goede3-24/+0
The DRM_AMDGPU Kconfig code contains: select BACKLIGHT_CLASS_DEVICE So the condition these ifdefs test for is always true, drop them. Signed-off-by: Hans de Goede <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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