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path: root/drivers/gpu/drm/amd/amdgpu
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2018-05-24drm/amdgpu: cleanup amdgpu_vm_validate_pt_bos v2Christian König1-12/+7
Use list_for_each_entry_safe here. v2: Drop the optimization, it doesn't work as expected. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-24drm/amdgpu: rework VM state machine lock handling v2Christian König2-49/+21
Only the moved state needs a separate spin lock protection. All other states are protected by reserving the VM anyway. v2: fix some more incorrect cases Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-24drm/amdgpu: Add runtime VCN PG supportRex Zhu2-18/+30
Enable support for dynamically powering up/down VCN on demand. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-24drm/amdgpu: Enable VCN static PG by default on RVRex Zhu1-1/+2
Enable static VCN powergating by default on Raven. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-24drm/amdgpu: Add VCN static PG support on RVRex Zhu2-1/+102
Implement static powergating suport on VCN. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-24drm/amdgpu: Enable VCN CG by default on RVRex Zhu1-1/+2
Enable VCN clockgating by default on Raven. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-24drm/amdgpu: Add static CG control for VCN on RVRex Zhu1-11/+39
Implement proper static clockgating support for VCN. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-24drm/amdgpu: Add SOC15_WAIT_ON_RREG macro defineRex Zhu1-0/+15
Add new macro to wait on a register field to be a specific value. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-24drm/amdgpu: skip CG for VCN when late_init/finiRex Zhu1-0/+2
VCN clockgating is handled manually like VCE and UVD. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-23drm/amdgpu/gmc9: disable partial wr rmw if ECC is not enabledAlex Deucher1-0/+1
The vbios mistakenly sets this bit on some boards without ECC. This can lead to reduced performance in some workloads. Disable the bit if the board does not have ECC. Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-23drm/amdgpu: add a df 1.7 implementation of enable_ecc_force_par_wr_rmwAlex Deucher1-0/+8
Needed for proper memory setup depending on whether ECC is enabled on a particular board. Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-23drm/amdgpu: add new DF callback for ECC setupAlex Deucher1-0/+2
The ForceParWrRMW setting needs to be enabled for ECC, but disabled when ECC is not enabled. Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Junwei Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-23Remove calls to suspend/resume atomic helpers from ↵Andrey Grodzovsky1-9/+1
amdgpu_device_gpu_recover. (v2) First of all it's already being called from the display code from amd_ip_funcs.suspend/resume hooks. Second of all, the place in amdgpu_device_gpu_recover it's being called is wrong for GPU stalls since it is called BEFORE we cancel and force completion of all in flight jobs which were not yet processed. So, as Bas pointed in the ticket we will try to wait for fence in amdgpu_pm_compute_clocks but the pipe is hanged so we end up in deadlock. v2: remove unused variable Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106500 Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu: fix insert nop for UVD4.2 ringLeo Liu1-2/+13
NO_OP register should be writen to 0 Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu: fix insert nop for UVD5 ringLeo Liu1-2/+13
NO_OP register should be writen to 0 Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu: fix insert nop for UVD6 ringLeo Liu1-2/+13
NO_OP register should be writen to 0 Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu: fix insert nop for UVD7 ringLeo Liu1-4/+6
NO_OP register should be writen to 0 Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu: fix insert nop for VCN decode ringLeo Liu1-6/+8
NO_OP register should be writen to 0 Signed-off-by: Leo Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu: Take vcn encode rings into account in idle workAlex Deucher1-0/+5
Take the encode rings into account in the idle work handler. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu: Take uvd encode rings into account in idle work (v2)Alex Deucher1-1/+4
Take the encode rings into account in the idle work handler. v2: fix typo: s/num_uvd_inst/num_enc_rings/ Reviewed-by: James Zhu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu: count fences from all uvd instances in idle handlerAlex Deucher1-1/+5
Current multi-UVD hardware uses a single clock and power source so handle all instances in the idle handler. Reviewed-by: James Zhu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amd/amdgpu: Code comments for the amdgpu_ttm.c driver. (v2)Tom St Denis1-7/+341
NFC just comments. (v2): Updated based on feedback from Alex Deucher. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu: remove unused memberChristian König1-3/+0
This lock isn't used any more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu: Skip drm_sched_entity related ops for KIQ ring.Andrey Grodzovsky1-3/+18
Following change 75fbed2 we never initialize or use the GPU scheduler for KIQ and hence we need to skip KIQ ring when iterating amdgpu_ctx's scheduler entites. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu: flag Vega20 as experimentalAlex Deucher1-6/+6
Must set amdgpu.exp_hw_support=1 on the kernel command line in grub to enable support. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu: Add vega20 pci idsFeifei Xu1-0/+7
Acked-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu: Switch to use df_v3_6_funcs for vega20 (v2)Feifei Xu1-1/+5
v2: fix whitespace (Alex) Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu/df: implement df v3_6 callback functions (v2)Feifei Xu3-1/+158
New df helpers for 3.6. v2: switch to using df 3.6 headers (Alex) Acked-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu/vg20:Enable UVD/VCE for Vega20James Zhu1-4/+2
Vega20 ucode load type is set to AMDGPU_FW_LOAD_DIRECT for default. So UVD/VCE needn't PSP IP block up. UVD/VCE for Vega20 can be enabled at this moment. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu/vg20:Enable 2nd instance queue maping for uvd 7.2James Zhu1-4/+10
Enable 2nd instance uvd queue maping for uvd 7.2. For user, only one UVD instance presents. there is two rings for uvd decode, and 4 rings for uvd encode. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu/vg20:Enable the 2nd instance IRQ for uvd 7.2James Zhu1-2/+10
For Vega20, the 2nd instance uvd IRQ using different client id. Enable the 2nd instance IRQ for uvd 7.2 Signed-off-by: James Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu/vg20:Enable the 2nd instance for uvdJames Zhu2-15/+22
For Vega20, set num of uvd instance to 2, to enble 2nd instance. The IB test build-in registers need update for vega20 2nd instance. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu/vg20:increase 3 rings for AMDGPU_MAX_RINGSJames Zhu1-1/+1
For Vega20, there are two UVD Hardware. One more UVD hardware adds one decode ring and two encode rings. So AMDGPU_MAX_RINGS need increase by 3. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu/vg20:Restruct uvd.inst to support multiple instancesJames Zhu5-590/+660
Vega20 has dual-UVD. Need add multiple instances support for uvd. Restruct uvd.inst, using uvd.inst[0] to replace uvd.inst->. Repurpose amdgpu_ring::me for instance index, and initialize to 0. There are no any logical changes here. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu/vg20:Restruct uvd to support multiple uvdsJames Zhu9-194/+205
Vega20 has dual-UVD. Need Restruct amdgpu_device::uvd to support multiple uvds. There are no any logical changes here. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu: Disable ip modules that are not ready yetFeifei Xu1-5/+9
Please enable above ips on soc15.c when they're available. Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amd/powerplay: update vega20 cg flags (v2)Evan Quan1-1/+17
v2: remove duplicate flag. Reviewed-by: Christian König <[email protected]> Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-18drm/amdgpu: conditionally compile amdgpu's amdkfd filesOded Gabbay3-9/+63
In case CONFIG_HSA_AMD is not chosen, there is no need to compile amdkfd files that reside inside amdgpu dirver. In addition, because amdkfd depends on x86_64 architecture and amdgpu is not, compiling amdkfd files under i386 architecture can cause compiler errors and warnings. This patch modifies amdgpu's makefile to build amdkfd files only if CONFIG_HSA_AMD is chosen. The only file to be compiled unconditionally is amdgpu_amdkfd.c There are stub functions that are compiled only if amdkfd is not compiled. In that case, calls from amdgpu driver proper will go to those functions instead of the real functions. v2: instead of using function pointers, use stub functions v3: initialize kgd2kfd to NULL in case amdkfd is not compiled Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Oded Gabbay <[email protected]>
2018-05-17drm/amdgpu: Set vega20 load_type to AMDGPU_FW_LOAD_DIRECT.Feifei Xu1-1/+2
Please revert this patch when psp load fw is enabled. Acked-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu: Use vbios table for gpu info on vega20Alex Deucher1-2/+12
Use the vbios table rather than gpu info firmware. Squash of the following patches: drm/amdgpu/vg20: fallback to vbios table if gpu info fw is not available (v2) drm/amdgpu: drop gpu_info firmware for vega20 Reviewed-by: Amber Lin <[email protected]> Reviewed-by: Hawking Zhang <Hawking.Zhang> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu/atomfirmware: add parser for gfx_info tableAlex Deucher2-0/+47
Add support for the gfx_info table on boards that use atomfirmware. Acked-by: Christian König <[email protected]> Reviewed-by: Hawking Zhang <Hawking.Zhang> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu: Add vega20 to dc support check (v2)Feifei Xu1-0/+1
v2: fix whitespace Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu: Add nbio support for vega20 (v2)Feifei Xu2-1/+19
Some register offset in nbio v7.4 are different with v7.0. v2: Use nbio7.0 for now. TODO: add a new nbio 7.4 module (Alex) Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu/soc15: Add ip blocks for vega20 (v2)Feifei Xu1-0/+1
Same as vega10 now. v2: squash in typo fix Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu/soc15: dynamic initialize ip offset for vega20Feifei Xu4-1/+59
Vega20 need a seperate vega20_reg_init.c due to ip base offset difference. Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu/soc15: Set common clockgating for vega20.Feifei Xu1-0/+1
Same as vega10 for now. Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu/soc15:Add vega20 soc15_common_early_init supportFeifei Xu1-0/+5
Set external_rev_id and disable cg,pg for now. Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu/gfx9: Add clockgatting support for vega20Feifei Xu1-0/+1
Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu/gfx9: Add support for vega20Feifei Xu1-0/+2
Reviewed-by: Christian König <[email protected]> Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-05-17drm/amdgpu/gfx9: Add gfx config for vega20. (v4)Feifei Xu1-0/+10
v2: clean up (Alex) v3: additional cleanups (Alex) v4: drop leftover TODO (Alex) Signed-off-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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