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2021-01-27ACPI: Test for ACPI_SUCCESS rather than !ACPI_FAILUREBjorn Helgaas1-2/+2
The double negative makes it hard to read "if (!ACPI_FAILURE(status))". Replace it with "if (ACPI_SUCCESS(status))". Signed-off-by: Bjorn Helgaas <[email protected]> Acked-by: Guenter Roeck <[email protected]> Acked-by: Alex Deucher <[email protected]> Acked-by: Takashi Iwai <[email protected]> Acked-by: Mark Brown <[email protected]> Signed-off-by: Rafael J. Wysocki <[email protected]>
2021-01-25drm/amdgpu: Fix masking binary not operator on two mask operationsColin Ian King1-2/+2
Currently the ! operator is incorrectly being used to flip bits on mask values. Fix this by using the bit-wise ~ operator instead. Addresses-Coverity: ("Logical vs. bitwise operator") Fixes: 3c9a7b7d6e7520 ("drm/amdgpu: update mmhub mgcg&ls for mmhub_v2_3") Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-25drm/amd/amdgpu: add error handling to amdgpu_virt_read_pf2vf_dataJingwen Chen1-1/+5
[Why] when vram lost happened in guest, try to write vram can lead to kernel stuck. [How] When the readback data is invalid, don't do write work, directly reschedule a new work. Signed-off-by: Jingwen Chen <[email protected]> Reviewed-by: Monk Liu<[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-25drm/amdgpu: race issue when jobs on 2 ring timeoutHorace Chen1-10/+59
Fix a racing issue when jobs on 2 rings timeout simultaneously. If 2 rings timed out at the same time, the amdgpu_device_gpu_recover will be reentered. Then the adev->gmc.xgmi.head will be grabbed by 2 local linked list, which may cause wild pointer issue in iterating. lock the device earily to prevent the node be added to 2 different lists. also increase karma for the skipped job since the job is also timed out and should be guilty. Signed-off-by: Horace Chen <[email protected]> Reviewed-by: Andrey Grodzovsky <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-25drm/amdgpu: Make contiguous pinning optionalFelix Kuehling1-1/+6
Enable pinning of VRAM without forcing it to be contiguous. When memory is already pinned, make sure it's contiguous if requested. Suggested-by: Christian König <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amdgpu: update mmhub mgcg&ls for mmhub_v2_3Aaron Liu1-23/+61
Starting from vangogh, the ATCL2 and DAGB0 registers relative to mgcg/ls has changed. For MGCG: Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL. For MGLS: Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL. Add DAGB0_(WR/RD)_CGTT_CLK_CTRL registers. Signed-off-by: Aaron Liu <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amdgpu: modify GCR_GENERAL_CNTL for VangoghJinzhou Su1-1/+3
GCR_GENERAL_CNTL is defined differently in gc_10_1_0_offset.h and gc_10_3_0_offset.h. Update GCR_GENERAL_CNTL for Vangogh. Signed-off-by: Jinzhou Su <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amdgpu: remove gpu info firmware of green sardineHuang Rui1-1/+0
The ip discovery is supported on green sardine, it doesn't need gpu info firmware anymore. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Prike Liang <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 5.10.x
2021-01-21drm/amdgpu: remove gpu info firmware of green sardineHuang Rui1-1/+0
The ip discovery is supported on green sardine, it doesn't need gpu info firmware anymore. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Prike Liang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amdgpu:Add pcie gen5 support in pcie capability.Feifei Xu1-2/+14
Add PCIE_SPEED_32_0GT and PCIE GEN5 support for amdgpu. Signed-off-by: Feifei Xu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amdgpu: Allow GfxOff on Vangogh as defaultJinzhou Su1-0/+1
Send allow GfxOff message to SMU to enter GfxOff mode as default. Signed-off-by: Jinzhou Su <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amdgpu: update mmhub mgcg&ls for mmhub_v2_3Aaron Liu1-23/+61
Starting from vangogh, the ATCL2 and DAGB0 registers relative to mgcg/ls has changed. For MGCG: Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL. For MGLS: Replace mmMM_ATC_L2_MISC_CG with mmMM_ATC_L2_CGTT_CLK_CTRL. Add DAGB0_(WR/RD)_CGTT_CLK_CTRL registers. Signed-off-by: Aaron Liu <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-21drm/amdgpu: Add RLC_PG_DELAY_3 for VangoghJinzhou Su1-0/+15
Driver should enable the CGPG feature for RLC in safe mode to prevent any misalignment or conflict in middle of any power feature entry/exit sequence. Achieved by setting RLC_PG_CNTL.GFX_POWER_GATING_ENABLE = 0x1, and RLC_PG_DELAY_3.CGCG_ACTIVE_BEFORE_CGPG to the desired CGPG hysteresis value in refclk count. Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Jinzhou Su <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20drm/amdgpu: modify GCR_GENERAL_CNTL for VangoghJinzhou Su1-1/+3
GCR_GENERAL_CNTL is defined differently in gc_10_1_0_offset.h and gc_10_3_0_offset.h. Update GCR_GENERAL_CNTL for Vangogh. Signed-off-by: Jinzhou Su <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20drm/amdgpu: Remove GFXOFF MASK for VangoghJinzhou Su1-3/+0
1. Remove PP_GFXOFF_MASK and then GFXOFF can be enabled by user space. 2. GFXOFF is still disabled on Vangogh by default. 3. When GFXOFF feature on Vangogh landed, will enable GFXOFF by default. 4. GFXOFF can be enabled by debugfs interface amdgpu_gfxoff. Signed-off-by: Jinzhou Su <[email protected]> Acked-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20drm/amd/amdgpu: remove redundant flush_delayed_workJingwen Chen1-1/+0
When using cancel_delayed_work_sync, there's no need to flush_delayed_work first. This sequence can lead to a redundant loop of work executing. Signed-off-by: Jingwen Chen <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-20Merge tag 'amd-drm-next-5.12-2021-01-20' of ↵Daniel Vetter22-32/+741
https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.12-2021-01-20: amdgpu: - Fix non-x86 build - W=1 fixes from Lee Jones - Enable GPU reset on Navy Flounder - Kernel doc fixes - SMU workload profile fixes for APUs - Display updates - SR-IOV fixes - Vangogh SMU feature enablment and bug fixes - GPU reset support for Vangogh - Misc cleanups Conflicts: drivers/gpu/drm/amd/display/dc/dcn10/dcn10_mpc.c Resolve the conflict by picking the initialization value from amd from f03e80d2e82c ("drm/amd/display: Initialize stack variable") over the one Linus picked in 61d791365b72 ("drm/amd/display: avoid uninitialized variable warning"). It shouldn't matter. From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Daniel Vetter <[email protected]>
2021-01-20Merge tag 'drm-misc-next-2021-01-19' of ↵Daniel Vetter6-27/+28
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for v5.12: UAPI Changes: - Fix fourcc macro for amlogic video fbc. Cross-subsystem Changes: - Export pci_rebar_bytes_to_size. - Add a PCI quirk to increase bar0 for RX 5600 XT Pulse to max possible size. - Convert devicetree bindings to use the OF graph schema. - Update s6e63m0 bindings. - Make omapfb2 DSI_CM incompatible with drm/omap2 DSI-CM because of module conflicts. - Add Zack Rusin as vmwgfx maintainer. - Add CONFIG_DMABUF_DEBUG for validating dma-buf users don't loo kat struct page when importing or detaching. Core Changes: - Remove references to drm_device.pdev - Fix regression in ttm_bo_move_to_lru_tail(). - Assorted docbook updates. - Do not send dp-mst hotplug events on error when probing. - Move some agp macros to agpsupport.c, so it's not always compiled. - Move drm_need_swiotlb.h to drm_cache.c - Only build drm_memory.o for legacy drivers, and move CONFIG_DRM_VM to legacy. - Nuke drm_device.hose - Warn when the ttm resource manager is non-empty when disabling. - Assorted small fixes. Driver Changes: - Small assorted fixes in radeon, v3d, hisilicon, mipi-dbi, panfrost, hibmc, vc4, amdgpu, vkms, vmwgfx. - Move hisilicon to use simple encode. - Add writeback connector to vkms. - Add support for BT2020 to DE3. - Use gem prime mmap helpers in vc4, and move the mmap function upwards. - Use managed drm device, and cleanup error paths and display registers in vmwgfx. - Use correct bus_format and connector_type for innolux_n116bge. - Fix a lot of warnings with W=1 (Lee Jones) Signed-off-by: Daniel Vetter <[email protected]> From: Maarten Lankhorst <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-01-19drm/amdgpu: Remove accidentally added small unused hunk.Maarten Lankhorst1-1/+0
Commit 8f66090b7bb7 ("drm/amdgpu: Remove references to struct drm_device.pdev") accidentally adds an initialization of adev, which isn't used anywhere. This caused a compiler warning on the unused variable, remove it. Fixes: 8f66090b7bb7 ("drm/amdgpu: Remove references to struct drm_device.pdev") Cc: Thomas Zimmermann <[email protected]> Cc: Christian König <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Sam Ravnborg <[email protected]> Signed-off-by: Maarten Lankhorst <[email protected]> Reviewed-by: Thomas Zimmermann <[email protected]>
2021-01-15drm/amdgpu: updated fw attestation interfaceJohn Clements1-4/+3
updated interface to be compatible with latest FW Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-15drm/amdgpu: toggle on DF Cstate after finishing xgmi injectionGuchun Chen1-1/+1
Fixes: 5c23e9e05e42 ("drm/amdgpu: Update RAS XGMI error inject sequence") Signed-off-by: Guchun Chen <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-15drm/amdgpu: Remove unused variableNirmoy Das1-1/+0
Remove unused space_needed variable. Fixes: 453f617a30aa ("drm/amdgpu: Resize BAR0 to the maximum available size, even if it doesn't cover VRAM") Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Christian König <[email protected]> Link: https://patchwork.freedesktop.org/patch/413807/
2021-01-15Merge tag 'amd-drm-next-5.12-2021-01-08' of ↵Dave Airlie50-1103/+1778
https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.12-2021-01-08: amdgpu: - Rework IH ring handling on vega and navi - Rework HDP handling for vega and navi - swSMU documenation updates - Overdrive support for Sienna Cichlid and newer asics - swSMU updates for vangogh - swSMU updates for renoir - Enable FP16 on DCE8-11 - Misc code cleanups and bug fixes radeon: - Fixes for platforms that can't access PCI resources correctly - Misc code cleanups From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Dave Airlie <[email protected]>
2021-01-14drm/amdgpu: set power brake sequenceLikun Gao1-0/+32
Add function to set power brake sequence. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-14drm/amdgpu: set power brake sequenceLikun Gao1-0/+32
Add function to set power brake sequence. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-14drm/amdgpu: add new device id for Reniormengwang2-1/+3
add DID 0x164C into pciidlist under CHIP_RENOIR family. Signed-off-by: mengwang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 5.10.x
2021-01-14drm/amdgpu: add green_sardine device id (v2)Prike Liang1-0/+1
Add green_sardine PCI id support and map it to renoir asic type. v2: add apu flag Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 5.10.x
2021-01-14drm/amdgpu: fix vram type and bandwidth error for DDR5 and DDR4Huang Rui1-17/+36
This patch is to update atomfirmware parser for the memory type and bandwidth of DDR5 and DDR4. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-14drm/amdgpu/gfx10: add updated GOLDEN_TSC_COUNT_UPPER/LOWER register offsets ↵chen gong1-2/+14
for VGH The address of the GOLDEN_TSC_COUNT_UPPER/GOLDEN_TSC_COUNT_LOWER for Vnagogh are different from the others. The offset of the GOLDEN_TSC_COUNT_UPPER for Vangogh is 0x0025 by calculation. The offset of the GOLDEN_TSC_COUNT_LOWER for Vangogh is 0x0026 by calculation. Signed-off-by: chen gong <[email protected]> Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-14drm/amdgpu/psp: fix psp gfx ctrl cmdsVictor Zhao1-1/+1
psp GFX_CTRL_CMD_ID_CONSUME_CMD different for windows and linux, according to psp, linux cmds are not correct. v2: only correct GFX_CTRL_CMD_ID_CONSUME_CMD. Signed-off-by: Victor Zhao <[email protected]> Reviewed-by: Emily.Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-14drm/amdgpu: fix DRM_INFO flood if display core is not supported (bug 210921)Alexandre Demers1-1/+1
This fix bug 210921 where DRM_INFO floods log when hitting an unsupported ASIC in amdgpu_device_asic_has_dc_support(). This info should be only called once. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=210921 Signed-off-by: Alexandre Demers <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2021-01-13drm/amdgpu: Add secure display TA interfaceJinzhou Su8-3/+438
Add interface to load, unload, invoke command for secure display TA. v2: Add debugfs interface for secure display TA v3: fix warning in copy_from_user (Alex) Signed-off-by: Jinzhou.Su <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-13drm/amdgpu: Add Secure Display TA header fileJinzhou Su1-0/+154
Add file ta_secureDisplay_if.h for Secure Display TA Signed-off-by: Jinzhou Su <[email protected]> Reviewed-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-13drm/amdgpu: add new device id for Reniormengwang2-1/+3
add DID 0x164C into pciidlist under CHIP_RENOIR family. Signed-off-by: mengwang <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 5.10.x
2021-01-13drm/amdgpu: add green_sardine device id (v2)Prike Liang1-0/+1
Add green_sardine PCI id support and map it to renoir asic type. v2: add apu flag Signed-off-by: Prike Liang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 5.10.x
2021-01-13drm/amdgpu: fix vram type and bandwidth error for DDR5 and DDR4Huang Rui1-17/+36
This patch is to update atomfirmware parser for the memory type and bandwidth of DDR5 and DDR4. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-13drm/amdgpu/gfx10: add updated GOLDEN_TSC_COUNT_UPPER/LOWER register offsets ↵chen gong1-2/+14
for VGH The address of the GOLDEN_TSC_COUNT_UPPER/GOLDEN_TSC_COUNT_LOWER for Vnagogh are different from the others. The offset of the GOLDEN_TSC_COUNT_UPPER for Vangogh is 0x0025 by calculation. The offset of the GOLDEN_TSC_COUNT_LOWER for Vangogh is 0x0026 by calculation. Signed-off-by: chen gong <[email protected]> Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-13drm/amdgpu: Enable GPU reset for vangoghAlex Deucher1-0/+1
Enable GPU reset when we encounter a hang. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Huang Rui <[email protected]>
2021-01-13drm/amdgpu: fix mode2 reset sequence for vangoghAlex Deucher1-1/+33
We need to save and restore PCI config space. Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Huang Rui <[email protected]>
2021-01-13drm/amdgpu/nv: add mode2 reset handlingAlex Deucher1-2/+12
Vangogh will use mode2 reset, so plumb it through the nv soc driver. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Reviewed-by: Huang Rui <[email protected]> Signed-off-by: Huang Rui <[email protected]>
2021-01-13drm/amdgpu/sriov Stop data exchange for wholegpu resetJack Zhang3-0/+3
[Why] When host trigger a whole gpu reset, guest will keep waiting till host finish reset. But there's a work queue in guest exchanging data between vf&pf which need to access frame buffer. During whole gpu reset, frame buffer is not accessable, and this causes the call trace. [How] After vf get reset notification from pf, stop data exchange. Signed-off-by: Jingwen Chen <[email protected]> Signed-off-by: Jack Zhang <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-13drm/amdgpu: Decrease compute timeout to 10 s for sriov multiple VFEmily.Deng1-1/+4
For multiple VF, after engine hang,as host driver will first encounter FLR, so has no meanning to set compute to 60s. v2: Refine the patch and comment Signed-off-by: Emily.Deng <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-13drm/amdgpu: Remove references to struct drm_device.pdevThomas Zimmermann7-22/+21
Using struct drm_device.pdev is deprecated. Convert amdgpu to struct drm_device.dev. No functional changes. v3: * rebased Signed-off-by: Thomas Zimmermann <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Christian König <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-01-13drm/amdgpu: Fix trailing whitespacesThomas Zimmermann1-3/+3
Adhere to kernel coding style. Signed-off-by: Thomas Zimmermann <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Cc: Alex Deucher <[email protected]> Cc: Christian König <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-01-14drm/amdgpu: Resize BAR0 to the maximum available size, even if it doesn't ↵Nirmoy Das1-1/+5
cover VRAM This allows BAR0 resizing to be done for cards which don't advertise support for a size large enough to cover the VRAM but which do advertise at least one size larger than the default. For example, my RX 5600 XT, which advertises 256MB, 512MB and 1GB. Signed-off-by: Darren Salt <[email protected]> Signed-off-by: Christian König <[email protected]> Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Nirmoy Das <[email protected]> Link: https://patchwork.kernel.org/project/dri-devel/patch/[email protected]
2021-01-11drm/amd/amdgpu/vega20_ih: Add missing descriptions for 'ih' and fix spelling ↵Lee Jones1-1/+4
error Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/vega20_ih.c:378: warning: Function parameter or member 'ih' not described in 'vega20_ih_get_wptr' drivers/gpu/drm/amd/amdgpu/vega20_ih.c:421: warning: Function parameter or member 'ih' not described in 'vega20_ih_irq_rearm' drivers/gpu/drm/amd/amdgpu/vega20_ih.c:447: warning: Function parameter or member 'ih' not described in 'vega20_ih_set_rptr' Cc: Alex Deucher <[email protected]> Cc: "Christian König" <[email protected]> Cc: David Airlie <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Hawking Zhang <[email protected]> Cc: Feifei Xu <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Lee Jones <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-11drm/amd/amdgpu/amdgpu_ih: Update 'amdgpu_ih_decode_iv_helper()'s function headerLee Jones1-0/+2
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c:220: warning: Function parameter or member 'ih' not described in 'amdgpu_ih_decode_iv_helper' drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c:220: warning: Function parameter or member 'entry' not described in 'amdgpu_ih_decode_iv_helper' Cc: Alex Deucher <[email protected]> Cc: "Christian König" <[email protected]> Cc: David Airlie <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Felix Kuehling <[email protected]> Cc: [email protected] Cc: [email protected] Signed-off-by: Lee Jones <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-11drm/amdgpu: enable gpu recovery for navy_flounderJiansong Chen1-0/+1
Enable gpu recovery for navy_flounder by default to trigger reset once needed. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-08drm/amdgpu: fix DRM_INFO flood if display core is not supported (bug 210921)Alexandre Demers1-1/+1
This fix bug 210921 where DRM_INFO floods log when hitting an unsupported ASIC in amdgpu_device_asic_has_dc_support(). This info should be only called once. Bug: https://bugzilla.kernel.org/show_bug.cgi?id=210921 Signed-off-by: Alexandre Demers <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2021-01-08drm/amdgpu/psp: fix psp gfx ctrl cmdsVictor Zhao1-1/+1
psp GFX_CTRL_CMD_ID_CONSUME_CMD different for windows and linux, according to psp, linux cmds are not correct. v2: only correct GFX_CTRL_CMD_ID_CONSUME_CMD. Signed-off-by: Victor Zhao <[email protected]> Reviewed-by: Emily.Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>