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2020-12-23drm/amdgpu: add helper to init ih ring regs for navi10Hawking Zhang1-0/+47
navi10_ih_init_register_offset will be used to init register offset for all the available ih rings Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: correct ih cg programming for vega10 ih blockHawking Zhang1-6/+2
vega10/12 and RAVEN don't support soft override ih_buffer_mem_clk. Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: use cached ih rb control reg offsets for vega10Hawking Zhang1-40/+14
all the ih rb control register offsets are cached at the beginning of ih_sw_init. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: switch to ih_enable_ring for vega10Hawking Zhang1-87/+8
use vega10_ih_enable_ring to enable all the available ring buffers for vega10/12, RAVEN series and RENOIR APUs Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: switch to ih_toggle_interrupts for vega10Hawking Zhang1-134/+34
replace ih_enable_interrupts and ih_disable_interrupts with ih_toggle_interrupts Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: switch to ih_init_register_offset for vega10Hawking Zhang1-0/+3
Initialize ih control registers offset through helper function vega10_ih_init_register_offset. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: add helper to toggle ih ring interrupts for vega10Hawking Zhang1-0/+45
vega10_ih_toggle_ring_interrupts will be used to enable/disable an ih ring interrupts for vega10/12, RAVEN series and RENOIR APUs Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: add helper to enable an ih ring for vega10Hawking Zhang1-0/+52
vega10_ih_enable_ring will be used to enable an ih ring for vega10/12, RAVEN series and RENOIR. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: add helper to init ih ring regs for vega10Hawking Zhang1-0/+47
vega10_ih_init_register_offset will be used to init register offset for all the available ih rings Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: add amdgpu_ih_regs structureHawking Zhang1-0/+13
amdgpu_ih_regs holds all the registers for an ih ring Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: Fix a copy-pasta commentAlex Deucher1-2/+1
This is not a scsi driver. Reviewed-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: only set DP subconnector type on DP and eDP connectorsAlex Deucher1-4/+6
Fixes a crash in drm_object_property_set_value() because the property is not set for internal DP ports that connect to a bridge chips (e.g., DP to VGA or DP to LVDS). Bug: https://bugzilla.kernel.org/show_bug.cgi?id=210739 Fixes: 65bf2cf95d3ade ("drm/amdgpu: utilize subconnector property for DP through atombios") Tested-By: Kris Karas <[email protected]> Cc: Oleg Vasilev <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected] # 5.10.x
2020-12-23drm/amdgpu: check gfx pipe availability before toggling its interruptsHawking Zhang1-1/+8
GUI_IDLE interrupts controlled by CP_INT_CNTL_RING0 are only applicable to me0 pipe0. For ASICs that have gfx pipe removed, don't toggle those bits. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: remove unnecessary asic type checkHawking Zhang1-7/+4
The number of crtc should be 0 for ASICs that don't have display engine. Remove the unnecessary asic type check then. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: check number of gfx ring before init cp gfxHawking Zhang1-6/+6
Check number of gfx ring, rather than asic type, before cp gfx engine initialization so driver just need to make sure number of gfx ring is initialized correctly in gfx early_init phase. No need to add additional asic type check everywhere when there is new asic with gfx pipe removed. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-17drm/amdgpu: fix vbios reservation handling on SR-IOVAlex Deucher1-1/+2
There is no reserveration so set the size to 0. Fixes a regression on SR-IOV. Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-16Merge tag 'amd-drm-fixes-5.11-2020-12-16' of ↵Daniel Vetter18-54/+139
git://people.freedesktop.org/~agd5f/linux into drm-next amd-drm-fixes-5.11-2020-12-16: amdgpu: - Fix a eDP regression for DCE asics - SMU fixes for sienna cichlid - Misc W=1 fixes - SDMA 5.2 reset fix - Suspend/resume fix - Misc display fixes - Misc runtime PM fixes and cleanups - Dimgrey Cavefish fixes - printk cleanup - Documentation warning fixes amdkfd: - Error logging fix - Fix pipe offset calculation radeon: - printk cleanup Signed-off-by: Daniel Vetter <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-12-16drm/amdgpu: print mmhub client name for dimgrey_cavefishTao Zhou1-0/+1
This makes it easier to debug what block is causing the fault, same as sienna_cichlid. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-16drm/amdgpu: set mode1 reset as default for dimgrey_cavefishTao Zhou1-0/+1
Use mode1 reset for dimgrey_cavefish by default. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-15drm/amdgpu: remove h from printk format specifierTom Rix3-5/+5
See Documentation/core-api/printk-formats.rst. h should no longer be used in the format specifier for printk. Reviewed-by: Christian König <[email protected]> Signed-off-by: Tom Rix <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-15drm/amdgpu: fix regression in vbios reservation handling on headlessAlex Deucher1-4/+5
We need to move the check under the non-headless case, otherwise we always reserve the VGA save size. Fixes: 157fe68d74c2ad ("drm/amdgpu: fix size calculation with stolen vga memory") Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-15drm/amdgpu/SRIOV: Extend VF reset request wait periodJiange Zhao4-3/+23
In Virtualization case, when one VF is sending too many FLR requests, hypervisor would stop responding to this VF's request for a long period of time. This is called event guard. During this period of cooling time, guest driver should wait instead of doing other things. After this period of time, guest driver would resume reset process and return to normal. Currently, guest driver would wait 12 seconds and return fail if it doesn't get response from host. Solution: extend this waiting time in guest driver and poll response periodically. Poll happens every 6 seconds and it will last for 60 seconds. v2: change the max repetition times from number to macro. Signed-off-by: Jiange Zhao <[email protected]> Acked-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-15drm/amdkfd: correct amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu log.Yifan Zhang1-1/+1
it could also be insufficient vram that makes amdgpu_amdkfd_reserve_mem_limit fail. Signed-off-by: Yifan Zhang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-15drm/amdgpu: print what method we are using for runtime pmAlex Deucher1-0/+4
So we know when it's enabled and what method we are using. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-15drm/amdgpu: simplify logic in atpx resume handlingAlex Deucher1-4/+2
Simplify the logic in the runtime resume handling for atpx Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-15drm/amdgpu: no need to call pci_ignore_hotplug for _PR3Alex Deucher1-8/+1
The platform knows it's doing d3cold. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-15drm/amdgpu: support runtime pm for GPUs that support BOCOAlex Deucher1-1/+4
Enable runtime pm on non HG/PX BOCO capable boards. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-15drm/amdgpu: update amdgpu_device_supports_boco()Alex Deucher1-2/+2
Change it to check if the device has ACPI power resources. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-15drm/amdgpu: add check for ACPI power resourcesAlex Deucher2-0/+5
Check if the device has ACPI power resources so we can enable runtime pm if so. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-15drm/amdgpu: split BOCO and ATPX handlingAlex Deucher4-14/+42
In preparation for systems that support d3cold on dGPUs independent of PX/HG. No functional change intended. Acked-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-15drm/amdgpu: skip load smu and sdma microcode on sriov for SIENNA_CICHLIDStanley.Yang1-0/+3
skip load smu and sdma fw on sriov due to sos, ta and asd fw have been skipped for SIENNA_CICHLID. V2: move asic check into smu11 Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: Kevin Wang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-15drm/amdgpu: add judgement for suspend/resume sequenceLikun Gao3-8/+10
S0ix only makes sense on APUs since they are part of the platform, so only when the ASIC is APU should set amdgpu_acpi_is_s0ix_supported flag to deal with the related situation. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-15drm/amdgpu/sdma5.2: soft reset sdma blocks before setup and start sdmaXiaomeng Hou1-7/+32
Without doing the soft reset, register mmSDMA0_GFX_RB_WPTR's value could not be reset to 0 when sdma block resumes. That would cause the ring buffer's read and write pointers not equal and ring test fail. So add the soft reset step. Signed-off-by: Xiaomeng Hou <[email protected]> Reviewed-by: Huang Rui <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-15drm/ttm: cleanup LRU handling furtherChristian König1-1/+3
We only completely delete the BO from the LRU on destruction. Signed-off-by: Christian König <[email protected]> Acked-by: Andrey Grodzovsky <[email protected]> Link: https://patchwork.freedesktop.org/patch/404618/
2020-12-15Merge drm/drm-next into drm-misc-nextMaarten Lankhorst115-673/+1768
Required backmerge since we will be based on top of v5.11, and there has been a request to backmerge already to upstream some features. Signed-off-by: Maarten Lankhorst <[email protected]>
2020-12-15Merge tag 'drm-misc-next-2020-11-27-1' of ↵Daniel Vetter3-32/+25
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for 5.11: UAPI Changes: Cross-subsystem Changes: * char/agp: Disable frontend without CONFIG_DRM_LEGACY * mm: Fix fput in mmap error path; Introduce vma_set_file() to change vma->vm_file Core Changes: * dma-buf: Use sgtables in system heap; Move heap helpers to CMA-heap code; Skip sync for unmapped buffers; Alloc higher order pages is available; Respect num_fences when initializing shared fence list * doc: Improvements around DRM modes and SCALING_FILTER * Pass full state to connector atomic functions + callee updates * Cleanups * shmem: Map pages with caching by default; Cleanups * ttm: Fix DMA32 for global page pool * fbdev: Cleanups * fb-helper: Update framebuffer after userspace writes; Unmap console buffer during shutdown; Rework damage handling of shadow framebuffer Driver Changes: * amdgpu: Multi-hop fixes, Clenaups * imx: Fix rotation for Vivante tiled formats; Support nearest-neighour skaling; Cleanups * mcde: Fix RGB formats; Support DPI output; Cleanups * meson: HDMI clock fixes * panel: Add driver and bindings for Innolux N125HCE-GN1 * panel/s6e63m0: More backlight levels; Fix init; Cleanups * via: Clenunps * virtio: Use fence ID for handling fences; Cleanups Signed-off-by: Daniel Vetter <[email protected]> From: Thomas Zimmermann <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/20201127083055.GA29139@linux-uq9g
2020-12-14drm/amdkfd: fix ttm size refactor falloutDaniel Vetter1-4/+4
I guess Christian didn't compile test amdkfd. Acked-by: Alex Deucher <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Fixes: e11bfb99d6ec ("drm/ttm: cleanup BO size handling v3") Cc: Christian König <[email protected]> Cc: Huang Rui <[email protected]> (v1) Cc: Daniel Vetter <[email protected]> Cc: Felix Kuehling <[email protected]> Cc: [email protected] Signed-off-by: Daniel Vetter <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-12-14drm/ttm: cleanup BO size handling v3Christian König7-10/+10
Based on an idea from Dave, but cleaned up a bit. We had multiple fields for essentially the same thing. Now bo->base.size is the original size of the BO in arbitrary units, usually bytes. bo->mem.num_pages is the size in number of pages in the resource domain of bo->mem.mem_type. v2: use the GEM object size instead of the BO size v3: fix printks in some places Signed-off-by: Christian König <[email protected]> Reviewed-by: Huang Rui <[email protected]> (v1) Acked-by: Daniel Vetter <[email protected]> Link: https://patchwork.freedesktop.org/patch/406831/
2020-12-10drm/amdgpu: limit the amdgpu_vm_update_ptes trace pointChristian König1-2/+3
The text output should not be more than a page, so only print the first 32 page table entries. If we need all of them we can still look into the binary trace. Signed-off-by: Christian König <[email protected]> Reviewed-by: Shashank Sharma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-10drm/amdgpu: clean up bo in vce and vcn testNirmoy Das2-4/+7
BO created with amdgpu_bo_create_reserved() wasn't clean properly before, which causes: [ 21.056218] WARNING: CPU: 0 PID: 7 at drivers/gpu/drm/ttm/ttm_bo.c:518 ttm_bo_release+0x2bf/0x310 [ttm] <snip> [ 21.056430] Call Trace: [ 21.056525] amdgpu_bo_unref+0x1a/0x30 [amdgpu] [ 21.056635] amdgpu_vcn_dec_send_msg+0x1b2/0x270 [amdgpu] [ 21.056740] amdgpu_vcn_dec_get_create_msg.constprop.0+0xd8/0x100 [amdgpu] [ 21.056843] amdgpu_vcn_dec_ring_test_ib+0x27/0x180 [amdgpu] [ 21.056936] amdgpu_ib_ring_tests+0xf1/0x150 [amdgpu] [ 21.057024] amdgpu_device_delayed_init_work_handler+0x11/0x30 [amdgpu] [ 21.057030] process_one_work+0x1df/0x370 [ 21.057033] worker_thread+0x46/0x340 [ 21.057034] ? process_one_work+0x370/0x370 [ 21.057037] kthread+0x11b/0x140 [ 21.057039] ? __kthread_bind_mask+0x60/0x60 [ 21.057043] ret_from_fork+0x22/0x30 Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Link: https://patchwork.freedesktop.org/patch/406382/ Signed-off-by: Christian König <[email protected]>
2020-12-10Merge tag 'amd-drm-next-5.11-2020-12-09' of ↵Dave Airlie115-673/+1768
git://people.freedesktop.org/~agd5f/linux into drm-next amd-drm-next-5.11-2020-12-09: amdgpu: - SR-IOV fixes - Navy Flounder updates - Sienna Cichlid updates - Dimgrey Cavefish updates - Vangogh updates - Misc SMU fixes - Misc display fixes - Last big hunk of W=1 warning fixes - Cursor validation fixes - CI BACO updates From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected] Signed-off-by: Dave Airlie <[email protected]>
2020-12-09drm/amdgpu: Initialise drm_gem_object_funcs for imported BOsAndrey Grodzovsky2-20/+29
For BOs imported from outside of amdgpu, setting of amdgpu_gem_object_funcs was missing in amdgpu_dma_buf_create_obj. Fix by refactoring BO creation and amdgpu_gem_object_funcs setting into single function called from both code paths. Fixes: d693def4fd1c ("drm: Remove obsolete GEM and PRIME callbacks from struct drm_driver") v2: Use use amdgpu_gem_object_create() directly v3: fix warning Reviewed-by: Christian König <[email protected]> Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-08drm/amdgpu: fix size calculation with stolen vga memoryAlex Deucher1-0/+3
If we need to keep the stolen vga memory, make sure it is at least as big as the legacy vga size. Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-08drm/amdgpu: remove amdgpu_ttm_late_init and amdgpu_bo_late_initAlex Deucher9-36/+0
No longer used. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-08drm/amdgpu: free the pre-OS console framebuffer after the first modesetAlex Deucher1-6/+2
Rather than in late_init to avoid race conditions between freeing the buffers and the initial modeset. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-08drm/amdgpu: enable runtime pm using BACO on CI dGPUsAlex Deucher1-5/+1
Works using BACO. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-08drm/amdgpu/cik: enable BACO reset on BonaireAlex Deucher1-4/+0
Works now that the BACO sequence is fixed. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-08drm/amd/display: add S/G support for VangoghRoman Li1-0/+1
[Why] Scatter/gather feature is supported on Vangogh. [How] Add GTT domain support for Vangogh to enable display buffers in system memory. Signed-off-by: Roman Li <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-08drm/amdgpu: use AMDGPU_NUM_VMID when possibleNirmoy Das12-12/+12
Replace hardcoded vmid number with AMDGPU_NUM_VMID macro. Signed-off-by: Nirmoy Das <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-08drm/amdgpu: fix sdma instance fw version and feature version initStanley.Yang1-1/+1
each sdma instance fw_version and feature_version should be set right value when asic type isn't between SIENNA_CICHILD and CHIP_DIMGREY_CAVEFISH Signed-off-by: Stanley.Yang <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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