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path: root/drivers/gpu/drm/amd/amdgpu
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2021-01-08drm/amdgpu: Add new mode 2560x1440Emily.Deng1-2/+3
Add one more 2k resolution which appears frequently in market. Signed-off-by: Emily.Deng <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-07Merge tag 'drm-misc-next-2020-12-17' of ↵Daniel Vetter15-32/+34
git://anongit.freedesktop.org/drm/drm-misc into drm-next drm-misc-next for v5.12: UAPI Changes: - Not necessarily one, but we document that userspace needs to force probe connectors. Cross-subsystem Changes: - Require FB_ATY_CT for aty on sparc64. - video: Fix documentation, and a few compiler warnings. - Add devicetree bindings for DP connectors. - dma-buf: Update kernel-doc, and add might_lock for resv objects in begin/end_cpu_access. Core Changes: - ttm: Warn when releasing a pinned bo. - ttm: Cleanup bo size handling. - cma-helper: Remove prime infix, and implement mmap as GEM CMA functions. - Split drm_prime_sg_to_page_addr_arrays into 2 functions. - Add a new api to install irq using devm. - Update panel kerneldoc to inline style. - Add DP support to drm/bridge. - Assorted small fixes to ttm, fb-helper, scheduler. - Add atomic_commit_setup function callback. - Automatically use the atomic gamma_set, instead of forcing drivers to declare the default atomic version. - Allow using degamma for legacy gamma if gamma is not available. - Clarify that primary/cursor planes are not tied to 1 crtc (depending on possible_crtcs). - ttm: Cleanup the lru handler. Driver Changes: - Add pm support to ingenic. - Assorted small fixes in radeon, via, rockchip, omap2fb, kmb, gma500, nouveau, virtio, hisilicon, ingenic, s6e63m0 panel, ast, udlfb. - Add BOE NV110WTM-N61, ys57pss36bh5gq, Khadas TS050 panels. - Stop using pages with drm_prime_sg_to_page_addr_arrays, and switch all callers to use ttm_sg_tt_init. - Cleanup compiler and docbook warnings in a lot of fbdev devices. - Use the drmm_vram_helper in hisilicon. - Add support for BCM2711 DSI1 in vc4. - Add support for 8-bit delta RGB panels to ingenic. - Add documentation on how to test vkms. - Convert vc4 to atomic helpers. - Use degamma instead of gamma table in omap, to add support for CTM and color encoding/range properties. - Rework omap DSI code, and merge all omapdrm modules now that the last omap panel is now a drm panel. - More refactoring of omap dsi code. - Enable 10/12 bpc outputs in vc4. Signed-off-by: Daniel Vetter <[email protected]> From: Maarten Lankhorst <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-01-06drm/amdgpu: enable ras eeprom support for sienna cichlidJohn Clements1-1/+7
added I2C address and asic support flag Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-06drm/amdgpu: fix no bad_pages issue after umc ue injectionDennis Li1-4/+4
old code wrongly used the bad page status as the function return value, which cause amdgpu_ras_badpages_read always return failed. Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-06drm/amdgpu: fix potential memory leak during navi12 deinitializationJiawei Gu1-4/+14
Navi12 HDCP & DTM deinitialization needs continue to free bo if already created though initialized flag is not set. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Jiawei Gu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-06drm/amdgpu: fix a GPU hang issue when remove deviceDennis Li1-2/+2
When GFXOFF is enabled and GPU is idle, driver will fail to access some registers. Therefore change to disable power gating before all access registers with MMIO. Dmesg log is as following: amdgpu 0000:03:00.0: amdgpu: amdgpu: finishing device. amdgpu: cp queue pipe 4 queue 0 preemption failed amdgpu 0000:03:00.0: amdgpu: failed to write reg 2890 wait reg 28a2 amdgpu 0000:03:00.0: amdgpu: failed to write reg 1a6f4 wait reg 1a706 amdgpu 0000:03:00.0: amdgpu: failed to write reg 2890 wait reg 28a2 amdgpu 0000:03:00.0: amdgpu: failed to write reg 1a6f4 wait reg 1a706 Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-06drm/amdgpu: fix a memory protection fault when remove amdgpu deviceDennis Li1-4/+3
ASD and TA share the same firmware in SIENNA_CICHLID and only TA firmware is requested during boot, so only need release TA firmware when remove device. [ 83.877150] general protection fault, probably for non-canonical address 0x1269f97e6ed04095: 0000 [#1] SMP PTI [ 83.888076] CPU: 0 PID: 1312 Comm: modprobe Tainted: G W OE 5.9.0-rc5-deli-amd-vangogh-0.0.6.6-114-gdd99d5669a96-dirty #2 [ 83.901160] Hardware name: System manufacturer System Product Name/TUF Z370-PLUS GAMING II, BIOS 0411 09/21/2018 [ 83.912353] RIP: 0010:free_fw_priv+0xc/0x120 [ 83.917531] Code: e8 99 cd b0 ff b8 a1 ff ff ff eb 9f 4c 89 f7 e8 8a cd b0 ff b8 f4 ff ff ff eb 90 0f 1f 00 0f 1f 44 00 00 55 48 89 e5 41 54 53 <4c> 8b 67 18 48 89 fb 4c 89 e7 e8 45 94 41 00 b8 ff ff ff ff f0 0f [ 83.937576] RSP: 0018:ffffbc34c13a3ce0 EFLAGS: 00010206 [ 83.943699] RAX: ffffffffbb681850 RBX: ffffa047f117eb60 RCX: 0000000080800055 [ 83.951879] RDX: ffffbc34c1d5f000 RSI: 0000000080800055 RDI: 1269f97e6ed04095 [ 83.959955] RBP: ffffbc34c13a3cf0 R08: 0000000000000000 R09: 0000000000000001 [ 83.968107] R10: ffffbc34c13a3cc8 R11: 00000000ffffff00 R12: ffffa047d6b23378 [ 83.976166] R13: ffffa047d6b23338 R14: ffffa047d6b240c8 R15: 0000000000000000 [ 83.984295] FS: 00007f74f6712540(0000) GS:ffffa047fbe00000(0000) knlGS:0000000000000000 [ 83.993323] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 84.000056] CR2: 0000556a1cca4e18 CR3: 000000021faa8004 CR4: 00000000003706f0 [ 84.008128] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 84.016155] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 84.024174] Call Trace: [ 84.027514] release_firmware.part.11+0x4b/0x70 [ 84.033017] release_firmware+0x13/0x20 [ 84.037803] psp_sw_fini+0x77/0xb0 [amdgpu] [ 84.042857] amdgpu_device_fini+0x38c/0x5d0 [amdgpu] [ 84.048815] amdgpu_driver_unload_kms+0x43/0x70 [amdgpu] [ 84.055055] drm_dev_unregister+0x73/0xb0 [drm] [ 84.060499] drm_dev_unplug+0x28/0x30 [drm] [ 84.065598] amdgpu_dev_uninit+0x1b/0x40 [amdgpu] [ 84.071223] amdgpu_pci_remove+0x4e/0x70 [amdgpu] [ 84.076835] pci_device_remove+0x3e/0xc0 [ 84.081609] device_release_driver_internal+0xfb/0x1c0 [ 84.087558] driver_detach+0x4d/0xa0 [ 84.092041] bus_remove_driver+0x5f/0xe0 [ 84.096854] driver_unregister+0x2f/0x50 [ 84.101594] pci_unregister_driver+0x22/0xa0 [ 84.106806] amdgpu_exit+0x15/0x2b [amdgpu] Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-06drm/amdgpu: switched to cached noretry setting for vangoghHawking Zhang1-1/+1
global noretry setting is cached to gmc.noretry Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: Add check to prevent IH overflowDefang Bo3-39/+71
Similar to commit <b82175750131>("drm/amdgpu: fix IH overflow on Vega10 v2"). When an ring buffer overflow happens the appropriate bit is set in the WPTR register which is also written back to memory. But clearing the bit in the WPTR doesn't trigger another memory writeback. So what can happen is that we end up processing the buffer overflow over and over again because the bit is never cleared. Resulting in a random system lockup because of an infinite loop in an interrupt handler. Reviewed-by: Christian König <[email protected]> Signed-off-by: Defang Bo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: enable ras eeprom support for sienna cichlidJohn Clements1-1/+7
added I2C address and asic support flag Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: fix no bad_pages issue after umc ue injectionDennis Li1-4/+4
old code wrongly used the bad page status as the function return value, which cause amdgpu_ras_badpages_read always return failed. Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: fix potential memory leak during navi12 deinitializationJiawei Gu1-4/+14
Navi12 HDCP & DTM deinitialization needs continue to free bo if already created though initialized flag is not set. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Jiawei Gu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: take runtime pm reference when we attach a bufferAlex Deucher1-2/+14
And drop it when we detach. If the shared buffer is in vram, we need to make sure we don't put the device into runtime suspend. Acked-by: Shashank Sharma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: Fix macro name _AMDGPU_TRACE_H_ in preprocessor if conditionChenyang Li1-1/+1
Add an underscore in amdgpu_trace.h line 24 "_AMDGPU_TRACE_H". Fixes: d38ceaf99ed0 ("drm/amdgpu: add core driver (v4)") Reviewed-by: Guchun Chen <[email protected]> Reviewed-by: Paul Menzel <[email protected]> Signed-off-by: Chenyang Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: do optimization for psp command submitpengzhou1-2/+2
In the psp command submit logic, the function msleep(1) delayed too long, Changing it to usleep_range(10, 100) to have a better performance. Signed-off-by: Peng Ju Zhou <[email protected]> Reviewed-by: Emily.Deng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: remove redundant include of navi10_enumLikun Gao4-4/+0
Remove unnecessary include of navi10_enum header file. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: remove redundant logic related HDPLikun Gao12-77/+0
Remove hdp_flush function from amdgpu_nbio struct as it have been unified into hdp struct. Remove the include about hdp register which was not used. V2: Remove hdp golden setting which is unnecessary. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: switch hdp callback functions for hdp v5Likun Gao5-174/+13
Switch to use the HDP functions which unified on hdp structure instead of the scattered hdp callback functions. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: switch hdp callback functions for hdp v4Likun Gao4-106/+16
Switch to use the HDP functions which unified on hdp structure instead of the scattered hdp callback functions. V2: clean up hdp reset ras error count function. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: add hdp version 5 functionsLikun Gao2-0/+243
Unify hdp related function into hdp structure for hdp version 5. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: add hdp version 4 functionsLikun Gao3-0/+178
Unify hdp related function into hdp structure for hdp version 4. V2: Add function to remap hdp registers for nbio version 6.1 Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: add amdgpu_hdp structureHawking Zhang2-0/+44
amdgpu_hdp hold all the callbacks for hdp Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: fix potential NULL pointer when check_atom_bios() failsJiawei Gu1-2/+3
Asic funcs pointer needs being checked whether is NULL. Because when check_atom_bios() fails in req_init_data handshake, asic funcs pointer is not initialized yet. Signed-off-by: Jiawei Gu <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: use GTT for uvd_get_create/destory_msgChen Li1-2/+2
On modern gpus, GTT (system memory) works as well here, and this may also be a workaround for platforms which cannot map vram correctly. Signed-off-by: chenli <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: fix a GPU hang issue when remove deviceDennis Li1-2/+2
When GFXOFF is enabled and GPU is idle, driver will fail to access some registers. Therefore change to disable power gating before all access registers with MMIO. Dmesg log is as following: amdgpu 0000:03:00.0: amdgpu: amdgpu: finishing device. amdgpu: cp queue pipe 4 queue 0 preemption failed amdgpu 0000:03:00.0: amdgpu: failed to write reg 2890 wait reg 28a2 amdgpu 0000:03:00.0: amdgpu: failed to write reg 1a6f4 wait reg 1a706 amdgpu 0000:03:00.0: amdgpu: failed to write reg 2890 wait reg 28a2 amdgpu 0000:03:00.0: amdgpu: failed to write reg 1a6f4 wait reg 1a706 Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: fix a memory protection fault when remove amdgpu deviceDennis Li1-4/+3
ASD and TA share the same firmware in SIENNA_CICHLID and only TA firmware is requested during boot, so only need release TA firmware when remove device. [ 83.877150] general protection fault, probably for non-canonical address 0x1269f97e6ed04095: 0000 [#1] SMP PTI [ 83.888076] CPU: 0 PID: 1312 Comm: modprobe Tainted: G W OE 5.9.0-rc5-deli-amd-vangogh-0.0.6.6-114-gdd99d5669a96-dirty #2 [ 83.901160] Hardware name: System manufacturer System Product Name/TUF Z370-PLUS GAMING II, BIOS 0411 09/21/2018 [ 83.912353] RIP: 0010:free_fw_priv+0xc/0x120 [ 83.917531] Code: e8 99 cd b0 ff b8 a1 ff ff ff eb 9f 4c 89 f7 e8 8a cd b0 ff b8 f4 ff ff ff eb 90 0f 1f 00 0f 1f 44 00 00 55 48 89 e5 41 54 53 <4c> 8b 67 18 48 89 fb 4c 89 e7 e8 45 94 41 00 b8 ff ff ff ff f0 0f [ 83.937576] RSP: 0018:ffffbc34c13a3ce0 EFLAGS: 00010206 [ 83.943699] RAX: ffffffffbb681850 RBX: ffffa047f117eb60 RCX: 0000000080800055 [ 83.951879] RDX: ffffbc34c1d5f000 RSI: 0000000080800055 RDI: 1269f97e6ed04095 [ 83.959955] RBP: ffffbc34c13a3cf0 R08: 0000000000000000 R09: 0000000000000001 [ 83.968107] R10: ffffbc34c13a3cc8 R11: 00000000ffffff00 R12: ffffa047d6b23378 [ 83.976166] R13: ffffa047d6b23338 R14: ffffa047d6b240c8 R15: 0000000000000000 [ 83.984295] FS: 00007f74f6712540(0000) GS:ffffa047fbe00000(0000) knlGS:0000000000000000 [ 83.993323] CS: 0010 DS: 0000 ES: 0000 CR0: 0000000080050033 [ 84.000056] CR2: 0000556a1cca4e18 CR3: 000000021faa8004 CR4: 00000000003706f0 [ 84.008128] DR0: 0000000000000000 DR1: 0000000000000000 DR2: 0000000000000000 [ 84.016155] DR3: 0000000000000000 DR6: 00000000fffe0ff0 DR7: 0000000000000400 [ 84.024174] Call Trace: [ 84.027514] release_firmware.part.11+0x4b/0x70 [ 84.033017] release_firmware+0x13/0x20 [ 84.037803] psp_sw_fini+0x77/0xb0 [amdgpu] [ 84.042857] amdgpu_device_fini+0x38c/0x5d0 [amdgpu] [ 84.048815] amdgpu_driver_unload_kms+0x43/0x70 [amdgpu] [ 84.055055] drm_dev_unregister+0x73/0xb0 [drm] [ 84.060499] drm_dev_unplug+0x28/0x30 [drm] [ 84.065598] amdgpu_dev_uninit+0x1b/0x40 [amdgpu] [ 84.071223] amdgpu_pci_remove+0x4e/0x70 [amdgpu] [ 84.076835] pci_device_remove+0x3e/0xc0 [ 84.081609] device_release_driver_internal+0xfb/0x1c0 [ 84.087558] driver_detach+0x4d/0xa0 [ 84.092041] bus_remove_driver+0x5f/0xe0 [ 84.096854] driver_unregister+0x2f/0x50 [ 84.101594] pci_unregister_driver+0x22/0xa0 [ 84.106806] amdgpu_exit+0x15/0x2b [amdgpu] Signed-off-by: Dennis Li <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: switched to cached noretry setting for vangoghHawking Zhang1-1/+1
global noretry setting is cached to gmc.noretry Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-01-05drm/amdgpu: remove unnecessary asic check for sdma5.2Jiansong Chen1-26/+5
For sdma5.2, all sdma instances will share the same fw, remove unnecessary asic check to be more generic. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-24Merge tag 'amd-drm-fixes-5.11-2020-12-23' of ↵Dave Airlie5-21/+27
git://people.freedesktop.org/~agd5f/linux into drm-next amd-drm-fixes-5.11-2020-12-23: amdgpu: - Vangogh SMU fixes - Arcturus gfx9 fixes - Misc display fixes - Sienna Cichlid SMU update - Fix S3 display memory leak - Fix regression caused by DP sub-connector support amdkfd: - Properly require pcie atomics for gfx10 Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2020-12-23drm/amdgpu: drop psp ih programming for sriov guest on naviHawking Zhang1-16/+2
the psp access ih path is not needed in navi Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Reviewed-by: Jane Jian <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: fix handling of irq domains on soc15 and newer GPUsAlex Deucher1-1/+2
We need to take into account the client id otherwise we'll end up sending generic events for any src id that is registered. We only support irq domains on pre-soc15 parts so client is always legacy. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: de-initialize software ih ringHawking Zhang3-0/+3
tear down software ih ring and its state. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: set ih soft ring enabled flag for vega and naviHawking Zhang2-0/+6
software ih ring is enabled in vega10 and navi ih block by default. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: enable software ih ring for vega20 ih blockHawking Zhang1-0/+7
software ih ring will be used as a workaround in case hardware ih ring 1 and ring 2 don't work Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: don't create ih ring 1 and ring 2 for APUHawking Zhang1-11/+12
APUs don't support ih ring 1 and ring 2. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: drop ih reroute function from psp v11Hawking Zhang1-36/+0
For all the ASICs that integrate psp v11, vega20 doesn't support ih reroute. arcturus and later will allow kernel driver to program ih_cfg_index/data through mmio directly. navi1x and onwards will only support grb_ih_set command in sriov configuration. psp_v11_0_reroute_ih is not needed any more. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: drop IH_CHICKEN programming from vega10 ih blockHawking Zhang1-3/+1
except for RENOIR, it is not correct to have IH_CHICKEN programming in vega10 ih block. Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: correct ih_chicken programming for vega10/vega20 ih blocksHawking Zhang2-6/+0
IH_CHICKEN.MC_SPACE_FBPA_ENABLE field is only valid when IH_RB_CNTL.MC_SPACE is programed to 0x3, frame buffer physical address. For both bus address and gpu virtual address, don't program MC_SPACE_FBPA_ENABLE field Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: retire the vega20 code path from navi10 ih blockHawking Zhang1-38/+2
already switched to vega20 ih block for vega20 and arcturus. no need to add vega20 support in navi10 ih block Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: switch to vega20 ih block for vega20/arcturusHawking Zhang1-4/+5
replace navi10 ih block with vega20 ih block for vega20 and arcturus Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: reroute vmc/utcl2 interrupts to ih ring 1 for arcturusHawking Zhang1-0/+34
in case page faults overwhlem the interrupt handlers and the driver lost the valuable interrupt information Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: create vega20 ih blocksHawking Zhang3-0/+692
vega20 ih blocks will be used for vega20/arcturus Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: switch to common decode iv helperHawking Zhang2-92/+2
The iv format is the same for all the soc15 adpater and onwards and can share a common function to decode iv. Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: add a helper function to decode ivHawking Zhang2-1/+46
since from soc15, all the chips share the same iv format. create a common helper to decode iv Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: use cached ih rb control reg offsets for navi10Hawking Zhang1-38/+14
all the ih rb control register offsets are cached at the beginning of navi10 ih_sw_init. Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: switch to ih_enable_ring for navi10Hawking Zhang1-90/+12
use navi10_ih_enable_ring to enable all the available ring buffers for navi1x and onwards Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: switch to ih_toggle_interrupts for navi10Hawking Zhang1-133/+33
replace ih_enable_interrupts and ih_disable_interrupts with ih_toggle_interrupts Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: switch to ih_init_register_offset for navi10Hawking Zhang1-0/+3
Initialize ih control registers offset through helper function navi10_ih_init_register_offset. Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: add helper to toggle ih ring interrupts for navi10Hawking Zhang1-0/+45
navi10_ih_toggle_ring_interrupts will be used to enable/disable an ih ring interrupts for navi1x and onwards Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-12-23drm/amdgpu: add helper to enable an ih ring for navi10Hawking Zhang1-0/+52
navi10_ih_enable_ring will be used to enable an ih ring for navi1x and onwards Signed-off-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Acked-by: Felix Kuehling <[email protected]> Reviewed-by: Dennis Li <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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