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path: root/drivers/gpu/drm/amd/amdgpu
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2016-10-25drm/amdgpu: rework IP block registration (v2)Alex Deucher69-1935/+924
This makes it easier to replace specific IP blocks on asics for handling virtual_dce, DAL, etc. and for building IP lists for hw or tables. This also stored the status information in the same structure. v2: split out spelling fix into a separate patch add a function to add IPs to the list Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu/powerplay: fix spelling in amdgpu_powerplay.hAlex Deucher1-3/+3
and update a comment as well. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu/virtual_dce: move define into source fileAlex Deucher2-1/+3
It's not used outside the file. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: enable virtual dce on SIAlex Deucher1-4/+136
Add the proper IP module when requested. Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: fill in vce clock info ioctl query (v2)Alex Deucher1-0/+18
Returns the vce clock table for the user mode driver. The user mode driver can fill this data into vce clock data packet for optimal VCE DPM. v2: update to the new API Reviewed-by: Rex Zhu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu/dpm: add an implementation for get_vce_clock_state (v2)Alex Deucher5-0/+15
Used by the non-powerplay dpm code. v2: update to the new API Reviewed-by: Rex Zhu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu/dpm: add new callback to fetch vce clock state (v2)Alex Deucher1-0/+5
Will be used by the new info ioctl query. v2: fetch a single state per request Reviewed-by: Rex Zhu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: save number of vce states in dpm struct.Rex Zhu5-6/+8
Reviewed-by: Christian König <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: use same vce state definition in dpm and powerplayRex Zhu6-30/+8
Reviewed-by: Christian König <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: move dpm related definitions to amdgpu_dpm.hAlex Deucher2-448/+448
No intended functional change. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: move align_mask and nop into ring funcs as well (v2)Christian König14-43/+62
They are constant as well. v2: update uvd and vce phys ring structures as well Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: move the ring type into the funcs structure (v2)Christian König16-43/+52
It's constant, so it doesn't make to much sense to keep it with the variable data. v2: update vce and uvd phys mode ring structures as well Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: move IB and frame size directly into the engine descriptionChristian König16-288/+117
I should have suggested that on the initial patchset. This saves us a few CPU cycles during CS and a bunch of loc. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: remove explicit NULL init for parse_csChristian König9-12/+0
sed -i "/\.parse_cs = NULL,/d" drivers/gpu/drm/amd/amdgpu/*.c That's just a leftover from radeon. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: remove 128 NOP hack from vm_flush v2Christian König1-5/+1
With the padding raised to 256 DW that shouldn't be needed any more. v2: reduce estimation as well Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: remove ring type check for conditional executionChristian König1-1/+1
If a ring doesn't support that it shouldn't implement the function. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: pad gfx and compute rings to 256 dwChristian König3-6/+6
The same as on windows to avoid further problems with CE/DE command submission overlaps. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: clarify why we evict vram twice on suspendAlex Deucher1-1/+4
Update the comment to explain why we do this. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: used cached gca values for vi_read_register (v2)Alex Deucher1-20/+97
Using the cached values has less latency for bare metal and SR-IOV, and prevents reading back bogus values if the engine is powergated. v2: fix typo in tile idx calculation Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu/gfx8: use cached raster config values in csb setupAlex Deucher1-28/+2
Simplify the code and properly set the csb for harvest values. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu/gfx8: cache rb config valuesAlex Deucher1-0/+15
Needed when for SR-IOV and when PG is enabled. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: add additional cached gca config variablesAlex Deucher1-0/+12
We need to cache some additional values to handle SR-IOV and PG. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: use amdgpu_vm_get_pd_bo in the GEM codeChristian König1-4/+3
Instead of messing with the PD directly. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: move VM defines into amdgpu_vm.hChristian König2-169/+206
Only cleanup, no intended functional change. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: move fence and ring defines into amdgpu_ring.hChristian König2-146/+185
Only cleanup, no intended functional change. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: move sync handling into a separate headerChristian König2-21/+57
Only cleanup, no intended functional change. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: stop using a bo list entry for the VM PTsChristian König2-22/+16
Saves us a bit of memory. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: move PT validation back into VM code v2Christian König4-35/+60
Saves a bunch of CPU cycles when swapping things back in and allows us to split the VM headers into a separate file. v2: rename parameters Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: remove adev pointer from struct amdgpu_bo v2Christian König9-62/+65
It's completely pointless to have two pointers to the device in the same structure. v2: rename function to amdgpu_ttm_adev, fix typos Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amd/amdgpu: Enable UVD PG on TongaTom St Denis1-1/+1
Tested by reading tile/clk bits during load/idle. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: update the shadow PD together with the real one v2Christian König2-66/+69
Far less CPU cycles needed for this approach. v2: fix typo Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu:wptr poll address of gfx8 is neededFrank Min1-1/+4
for GFX8, gfx ring's wptr_addr is needed by SRIOV & CP for polling. Signed-off-by: Frank Min <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu:properly fix some JumpTable issuesMonk Liu3-6/+52
we found some MEC ucode leads to IB test fail or even ring test fail if Jump Table of it is not start in FW bo with page aligned address, fixed by always make JT address page aligned. we don't need to patch JT2 for MEC2, because for VI, MEC2 is a copy of MEC1, thus when converting fw_type for MEC_JT2 we just return MEC1,hw can use the same JT for both MEC1 & MEC2. above two change fixed some ring/ib test failure issue for some version of MEC ucode. Signed-off-by: Frank Min <[email protected]> Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu:add MEC_STORAGE ucode id for sriovMonk Liu4-0/+15
for sriov, SMC need MEC_STORAGE reserved in fw bo. Signed-off-by: Monk Liu <[email protected]> Signed-off-by: Frank Min <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu:add callback in cgs for sriov detectFrank Min1-0/+7
Signed-off-by: Frank Min <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu:fw bo should be in VRAM for SRIOVFrank Min1-2/+4
for GTT memory SMC can only access it within PF space, which is not used for SRIOV case, thus for SRIOV case, we let SMC use FB space for ucode bo. Signed-off-by: Frank Min <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu:keep bo pinned in prefered domainFrank Min1-1/+1
Signed-off-by: Frank Min <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu:use smc_index_11 for VIMonk Liu1-8/+8
for VI smc, index_0 to index_8 are all not safe, they may used by BIOS/FW, and index_11 is reserved only for driver. Signed-off-by: Monk Liu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu:add one more fiji device idFrank Min1-0/+1
Signed-off-by: Frank Min <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amd/amdgpu: bump version for memory query infoJunwei Zhang1-1/+2
Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amd/amdgpu: unify memory query info interfaceJunwei Zhang1-26/+28
Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Marek Olšák <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: add VRAM manager v2Christian König7-2/+237
Split VRAM allocations into 4MB blocks. v2: fix typo in comment, some suggested cleanups v3: document how to disable the feature, fix rebase issue Signed-off-by: Christian König <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Tested-by: Mike Lothian <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: enable amdgpu_move_blit to handle multiple MM nodes v2Christian König1-33/+85
This allows us to move scattered buffers around. v2: fix a couple of typos, handle scattered to scattered moves as well. Signed-off-by: Christian König <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Tested-by: Mike Lothian <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: handle multiple MM nodes in the VMs v2Christian König1-35/+46
This allows us to map scattered VRAM BOs to the VMs. v2: fix offset handling, use pfn instead of offset, fix PAGE_SIZE != AMDGPU_GPU_PAGE_SIZE case Signed-off-by: Christian König <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Tested-by: Mike Lothian <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: set at least the node size in the gtt managerChristian König1-0/+1
Otherwise the new VM code becomes confused. Signed-off-by: Christian König <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Tested-by: Mike Lothian <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: use explicit limit for VRAM_CONTIGUOUSChristian König1-2/+7
Split VRAM won't have a valid offset, so just set an explicit limit when the flag is given to trigger reallocation if necessary. Signed-off-by: Christian König <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Tested-by: Mike Lothian <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu: add AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS flag v3Christian König12-18/+51
Add a flag noting that a BO must be created using linear VRAM and set this flag on all in kernel users where appropriate. Hopefully I haven't missed anything. v2: add it in a few more places, fix CPU mapping. v3: rename to VRAM_CONTIGUOUS, fix typo in CS code. Signed-off-by: Christian König <[email protected]> Reviewed-by: Edward O'Callaghan <[email protected]> Tested-by: Mike Lothian <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amd/amdgpu: add info about vram and gtt max allocation sizeJunwei Zhang1-0/+18
Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amd/amdgpu: add info about vram and gtt total sizeJunwei Zhang1-0/+10
Signed-off-by: Junwei Zhang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2016-10-25drm/amdgpu/dce6: don't enable HPD Rx interruptsAlex Deucher1-2/+2
Not used currently. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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