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2019-07-31drm/amdgpu: drop drmP.h in gfx_v10_0.cAlex Deucher1-3/+7
And fix the fallout. Acked-by: Sam Ravnborg <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-31drm/amdgpu: drop drmP.h from amdgpu_amdkfd_gfx_v10.cAlex Deucher1-1/+0
Unused. Acked-by: Sam Ravnborg <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-31drm/amdgpu: drop drmP.h in amdgpu_amdkfd_arcturus.cAlex Deucher1-1/+0
Unused. Acked-by: Sam Ravnborg <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-31drm/amdgpu: Provide ddc symlink in connector sysfs directoryAndrzej Pietrasiewicz1-26/+70
Use the ddc pointer provided by the generic connector. Signed-off-by: Andrzej Pietrasiewicz <[email protected]> Acked-by: Alex Deucher <[email protected]> Acked-by: Sam Ravnborg <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Neil Armstrong <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/7fee0fa0d0f77af6595d283d5f3ae5d551475821.1564161140.git.andrzej.p@collabora.com
2019-07-31drm/amdgpu: Fill out gem_object->resvDaniel Vetter4-18/+3
That way we can ditch our gem_prime_res_obj implementation. Since ttm absolutely needs the right reservation object all the boilerplate is already there and we just have to wire it up correctly. Note that gem/prime doesn't care when we do this, as long as we do it before the bo is registered and someone can call the handle2fd ioctl on it. Aside: ttm_buffer_object.ttm_resv could probably be ditched in favour of always passing a non-NULL resv to ttm_bo_init(). At least for gem drivers that would avoid having two of these, on in ttm_buffer_object and the other in drm_gem_object, one just there for confusion. Acked-by: Gerd Hoffmann <[email protected]> Cc: Gerd Hoffmann <[email protected]> Reviewed-by: Emil Velikov <[email protected]> Signed-off-by: Daniel Vetter <[email protected]> Cc: Alex Deucher <[email protected]> Cc: "Christian König" <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: "Michel Dänzer" <[email protected]> Cc: Chris Wilson <[email protected]> Cc: Huang Rui <[email protected]> Cc: Felix Kuehling <[email protected]> Cc: Andrey Grodzovsky <[email protected]> Cc: Evan Quan <[email protected]> Cc: Sonny Jiang <[email protected]> Cc: Amber Lin <[email protected]> Cc: "Michał Mirosław" <[email protected]> Cc: Junwei Zhang <[email protected]> Cc: Thomas Zimmermann <[email protected]> Cc: Samuel Li <[email protected]> Reviewed-by: Christian König <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-31drm/amd/powerplay: correct UVD/VCE/VCN power status retrievalEvan Quan1-20/+36
VCN should be used for Vega20 later ASICs while UVD and VCE are for previous ASICs. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-31drm/amdgpu: fix a potential information leaking bugWang Xiayang1-1/+1
Coccinelle reports a path that the array "data" is never initialized. The path skips the checks in the conditional branches when either of callback functions, read_wave_vgprs and read_wave_sgprs, is not registered. Later, the uninitialized "data" array is read in the while-loop below and passed to put_user(). Fix the path by allocating the array with kcalloc(). The patch is simplier than adding a fall-back branch that explicitly calls memset(data, 0, ...). Also it does not need the multiplication 1024*sizeof(*data) as the size parameter for memset() though there is no risk of integer overflow. Signed-off-by: Wang Xiayang <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-31drm/amdgpu: fix error handling in amdgpu_cs_process_fence_depChristian König1-14/+12
We always need to drop the ctx reference and should check for errors first and then dereference the fence pointer. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-31drm/amd/powerplay: fix null pointer dereference around dpm state relatesEvan Quan1-5/+13
DPM state relates are not supported on the new SW SMU ASICs. But still it's not OK to trigger null pointer dereference on accessing them. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdkfd: Fix byte align on VegaMKent Russell1-1/+2
This was missed during the addition of VegaM support Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Kent Russell <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu: correct irq type used for sdma eccHawking Zhang1-2/+2
we should pass irq type, instead of irq client id, to irq_get/put interface Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Feifei Xu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amd/powerplay: correct UVD/VCE/VCN power status retrievalEvan Quan1-20/+36
VCN should be used for Vega20 later ASICs while UVD and VCE are for previous ASICs. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu: update more sdma instances irq supportLe Ma1-50/+27
Update for sdma ras ecc_irq and other minors. Signed-off-by: Le Ma <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu: correct VCN powergate routine for acturusEvan Quan1-2/+2
Arcturus VCN should powergate in the way as Navi. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Le Ma <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amd/powerplay: enable arcturus powerplayEvan Quan1-0/+1
Arcturus powerplay is ready to use. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amd/powerplay: initialize arcturus MP1 and THM base addressEvan Quan1-0/+2
Initialize base address for those IPs which are used in powerplay. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu: fix a potential information leaking bugWang Xiayang1-1/+1
Coccinelle reports a path that the array "data" is never initialized. The path skips the checks in the conditional branches when either of callback functions, read_wave_vgprs and read_wave_sgprs, is not registered. Later, the uninitialized "data" array is read in the while-loop below and passed to put_user(). Fix the path by allocating the array with kcalloc(). The patch is simplier than adding a fall-back branch that explicitly calls memset(data, 0, ...). Also it does not need the multiplication 1024*sizeof(*data) as the size parameter for memset() though there is no risk of integer overflow. Signed-off-by: Wang Xiayang <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu: fix error handling in amdgpu_cs_process_fence_depChristian König1-14/+12
We always need to drop the ctx reference and should check for errors first and then dereference the fence pointer. Signed-off-by: Christian König <[email protected]> Reviewed-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amd/amdgpu/vcn_v2_0: Move VCN 2.0 specific dec ring test to vcn_v2_0Thong Thai1-1/+31
VCN 2.0 firmware now requires a packet start command to be sent before any other decode ring buffer command. Signed-off-by: Thong Thai <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu/gfx10: update golden settings for navi14Alex Deucher1-1/+0
Updated settings for hw team. Reviewed-by: Xiaojie Yuan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amd/powerplay: implment sysfs feature status function in smuKevin Wang1-12/+12
1. Unified feature enable status format in sysfs 2. Rename ppfeature to pp_features to adapt other pp sysfs node name 3. this function support all asic, not asic related function. Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Acked-by: Rui Huang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu: Default disable GDS for compute+gfxJoseph Greathouse4-28/+69
Units in the GDS block default to allowing all VMIDs access to all entries. Disable shader access to the GDS, GWS, and OA blocks from all compute and gfx VMIDs by default. For compute, HWS firmware will set up the access bits for the appropriate VMID when a compute queue requires access to these blocks. The driver will handle enabling access on-demand for graphics VMIDs. Leaving VMID0 with full access because otherwise HWS cannot save or restore values during task switch. v2: Fixed code and comment styling. Signed-off-by: Joseph Greathouse <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amd/amdgpu/vcn_v2_0: Mark RB commands as KMD commandsThong Thai2-6/+7
Sets the CMD_SOURCE bit for VCN 2.0 Decoder Ring Buffer commands. This bit was previously set by the RBC HW on older firmware. Newer firmware uses a SW RBC and this bit has to be set by the driver. Signed-off-by: Thong Thai <[email protected]> Reviewed-by: Leo Liu <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu: Fix amdgpu_display_supported_domains logic.Andrey Grodzovsky5-14/+21
Add restriction to dissallow GTT domain if the relevant BO doesn't have USWC flag set to avoid the APU hang scenario. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu: put the SMC into the proper state on reset/unloadAlex Deucher3-0/+30
When doing a GPU reset or unloading the driver, we need to put the SMU into the apprpriate state for the re-init after the reset or unload to reliably work. I don't think this is necessary for BACO because the SMU actually controls the BACO state to it needs to be active. For suspend (S3), the asic is put into D3 so the SMU would be powered down so I don't think we need to put the SMU into any special state. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu: add reset_method asic callback for naviAlex Deucher1-1/+14
Navi uses either mode1 or baco depending on various conditions. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu: add reset_method asic callback for soc15Alex Deucher1-2/+15
APUs only support mode2 reset. dGPUs use either mode1 or baco depending on various conditions. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu: add reset_method asic callback for viAlex Deucher1-0/+7
VI always uses the legacy pci based reset. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu: add reset_method asic callback for cikAlex Deucher1-0/+7
CIK always uses the legacy pci based reset. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu: add reset_method asic callback for siAlex Deucher1-0/+7
SI always uses the legacy pci based reset. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu: add an asic callback to determine the reset methodAlex Deucher1-0/+10
Sometimes the driver may have to behave differently depending on the method we are using to reset the GPU. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amd/powerplay: fix null pointer dereference around dpm state relatesEvan Quan1-5/+13
DPM state relates are not supported on the new SW SMU ASICs. But still it's not OK to trigger null pointer dereference on accessing them. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amd/powerplay: minor fixes around SW SMU power and fan settingEvan Quan1-12/+10
Add checking for possible invalid input and null pointer. And drop redundant code. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amd/display: enable S/G for RAVEN chipShirish S1-1/+1
enables gpu_vm_support in dm and adds AMDGPU_GEM_DOMAIN_GTT as supported domain v2: Move BO placement logic into amdgpu_display_supported_domains v3: Use amdgpu_bo_validate_uswc in amdgpu_display_supported_domains. v4: amdgpu_bo_validate_uswc moved to sepperate patch. Signed-off-by: Shirish S <[email protected]> Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Nicholas Kazlauskas <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu: Add check for USWC support for amdgpu_display_supported_domainsAndrey Grodzovsky1-1/+8
This verifies we don't add GTT as allowed domain for APUs when USWC is disabled. Signed-off-by: Andrey Grodzovsky <[email protected]> Acked-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu: Create helper to clear AMDGPU_GEM_CREATE_CPU_GTT_USWCAndrey Grodzovsky2-26/+37
Move the logic to clear AMDGPU_GEM_CREATE_CPU_GTT_USWC in amdgpu_bo_do_create into standalone helper so it can be reused in other functions. v4: Switch to return bool. v5: Fix typos. Signed-off-by: Andrey Grodzovsky <[email protected]> Acked-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu: Fix hard hang for S/G display BOs.Andrey Grodzovsky2-5/+5
HW requires for caching to be unset for scanout BO mappings when the BO placement is in GTT memory. Usually the flag to unset is passed from user mode but for FB mode this was missing. v2: Keep all BO placement logic in amdgpu_display_supported_domains Suggested-by: Alex Deucher <[email protected]> Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Tested-by: Shirish S <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu: adding xgmi error monitoringJonathan Kim1-2/+36
monitor xgmi errors via mc pie status through fica registers. Signed-off-by: Jonathan Kim <[email protected]> Reviewed-by: Kent Russell <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu: add perfmon and fica atomics for dfJonathan Kim2-77/+128
adding perfmon and fica atomic operations to adhere to data fabrics finite state machine requirements for indirect register access. Signed-off-by: Jonathan Kim <[email protected]> Reviewed-by: Kent Russell <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu/gmc10: fix pte mytpe field error for navi14tiancyin2-2/+2
navi14 share same PTE format with navi10. Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: tiancyin <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu: use VCN firmware offset for cache windowJames Zhu1-3/+0
Since we are using the signed FW now, and also using PSP firmware loading, but it's still potential to break driver when loading FW directly instead of PSP, so we should add offset. Signed-off-by: James Zhu <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amd/powerplay: some cosmetic fixesEvan Quan1-17/+16
Drop redundant check, duplicate check, duplicate setting and fix the return value. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdgpu: Use dev_get_drvdata where possibleChuhong Yuan1-14/+7
Instead of using to_pci_dev + pci_get_drvdata, use dev_get_drvdata to make code simpler. Signed-off-by: Chuhong Yuan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-30drm/amdkfd: Fix byte align on VegaMKent Russell1-1/+2
This was missed during the addition of VegaM support Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Kent Russell <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2019-07-27Merge tag 'Wimplicit-fallthrough-5.3-rc2' of ↵Linus Torvalds1-0/+1
git://git.kernel.org/pub/scm/linux/kernel/git/gustavoars/linux Pull Wimplicit-fallthrough enablement from Gustavo A. R. Silva: "This marks switch cases where we are expecting to fall through, and globally enables the -Wimplicit-fallthrough option in the main Makefile. Finally, some missing-break fixes that have been tagged for -stable: - drm/amdkfd: Fix missing break in switch statement - drm/amdgpu/gfx10: Fix missing break in switch statement With these changes, we completely get rid of all the fall-through warnings in the kernel" * tag 'Wimplicit-fallthrough-5.3-rc2' of git://git.kernel.org/pub/scm/linux/kernel/git/gustavoars/linux: Makefile: Globally enable fall-through warning drm/i915: Mark expected switch fall-throughs drm/amd/display: Mark expected switch fall-throughs drm/amdkfd/kfd_mqd_manager_v10: Avoid fall-through warning drm/amdgpu/gfx10: Fix missing break in switch statement drm/amdkfd: Fix missing break in switch statement perf/x86/intel: Mark expected switch fall-throughs mtd: onenand_base: Mark expected switch fall-through afs: fsclient: Mark expected switch fall-throughs afs: yfsclient: Mark expected switch fall-throughs can: mark expected switch fall-throughs firewire: mark expected switch fall-throughs
2019-07-26mm/hmm: replace the block argument to hmm_range_fault with a flags valueChristoph Hellwig1-1/+1
This allows easier expansion to other flags, and also makes the callers a little easier to read. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Christoph Hellwig <[email protected]> Signed-off-by: Ralph Campbell <[email protected]> Reviewed-by: Jason Gunthorpe <[email protected]> Signed-off-by: Jason Gunthorpe <[email protected]>
2019-07-26mm/hmm: replace hmm_update with mmu_notifier_rangeRalph Campbell1-6/+8
The hmm_mirror_ops callback function sync_cpu_device_pagetables() passes a struct hmm_update which is a simplified version of struct mmu_notifier_range. This is unnecessary so replace hmm_update with mmu_notifier_range directly. Link: https://lore.kernel.org/r/[email protected] Signed-off-by: Ralph Campbell <[email protected]> Reviewed: Christoph Hellwig <[email protected]> Reviewed-by: Jason Gunthorpe <[email protected]> [jgg: white space tuning] Signed-off-by: Jason Gunthorpe <[email protected]>
2019-07-26Merge tag 'drm-fixes-5.3-2019-07-24' of ↵Dave Airlie8-13/+51
git://people.freedesktop.org/~agd5f/linux into drm-fixes drm-fixes-5.3-2019-07-24: amdgpu: - RAS fixes for vega20 - Navi VCN fix - DC audio fixes - DC DSC fixes - DC dongle fixes - DC clk mgr fixes - Fix DDC lines on some RV2 boards - GDS fixes for compute - Navi SMU fixes ttm: - Use the same attributes when freeing d_page->vaddr Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2019-07-25drm/amdgpu/gfx10: Fix missing break in switch statementGustavo A. R. Silva1-0/+1
Add missing break statement in order to prevent the code from falling through to case AMDGPU_IRQ_STATE_ENABLE. This bug was found thanks to the ongoing efforts to enable -Wimplicit-fallthrough. Fixes: a644d85a5cd4 ("drm/amdgpu: add gfx v10 implementation (v10)") Cc: [email protected] Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Gustavo A. R. Silva <[email protected]>
2019-07-22drm/amdgpu/smu: move fan rpm query into the asic specific codeAlex Deucher1-2/+2
On vega20, there is an SMU message to query it. On navi, it's fetched from the metrics table. Reviewed-by: Evan Quan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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