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2018-02-19Revert "drm/amdgpu/gfx8: Fix compute ring failure after resetting"Andrey Grodzovsky1-7/+3
This reverts commit 75737cb4eb78c7f185e4700b4aa20cf7a3381aca. Fixes compute rings test failure on bare metal during full GPU reset. RCA: the ring buffer has to be filled with valid packets (such as NOPs) first before submitting MAP_QUEUEs packet into KIQ. Once a compute engine is mapped, it will immediately execute the ring buffer if the RTPR is not equal to the WTPR from the MQD. It could lead to engine hang if the ring buffer filled with random data. Signed-off-by: Andrey Grodzovsky <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: move waiting for VM flush into gmc_v9_0_emit_flush_gpu_tlbChristian König7-60/+33
Keep that at a common place instead of spread over all engines. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: implement vcn_v1_0_(dec|enc)_ring_emit_reg_wait v2Christian König1-17/+25
Add emit_reg_wait implementation for VCN v1. v2: cleanup the existing code as well Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: implement vce_v4_0_emit_reg_wait v2Christian König1-8/+14
Add emit_reg_wait implementation for VCE v4. v2: call new function directly from existing code Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: implement uvd_v7_0_(enc_|)ring_emit_reg_wait v2Christian König1-16/+24
Add emit_reg_wait implementation for UVD v7. v2: call new function directly from the existing code Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: implement sdma_v4_0_ring_emit_reg_waitChristian König1-0/+15
Add emit_reg_wait implementation for SDMA v4. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: implement gfx_v9_0_ring_emit_reg_waitChristian König1-0/+9
Implement emit_reg_wait for gfx v9. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: add new emit_reg_wait callbackChristian König2-0/+3
Allows us to wait for a register value/mask on a ring. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: fix DW estimation on VIChristian König2-2/+4
Forgot to update that during recent changes. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/pp: Fix sysfs pp_dpm_pcie bug on CI/VIRex Zhu1-7/+10
when echo "01">pp_dpm_pcie the pcie dpm will fix in highest link speed. But user should expect auto speed between level 0 and level1 Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/pp: Refine pp_dpm_force_clock_level functionsRex Zhu1-3/+1
Only when user set manual performance mode, driver enable pp_dpm_force_clock_level. so check the mode in pp_dpm_force_clock_level, and delete the same logic in callback functions. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/pp: Delete debug info when set power_profile_modeRex Zhu1-1/+0
Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: limit the VM address space with older VCE FW versionsChristian König2-0/+7
Older VCE FW versions are buggy and can't work with 48bit address spaces. RFC: Should we limit the address space or just reject loading the older VCE firmware? Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: set DRIVER_ATOMIC flag earlyAlex Deucher1-0/+12
The atomic debugfs stuff gets created in drm_dev_alloc() but this gets called before we've enumerated all of our IPs, so move the DRIVER_ATOMIC flag setting to fix that. Since DRIVER_ATOMIC is a driver flag it's currently global to the driver so setting it affects all GPUs driven by the driver. Unfortunately, not all GPUs support atomic. Warn the user if that is the case. This is the same as our current behavior, but at least the atomic debugfs stuff gets created now. Acked-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: remove DC special casing for KB/MLAlex Deucher1-3/+2
It seems to be working now. Bug: https://bugs.freedesktop.org/show_bug.cgi?id=102372 Reviewed-by: Mike Lothian <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: fill only the lower range with ATS entries v2Christian König1-29/+53
At least on x86-64 the upper range is purely used by the kernel, avoid creating any ATS mappings there as security precaution and to allow proper page fault reporting in the upper range. v2: remove unused variable Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: revert "Add support for filling a buffer with 64 bit value"Christian König9-39/+8
This reverts commit 7bdc53f925af085ffa0580f10489f82b36cc2f1c and commit 330df03b3abf944f8f5180f2abc61367749984c0. Neither are needed any more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: revert "Add a parameter to amdgpu_bo_create()"Christian König14-29/+21
This reverts commit 2046d46db9166bddc84778f0b3477f6d1e9068ea. Not needed any more. Signed-off-by: Christian König <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: drop root shadow syncChristian König1-5/+0
Completely pointless, it is the same reservation object as the root PD anyway. Signed-off-by: Christian König <[email protected]> Reviewed-by: Roger He <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: revert "drm/amdgpu: use AMDGPU_GEM_CREATE_VRAM_CLEARED for VM ↵Christian König1-24/+92
PD/PTs" v2 Using the standard clear turned out to be to inflexible. First of all it is executed on the system queue, together with buffer moves instead on the per VM queue. And second we need to fill in the page tables with more than just zero. We keep the new functionality of initializing the PDEs/PTEs with ATC routing entries intact. v2: update commit message. Signed-off-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: fix vcn_v1_0_dec_ring_emit_wregChristian König1-1/+18
That got mixed up with the encode ring function. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu/pm: rework the hwmon visibility settingsAlex Deucher1-13/+17
Previously we just always exposed everything for asics supported by powerplay. Make it a bit more fine grained. In practice this shouldn't change anything. Acked-by: Christian König <[email protected]> Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu/pp: remove the get_temperature APIAlex Deucher5-9/+0
This is also supported with the read_sensor API and there were no more users of the get_temperature API. Acked-by: Christian König <[email protected]> Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu/pm: use read_sensor API to get temperatureAlex Deucher1-8/+16
Rather than using the amdgpu_dpm_get_temperature. Both provide access to the temperature. Acked-by: Christian König <[email protected]> Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu/pm: report gpu average power via hwmon APIAlex Deucher1-0/+34
Expose power via hwmon. Acked-by: Christian König <[email protected]> Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu/pm: report gpu voltages via hwmon APIAlex Deucher1-0/+82
Expose vddgfx and vddnb via hwmon. Acked-by: Christian König <[email protected]> Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu/pm: handle fan properly when card is powered downAlex Deucher1-0/+20
Return an error if the user tried to check or set the fan parameters while the card is powered down (e.g., on a PX/HG system for example). This makes the fan consistent with the temperature stuff. Acked-by: Christian König <[email protected]> Reviewed-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: move static CSA address to top of address space v2Christian König4-13/+26
Move the CSA area to the top of the VA space to avoid clashing with HMM/ATC in the lower range on GFX9. v2: wrong sign noticed by Roger, rebase on CSA_VADDR cleanup, handle VA hole on GFX9 as well. Signed-off-by: Christian König <[email protected]> Acked-by: Alex Deucher <[email protected]> Acked-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu/soc15: don't abuse IP soft reset for adapter resetAlex Deucher3-20/+6
The IP soft reset interface is for per IP reset but it was being abused for adapter reset on soc15 asics. Adjust the interface to make it explicit. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu/psp: use a function pointer structureAlex Deucher6-116/+113
This way we can make all of the IP specific functions static, and we only need a single entry point into the PSP IP modules. Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: consistently use AMDGPU_CSA_VADDRChristian König2-7/+7
Instead of repeating this multiple times. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: apply top reserved VA space to pre Vega10 as wellChristian König4-4/+7
Reserve VA space at the top for older generations as well. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: reduce reserved VA sizeChristian König1-1/+1
1MB should be more than enough, currently we use about 8K. Signed-off-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Acked-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: rename amdgpu_crtc_idx_to_irq_typeSamuel Li8-13/+21
Add display to the name for consistency. Signed-off-by: Samuel Li <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: rename amdgpu_get_crtc_scanoutposSamuel Li4-18/+18
Add display to the name for consistency. Signed-off-by: Samuel Li <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: rename amdgpu_crtc_scaling_mode_fixupSamuel Li6-10/+10
Add display to the name for consistency. Signed-off-by: Samuel Li <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: rename amdgpu_update_display_prioritySamuel Li6-6/+6
Rename as amdgpu_display_update_priority for consistency. Signed-off-by: Samuel Li <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: rename amdgpu_modeset_create_propsSamuel Li7-7/+7
Add display to the name for consistency. Signed-off-by: Samuel Li <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: rename amdgpu_user_framebuffer_createSamuel Li2-7/+7
Add display to the name for consistency. Signed-off-by: Samuel Li <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: rename amdgpu_framebuffer_initSamuel Li3-11/+11
Add display to the name for consistency. Signed-off-by: Samuel Li <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: rename amdgpu_ddc_probeSamuel Li3-8/+11
Add display to the name for consistency. Signed-off-by: Samuel Li <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: rename amdgpu_print_display_setupSamuel Li6-6/+6
Add display to the name for consistency. Signed-off-by: Samuel Li <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: rename amdgpu_crtc_set_configSamuel Li7-9/+9
Add display to the name for consistency. Signed-off-by: Samuel Li <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: rename amdgpu_crtc_page_flip_targetSamuel Li7-15/+15
Add display to the name for consistency. Signed-off-by: Samuel Li <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: rename static functions in amdgpu_display.cSamuel Li1-19/+22
Add display to the name for consistency. Signed-off-by: Samuel Li <[email protected]> Acked-by: Christian König <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: remove now superflous *_hdp operationChristian König17-302/+18
All HDP invalidation and most flush can now be replaced by the generic ASIC function. Signed-off-by: Christian König <[email protected]> Acked-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: fallback to generic HDP operationChristian König1-8/+14
When ring special operations aren't available we can fallback to the generic ASIC operations. Signed-off-by: Christian König <[email protected]> Acked-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: add optional ring to *_hdp callbacksChristian König10-36/+81
This adds an optional ring to the invalidate_hdp and flush_hdp callbacks. If the ring isn't specified or the emit_wreg function not available the HDP operation will be done with the CPU otherwise by writing on the ring. Signed-off-by: Christian König <[email protected]> Acked-by: Chunming Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amd/pp: Add edit/commit/show OD clock/voltage support in sysfsRex Zhu2-1/+101
when cat pp_od_clk_voltage it show OD_SCLK: 0: 300Mhz 800 mV 1: 466Mhz 818 mV 2: 751Mhz 824 mV 3: 1019Mhz 987 mV 4: 1074Mhz 1037 mV 5: 1126Mhz 1087 mV 6: 1169Mhz 1137 mV 7: 1206Mhz 1150 mV OD_MCLK: 0: 300Mhz 800 mV 1: 1650Mhz 1000 mV echo "s/m level clock voltage" to change sclk/mclk's clock and voltage echo "r" to restore default value. echo "c" to commit the user setting. Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Rex Zhu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2018-02-19drm/amdgpu: drop the drm irq pre/post/un install callbacksAlex Deucher4-56/+6
The preinstall callback didn't do anything because not all of the IPs were initialized when it was called. Move the postinstall setup into sequence in the driver. The uninstall callback disabled all interrupt source, but it got called too late in the driver sequence and caused problems with IPs who already freed the relevant data structures. Move the call into the right place in the driver sequence. Acked-by: Christian König <[email protected]> Acked-by: Harry Wentland <[email protected]> Tested-By: Mikita Lipski <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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