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path: root/drivers/gpu/drm/amd/amdgpu
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2024-05-02drm/amdgpu/gfx: enable mes to map legacy queue supportJack Xiao2-25/+4
Enable mes to map legacy queue support. v2: drop unused gfx_v12_0_kiq_enable_kgq() (Alex) Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu/mes12: add mes mapping legacy queue supportJack Xiao1-0/+26
Add mes12 map legacy queue packet submission. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu/mes12: enable uni_mes fw on mes pipe0Jack Xiao1-13/+38
Enable the unified mes firmware on mes pipe0. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu/mes12: add uni_mes fw loading supportJack Xiao1-0/+10
Add the unified mes firmware loading support. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu/mes: add uni_mes fw loading supportJack Xiao2-1/+5
Add the unified mes firmware loading support. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdkfd: mark GFX12 system and peer GPU memory mappings as MTYPE_NCSreekant Somasekharan1-0/+9
Due to a HW bug, the system memory mappings and peer GPU mappings on GFX12 need to be marked as MTYPE_NC. Cc: Joe Greathouse <[email protected]> Cc: David Belanger <[email protected]> Signed-off-by: Rajneesh Bhardwaj <[email protected]> Signed-off-by: Sreekant Somasekharan <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdkfd: fix support for trap on wave start and end for gfx12Jonathan Kim1-5/+43
Similar to GFX11, GFX12 supports trapping on wave start and end. Signed-off-by: Jonathan Kim <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdkfd: always enable ttmp setup for gfx12Jonathan Kim2-1/+2
Similar to GFX11, always enable the setup of trap temporaries on GFX12. Signed-off-by: Jonathan Kim <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdkfd: Added gfx_v12_kfd2kgd interface for GFX12.David Belanger2-1/+341
Initial implementation, based on GFX11. v2: Removed functions not needed by cp scheduler. v3: Fixed typos. v4: squash in warning fix (Alex) Signed-off-by: David Belanger <[email protected]> Acked-by: Jonathan Kim <[email protected]> Reviewed-by: Harish Kasiviswanathan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: Enable event log on MES 12shaoyunl1-0/+4
Enable event log through the HW specific FW API Signed-off-by: shaoyunl <[email protected]> Reviewed-by: Harish Kasiviswanthan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: Enable unmapped doorbell handling basic mode on mes 12shaoyunl1-1/+15
Enable basic mode handling for doorbell ring on unmapped CP queue. In this mode, MES can start schedule the queue mapping based on HW interrupt instead of timer. Signed-off-by: shaoyunl <[email protected]> Reviewed-by: Harish Kasiviswanthan <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: Switch to smuio func to get gpu clk counterHawking Zhang1-9/+7
Switch to smuio callback to query gpu clock counter Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: init gfxhub setting to align with mmhubLikun Gao1-0/+39
Align gfxhub settings with mmhub when program rlc ram. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: skip dpm check to init imu fwLikun Gao1-1/+1
Skip dpm check to init imu firmware for imu v12. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: fix active rb and cu number for gfx12Likun Gao1-26/+55
Correct the algorithm of active CU and RB to bypass the disabled SA for gfx12. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: use new method to program rlc ramLikun Gao1-9/+61
Program rlc ram with golden setting data instead. The old method (program_imu_rlc_ram_old) should be retired in the future. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amd/amdgpu: add cgcg&cgls interface for gfx 12.0Kenneth Feng2-2/+191
add cgcg&cgls interface for gfx 12.0 Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amd/amdgpu: update GFX12 wave data registersTom St Denis1-2/+11
Update the registers for gfx12. Signed-off-by: Tom St Denis <[email protected]> Reviewed-by: Jonathan Kim <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: set different fw data addr for mec pipeLikun Gao1-4/+10
For MEC fw data, different pipe should programed into different address. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amd/amdgpu: workaround for the imu fw loadingKenneth Feng1-0/+5
workaournd for the imu fw loading on gfx 12.0 without psp Signed-off-by: Kenneth Feng <[email protected]> Reviewed-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amd: Move fw init from sw_init to early_init for imu v12Likun Gao1-8/+8
Move microcode loading from sw_init to early_init to align with the perious version of imu init sequence. Signed-off-by: Likun Gao <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: support S&R fw load for gfx v12Likun Gao1-0/+16
Support Save & Restore related fw load with backdoor RLC autoload type on gfx v12. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Kenneth Feng <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu/gfx12: recalculate available compute rings to useJack Xiao1-0/+7
Recalculate the number of compute rings to use based on the gfx hardware configuration. As needed reserve half of compute rings for mes, kgd can't use up all compute rings. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: skip imu related function if dpm=0Likun Gao1-3/+3
Only execute IMU related functions if dpm>0. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amd/amdgpu: imu fw loading supportKenneth Feng4-3/+337
support imu related function for gfx v12. Signed-off-by: Kenneth Feng <[email protected]> Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: set cp fw address set for gfx v12Likun Gao1-64/+122
Split PFF/ME/MEC firmware address setting function from related load microcode funtion, as it's also needed for rlc autolad. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: Add gfx v12_0 ip block support (v6)Likun Gao3-1/+4633
Initial support for GFX 12. v1: Add gfx v12_0 ip block support. (Likun) v2: Switch to gfx.kiq array. Move the vmhub from ring callback to ring. (Hawking) v3: Update various callback function impl. (Hawking) v4: Warning fixes (Alex) v5: squash in imu fix, csb, rlc autoload implementations (Alex) v6: Rebase (Alex) Signed-off-by: Likun Gao <[email protected]> Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu/mes12: update data cache boundaryJack Xiao1-2/+2
Enlarge the data cache boundary. v2: use the fix data cache boundary. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: fix trap enablement for gfx12Jonathan Kim1-0/+1
Fix request to MES to set SQ_SHADER_TBA_HI.trap_en for GFX12. Signed-off-by: Jonathan Kim <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: Enable MES to handle doorbell ring on unmapped queueshaoyunl1-0/+24
On MES12, HW can monitor up to 2048 doorbells that not be mapped currently and trigger the interrupt to MES when these unmapped doorbell been ringed. Signed-off-by: shaoyunl <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: enable mes v12 self testJack Xiao2-1/+7
1. fix available compute queue to use 2. enable mes v12 self test Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: set mes fw address for mes v12Likun Gao1-9/+28
Split the function of mes fimrware address setting from mes firmware load for mes v12, as it's also needed for rlc autoload. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: Add mes v12_0 ip block support (v4)Jack Xiao3-1/+1337
v1: Add mes v12_0 ip block support. (Jack) v2: Switch to gfx.kiq array. (Hawking) v3: Switch to AMDGPU_GFXHUB(0). (Hawking) v4: Rebase (Alex) Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: init mes ucode name for gfx v12Likun Gao1-1/+2
Keep gfx v12 mes fw name to gc_12_x_x_mes.bin and gc_12_x_x_mes1.bin. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: add rlc TOC header file for soc24Likun Gao1-0/+47
Add RLC autoload TOC header file for soc24 ASIC. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: add new TOC structureLikun Gao1-0/+27
Add new RLC_TABLE_OF_CONTENT structure definition. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: add gfx12 clearstate headerLikun Gao1-0/+121
Add gfx12 clearstate register arrays. Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu/discovery: Set GC family for GC 12.0 IPLikun Gao1-0/+4
Set GC family for GC 12.0 IPs. v2: squash in updates (Alex) Signed-off-by: Likun Gao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: IB test encode test package change for VCN5Sonny Jiang1-2/+2
VCN5 session info package interface changed Signed-off-by: Sonny Jiang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: Add gfx v9_4_4 ip blockHawking Zhang9-18/+55
Add gfx v9_4_4 ip block support Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: Add smu v13_0_14 ip blockHawking Zhang7-3/+15
Add smu v13_0_14 ip block support Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: Add psp v13_0_14 ip blockHawking Zhang5-7/+24
Add psp v13_0_14 ip block support. Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: Add sdma v4_4_5 ip blockHawking Zhang5-12/+24
Add sdma v4_4_5 ip block support Signed-off-by: Hawking Zhang <[email protected]> Reviewed-by: Le Ma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amd: Override DCN410 IP versionAurabindo Pillai1-0/+4
Override DCN IP version to 4.0.1 from 4.1.0 temporarily until change is made in DC codebase to use 4.1.0 Signed-off-by: Aurabindo Pillai <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdkfd: handle duplicate BOs in reserve_bo_and_cond_vmsLang Yu1-1/+2
Observed on gfx8 ASIC where KFD_IOC_ALLOC_MEM_FLAGS_AQL_QUEUE_MEM is used. Two attachments use the same VM, root PD would be locked twice. [ 57.910418] Call Trace: [ 57.793726] ? reserve_bo_and_cond_vms+0x111/0x1c0 [amdgpu] [ 57.793820] amdgpu_amdkfd_gpuvm_unmap_memory_from_gpu+0x6c/0x1c0 [amdgpu] [ 57.793923] ? idr_get_next_ul+0xbe/0x100 [ 57.793933] kfd_process_device_free_bos+0x7e/0xf0 [amdgpu] [ 57.794041] kfd_process_wq_release+0x2ae/0x3c0 [amdgpu] [ 57.794141] ? process_scheduled_works+0x29c/0x580 [ 57.794147] process_scheduled_works+0x303/0x580 [ 57.794157] ? __pfx_worker_thread+0x10/0x10 [ 57.794160] worker_thread+0x1a2/0x370 [ 57.794165] ? __pfx_worker_thread+0x10/0x10 [ 57.794167] kthread+0x11b/0x150 [ 57.794172] ? __pfx_kthread+0x10/0x10 [ 57.794177] ret_from_fork+0x3d/0x60 [ 57.794181] ? __pfx_kthread+0x10/0x10 [ 57.794184] ret_from_fork_asm+0x1b/0x30 Signed-off-by: Lang Yu <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: Move ras resume into SRIOV functionYunxiang Li1-7/+5
This is part of the reset, move it into the reset function. Signed-off-by: Yunxiang Li <[email protected]> Reviewed-by: Emily Deng <[email protected]> Reviewed-by: Zhigang Luo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu/vpe: fix vpe dpm clk ratio setup failedPeyton Lee1-2/+11
Some version of BIOS does not enable all clock levels, resulting in high level clock frequency of 0. The number of valid CLKs must be confirmed in advance. Signed-off-by: Peyton Lee <[email protected]> Reviewed-by: Lang Yu <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: Fix amdgpu_device_reset_sriov retry logicYunxiang Li1-25/+22
The retry loop for SRIOV reset have refcount and memory leak issue. Depending on which function call fails it can potentially call amdgpu_amdkfd_pre/post_reset different number of times and causes kfd_locked count to be wrong. This will block all future attempts at opening /dev/kfd. The retry loop also leakes resources by calling amdgpu_virt_init_data_exchange multiple times without calling the corresponding fini function. Align with the bare-metal reset path which doesn't have these issues. This means taking the amdgpu_amdkfd_pre/post_reset functions out of the reset loop and calling amdgpu_device_pre_asic_reset each retry which properly free the resources from previous try by calling amdgpu_virt_fini_data_exchange. Signed-off-by: Yunxiang Li <[email protected]> Reviewed-by: Emily Deng <[email protected]> Reviewed-by: Zhigang Luo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amd: Enable DCN410 initAurabindo Pillai1-0/+1
Enable initializing Display Manager for DCN410 IP Signed-off-by: Aurabindo Pillai <[email protected]> Reviewed-by: Harry Wentland <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2024-05-02drm/amdgpu: Add reset_context flag for host FLRYunxiang Li5-5/+12
There are other reset sources that pass NULL as the job pointer, such as amdgpu_amdkfd_reset_work. Therefore, using the job pointer to check if the FLR comes from the host does not work. Add a flag in reset_context to explicitly mark host triggered reset, and set this flag when we receive host reset notification. Signed-off-by: Yunxiang Li <[email protected]> Reviewed-by: Emily Deng <[email protected]> Reviewed-by: Zhigang Luo <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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