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2021-06-04drm: amdgpu: Remove unneeded semicolon in amdgpu_vm.cWan Jiabing1-1/+1
Fix following coccicheck warning: ./drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c:1726:2-3: Unneeded semicolon Reviewed-by: Christian König <[email protected]> Signed-off-by: Wan Jiabing <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: Modify GC register access to use _SOC15 macrosRohit Khaire1-21/+21
In SRIOV environment, KMD should access GC registers with RLCG if GC indirect access flag enabled. Using _SOC15 read/write macros ensures that they go through RLC when flag is enabled. Signed-off-by: Rohit Khaire <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: Enable RLCG read/write interface for Sienna CichlidRohit Khaire1-1/+1
Enable this only for Sienna Cichild since only Navi12 and Sienna Cichlid support SRIOV Signed-off-by: Rohit Khaire <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: Fix incorrect register offsets for Sienna CichlidRohit Khaire1-5/+21
RLC_CP_SCHEDULERS and RLC_SPARE_INT0 have different offsets for Sienna Cichlid Signed-off-by: Rohit Khaire <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: Don't flush/invalidate HDP for APUs and A+AEric Huang6-21/+42
Integrate two generic functions to determine if HDP flush is needed for all Asics. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: remove redundant assignment of variable kColin Ian King1-1/+1
The variable k is being assigned a value that is never read, the assignment is redundant and can be removed. Addresses-Coverity: ("Unused value") Signed-off-by: Colin Ian King <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdkfd: Make TLB flush conditional on mappingEric Huang2-9/+12
It is to optimize memory mapping latency, and also aviod a page fault in a corner case of changing valid PDE into PTE. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: Add table_freed parameter to amdgpu_vm_bo_updateEric Huang4-10/+10
It is to pass the flag to KFD, and optimize table_freed in amdgpu_vm_bo_update_mapping. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Felix Kuehling <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: Use drm_dbg_kms for reporting failure to get a GEM FBMichel Dänzer1-2/+2
drm_err meant broken user space could spam dmesg. Fixes: f258907fdd835e "drm/amdgpu: Verify bo size can fit framebuffer size on init." Reviewed-by: Christian König <[email protected]> Signed-off-by: Michel Dänzer <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: switch kzalloc to kvzalloc in amdgpu_bo_createChangfeng1-2/+2
It will cause error when alloc memory larger than 128KB in amdgpu_bo_create->kzalloc. So it needs to switch kzalloc to kvzalloc. Call Trace: alloc_pages_current+0x6a/0xe0 kmalloc_order+0x32/0xb0 kmalloc_order_trace+0x1e/0x80 __kmalloc+0x249/0x2d0 amdgpu_bo_create+0x102/0x500 [amdgpu] ? xas_create+0x264/0x3e0 amdgpu_bo_create_vm+0x32/0x60 [amdgpu] amdgpu_vm_pt_create+0xf5/0x260 [amdgpu] amdgpu_vm_init+0x1fd/0x4d0 [amdgpu] Signed-off-by: Changfeng <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: soc15 register access through RLC should only apply to sriov runtimeshaoyunl1-2/+2
On SRIOV, driver should only access register through RLC in runtime Acked-by: Alex Deucher <[email protected]> Signed-off-by: shaoyunl <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/amdgpu: attr to control SS2.0 bias level (v2)Sathishkumar S2-0/+6
add sysfs attr to read/write smartshift bias level. document smartshift_bias sysfs attr. V2: add attr to amdgpu_device_attrs and use attr_update (Lijo) Signed-off-by: Sathishkumar S <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-04drm/ttm: flip the switch for driver allocated resources v2Christian König4-61/+50
Instead of both driver and TTM allocating memory finalize embedding the ttm_resource object as base into the driver backends. v2: fix typo in vmwgfx grid mgr and double init in amdgpu_vram_mgr.c Signed-off-by: Christian König <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-04drm/amdgpu: switch the VRAM backend to self allocChristian König1-21/+30
Similar to the TTM range manager. Signed-off-by: Christian König <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-04drm/amdgpu: switch the GTT backend to self allocChristian König1-14/+22
Similar to the TTM range manager. Signed-off-by: Christian König <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-04drm/amdgpu: revert "drm/amdgpu: stop allocating dummy GTT nodes"Christian König1-29/+39
TTM is going to need this again since we are moving the resource allocation into the backend. Signed-off-by: Christian König <[email protected]> Acked-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-04drm/ttm: flip over the range manager to self allocated nodesChristian König1-0/+1
Start with the range manager to make the resource object the base class for the allocated nodes. While at it cleanup a lot of the code around that. Signed-off-by: Christian König <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-04drm/ttm: allocate resource object instead of embedding it v2Christian König2-29/+29
To improve the handling we want the establish the resource object as base class for the backend allocations. v2: add missing error handling Signed-off-by: Christian König <[email protected]> Acked-by: Thomas Hellström <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-04Merge tag 'amd-drm-next-5.14-2021-06-02' of ↵Dave Airlie67-632/+1442
https://gitlab.freedesktop.org/agd5f/linux into drm-next amd-drm-next-5.14-2021-06-02: amdgpu: - GC/MM register access macro clean up for SR-IOV - Beige Goby updates - W=1 Fixes - Aldebaran fixes - Misc display fixes - ACPI ATCS/ATIF handling rework - SR-IOV fixes - RAS fixes - 16bpc fixed point format support - Initial smartshift support - RV/PCO power tuning fixes for suspend/resume - More buffer object subclassing work - Add new INFO query for additional vbios information - Add new placement for preemptable SG buffers amdkfd: - Misc fixes radeon: - W=1 Fixes - Misc cleanups UAPI: - Add new INFO query for additional vbios information Useful for debugging vbios related issues. Proposed umr patch: https://patchwork.freedesktop.org/patch/433297/ - 16bpc fixed point format support IGT test: https://lists.freedesktop.org/archives/igt-dev/2021-May/031507.html Proposed Vulkan patch: https://github.com/kleinerm/pal/commit/a25d4802074b13a8d5f7edc96ae45469ecbac3c4 - Add a new GEM flag which is only used internally in the kernel driver. Userspace is not allowed to set it. drm: - 16bpc fixed point format fourcc Signed-off-by: Dave Airlie <[email protected]> From: Alex Deucher <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-02drm/amdgpu: make sure we unpin the UVD BONirmoy Das1-0/+1
Releasing pinned BOs is illegal now. UVD 6 was missing from: commit 2f40801dc553 ("drm/amdgpu: make sure we unpin the UVD BO") Fixes: 2f40801dc553 ("drm/amdgpu: make sure we unpin the UVD BO") Cc: [email protected] Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-02drm/amd/amdgpu:save psp ring wptr to avoid attackVictor Zhao3-2/+5
[Why] When some tools performing psp mailbox attack, the readback value of register can be a random value which may break psp. [How] Use a psp wptr cache machanism to aovid the change made by attack. v2: unify change and add detailed reason Signed-off-by: Victor Zhao <[email protected]> Signed-off-by: Jingwen Chen <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-02drm/amdgpu: Don't query CE and UE errorsLuben Tuikov1-16/+0
On QUERY2 IOCTL don't query counts of correctable and uncorrectable errors, since when RAS is enabled and supported on Vega20 server boards, this takes insurmountably long time, in O(n^3), which slows the system down to the point of it being unusable when we have GUI up. Fixes: ae363a212b14 ("drm/amdgpu: Add a new flag to AMDGPU_CTX_OP_QUERY_STATE2") Cc: Alexander Deucher <[email protected]> Cc: [email protected] Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Alexander Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-02drm/amdgpu: refine amdgpu_fru_get_product_infoJiansong Chen1-19/+23
1. eliminate potential array index out of bounds. 2. return meaningful value for failure. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Jack Gui <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-02drm/amdgpu: add judgement for dc supportAsher Song1-1/+3
Drop DC initialization when DCN is harvested in VBIOS. The way doesn't affect virtual display ip initialization. Signed-off-by: Likun Gao <[email protected]> Signed-off-by: Asher Song <[email protected]> Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-02drm/ttm: rename bo->mem and make it a pointerChristian König11-68/+72
When we want to decouble resource management from buffer management we need to be able to handle resources separately. Add a resource pointer and rename bo->mem so that all code needs to change to access the pointer instead. No functional change. Signed-off-by: Christian König <[email protected]> Reviewed-by: Matthew Auld <[email protected]> Link: https://patchwork.freedesktop.org/patch/msgid/[email protected]
2021-06-01drm/amdgpu: remove unsafe optimization to drop preamble ibJiansong Chen1-10/+1
Take the situation with gfxoff, the optimization may cause corrupt CE ram contents. In addition emit_cntxcntl callback has similar optimization which firmware can handle properly even for power feature. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-01drm/amdgpu: Add vbios info ioctl interfaceJiawei Gu3-0/+197
Add AMDGPU_INFO_VBIOS_INFO subquery id for detailed vbios info. Provides a way for the user application to get the VBIOS information without having to parse the binary. It is useful for the user to be able to display in a simple way the VBIOS version in their system if they happen to encounter an issue. V2: Use numeric serial. Parse and expose vbios version string. V3: Remove redundant data in drm_amdgpu_info_vbios struct. V4: 64 bit alignment in drm_amdgpu_info_vbios. v5: squash together all the reverts, etc. (Alex) Signed-off-by: Jiawei Gu <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-01drm/amdgpu: bump driver versionAlex Deucher1-1/+2
For 16bpc display support. Reviewed-by: Mario Kleiner <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: Mario Kleiner <[email protected]>
2021-06-01drm/amdgpu: Remove unneeded semicolonZheng Yongjun1-1/+1
Remove unneeded semicolon. Signed-off-by: Zheng Yongjun <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-01amdgpu: remove unreachable codeJiapeng Chong1-2/+1
In the function amdgpu_uvd_cs_msg(), every branch in the switch statement will have a return, so the code below the switch statement will not be executed. Eliminate the follow smatch warning: drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.c:845 amdgpu_uvd_cs_msg() warn: ignoring unreachable code. Reported-by: Abaci Robot <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Jiapeng Chong <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-01drm/amdgpu: Fix a bug on flag table_freedEric Huang1-2/+5
table_freed will be always true when mapping a memory with size bigger than 2MB. The problem is page table's entries are always existed, but existing mapping depends on page talbe's bo, so using a check of page table's bo existed will resolve the issue. Signed-off-by: Eric Huang <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-01drm/amdgpu: optimize code about format string in gfx_v10_0_init_microcode()Kevin Wang1-3/+2
the memset() and snprintf() is not necessary. Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-01drm/amdgpu: fix sdma firmware version error in sriovKevin Wang1-3/+3
Re-adjust the function return order to avoid empty sdma version in the sriov environment. (read amdgpu_firmware_info) Signed-off-by: Kevin Wang <[email protected]> Reviewed-by: Stanley.Yang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-01drm/amdgpu: enable smart shift on dGPU (v5)Sathishkumar S4-0/+97
enable smart shift on dGPU if it is part of HG system and the platform supports ATCS method to handle power shift. V2: avoid psc updates in baco enter and exit (Lijo) fix alignment (Shashank) V3: rebased on unified ATCS handling. (Alex) V4: check for return value and warn on failed update (Shashank) return 0 if device does not support smart shift. (Lizo) V5: rebased on ATPX/ATCS structures global (Alex) Signed-off-by: Sathishkumar S <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Reviewed-by: Shashank Sharma <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-01drm/amdgpu: flush gart changes after all BO recoveryNirmoy Das4-8/+21
Don't flush gart changes after recovering each BO instead do it after recovering all the BOs. Flishing gart also needed for amdgpu_ttm_alloc_gart(). v4: use containerof to retrieve adev struct. v3: rename amdgpu_gart_tlb_flush() -> amdgpu_gart_invalidate_tlb(). v2: abstract out gart tlb flushing logic to amdgpu_gart.c Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-01drm/amdgpu: do not allocate entries separatelyNirmoy Das1-14/+20
Allocate PD/PT entries while allocating VM BOs and use that instead of allocating those entries separately. v2: create a new var for num entries. Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-01drm/amdgpu: remove unused codeNirmoy Das2-35/+0
Remove unused code related to shadow BO. v2: removing shadow bo ptr from base class. Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-01drm/amdgpu: switch to amdgpu_bo_vm for vm codeNirmoy Das4-65/+96
The subclass, amdgpu_bo_vm is intended for PT/PD BOs which are also shadowed, so switch to amdgpu_bo_vm BO for PT/PD BOs. v4: update amdgpu_vm_update_funcs to accept amdgpu_bo_vm. v3: simplify code. check also if shadow bo exist instead of checking bo only type. v2: squash three related patches. Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-01drm/admgpu: add two shadow BO helper functionsNirmoy Das2-0/+33
Add amdgpu_bo_add_to_shadow_list() to handle shadow list additions and amdgpu_bo_shadowed() to check if a BO is shadowed. Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-01drm/amdgpu: move shadow bo validation to VM codeNirmoy Das2-19/+9
Do the shadow bo validation in the VM code as VM code knows/owns shadow BOs. Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-01drm/amdgpu: add amdgpu_bo_vm bo typeNirmoy Das2-0/+42
Add new BO subclass that will be used by amdgpu vm code. Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-01drm/amdgpu: make sure we unpin the UVD BONirmoy Das1-0/+1
Releasing pinned BOs is illegal now. UVD 6 was missing from: commit 2f40801dc553 ("drm/amdgpu: make sure we unpin the UVD BO") Fixes: 2f40801dc553 ("drm/amdgpu: make sure we unpin the UVD BO") Cc: [email protected] Signed-off-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-01drm/amdgpu: support atcs method powershift (v4)Sathishkumar S2-0/+61
add support to handle ATCS method for power shift control. used to communicate dGPU device state to SBIOS. V2: use defined acpi func for checking psc support (Lijo) fix alignment (Shashank) V3: rebased on unified ATCS handling (Alex) V4: rebased on ATPX/ATCS structures global (Alex) Signed-off-by: Sathishkumar S <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-01drm/amdgpu: free the metadata buffer for sg type BOs as wellShiwu Zhang1-1/+1
Since both sg and device type BOs have metadata buffer, free the buffer in both cases when to destroy BOs Signed-off-by: Shiwu Zhang <[email protected]> Acked-by: Nirmoy Das <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-06-01drm/amdgpu: fix metadata_size for ubo ioctl queriesShiwu Zhang1-2/+3
Although the kfd_ioctl_get_dmabuf_info() still fail it will indicate the caller right metadat_size useful for the same kfd ioctl next time. Signed-off-by: Shiwu Zhang <[email protected]> Reviewed-by: Nirmoy Das <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-27drm/amdgpu/acpi: make ATPX/ATCS structures global (v2)Alex Deucher3-160/+138
They are global ACPI methods, so maybe the structures global in the driver. This simplified a number of things in the handling of these methods. v2: reset the handle if verify interface fails (Lijo) v3: fix compilation when ACPI is not defined. Reviewed-by: Lijo Lazar <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-27drm/amd/amdgpu:save psp ring wptr to avoid attackVictor Zhao3-2/+5
[Why] When some tools performing psp mailbox attack, the readback value of register can be a random value which may break psp. [How] Use a psp wptr cache machanism to aovid the change made by attack. v2: unify change and add detailed reason Signed-off-by: Victor Zhao <[email protected]> Signed-off-by: Jingwen Chen <[email protected]> Reviewed-by: Monk Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-27drm/amd/amdgpu/amdgpu_device: Make local function staticLee Jones1-1/+1
Fixes the following W=1 kernel build warning(s): drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:4624:6: warning: no previous prototype for ‘amdgpu_device_recheck_guilty_jobs’ [-Wmissing-prototypes] Cc: Alex Deucher <[email protected]> Cc: "Christian König" <[email protected]> Cc: David Airlie <[email protected]> Cc: Daniel Vetter <[email protected]> Cc: Sumit Semwal <[email protected]> Cc: [email protected] Cc: [email protected] Cc: [email protected] Cc: [email protected] Signed-off-by: Lee Jones <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-27drm/amdgpu/acpi: fix typo in ATCS handlingAlex Deucher1-1/+1
Path should be NULL when we already have the handle to the object. Reviewed-by: Lijo Lazar <[email protected]> Tested-by: Sathishkumar S <[email protected]> Reviewed-by: Sathishkumar S <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2021-05-27drm/amdgpu: Use delayed work to collect RAS error countersLuben Tuikov3-2/+74
On Context Query2 IOCTL return the correctable and uncorrectable errors in O(1) fashion, from cached values, and schedule a delayed work function to calculate and cache them for the next such IOCTL. v2: Cancel pending delayed work at ras_fini(). v3: Remove conditionals when dealing with delayed work manipulation as they're inherently racy. Cc: Alexander Deucher <[email protected]> Cc: Christian König <[email protected]> Cc: John Clements <[email protected]> Cc: Hawking Zhang <[email protected]> Signed-off-by: Luben Tuikov <[email protected]> Reviewed-by: Alexander Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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