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path: root/drivers/gpu/drm/amd/amdgpu
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2020-07-15drm/amdgpu: enable VCN3.0 DPG for navy_flounderBoyuan Zhang1-1/+2
Enable VCN3.0 DPG for navy_flounder by setting up the flag to the ASIC Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: enable VCN3.0 PG and CG for navy_flounderBoyuan Zhang1-2/+2
Enable VCN3.0 PG and CG for navy_flounder by setting up the flags to the ASIC Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: enable cp_fw_write_wait for navy_flounderJiansong Chen1-0/+1
It's the same with sienna_cichlid, cp fw for navy_flounder can support WAIT_REG_MEM packet. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add vcn ip block for navy_flounderBoyuan Zhang1-0/+2
Add vcn3.0 and jpeg3.0 ip blocks for navy_flounder Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add navy_flounder vcn firmware supportBoyuan Zhang1-0/+8
Add navy_flounder to vcn family Signed-off-by: Boyuan Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu/gfx10: add gc golden setting for navy_flounderJiansong Chen1-0/+48
Add gc golden setting for navy_flounder Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: use front door firmware loading for navy_flounderJiansong Chen1-2/+1
Same as other navi asics. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add psp block for navy_flounderJiansong Chen1-0/+5
Add psp and smu block for navy_flounder with psp firmware load type. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add psp support for navy_flounderJiansong Chen2-4/+16
Currently skip ASD FW loading and ih reroute per sienna_cichlid. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add smu block for navy_flounderJiansong Chen1-0/+3
Add SMU block for navy_flounder with direct firmware load type. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add gmc cg support for navy_flounderJiansong Chen2-2/+5
The athub version used for navy_flounder is v2.1. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: force pa_sc_tile_steering_override to 0 for navy_flounderJiansong Chen1-1/+2
pa_sc_tile_steering_override is only programmable for gfx10.0/10.1/10.2, and navy_flounder has the same gfx10.3 IP with sienna_cichlid. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: configure navy_flounder gfx according to gfx 10.3Tao Zhou1-0/+9
The gfx version of navy_flounder is 10.3, identical to sienna_cichlid, follow the way of sienna_cichlid. Signed-off-by: Tao Zhou <[email protected]> Reviewed-by: Jiansong Chen <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add virtual display support for navy_flounder.Jiansong Chen1-0/+2
Virtual display support for bring up and virtualization. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add sdma ip block for navy_flounderJiansong Chen2-2/+19
Navy_Flounder has the same sdma IP version with sienna_cichlid, and it has 2 sdma controllers. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add gfx ip block for navy_flounderJiansong Chen2-0/+5
since navy_flounder has similar gc IP version with sienna_cichlid, follow its setting for the moment. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add ih ip block for navy_flounderJiansong Chen2-0/+2
navy_flounder has the same osssys IP verison with sienna_cichlid, follow its setting. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add gmc ip block for navy_flounderJiansong Chen2-6/+13
navy_flounder has similar gc IP version with sienna_cichlid, follow its setting for the moment. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add common ip block for navy_flounderJiansong Chen1-0/+3
Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add support on mmhub for navy_flounderJiansong Chen1-0/+5
navy_flounder has the same mmhub IP version with sienna_cichlid, follow its setting. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: initialize IP offset for navy_flounderJiansong Chen1-0/+1
since navy_flounder has the same ip offset with sienna_cichlid, follow sienna_cichlid setting for the moment. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu/soc15: add support for navy_flounderJiansong Chen1-0/+7
Add soc support. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu/gfx10: add clockgating support for navy_flounderJiansong Chen1-0/+1
Same as navi10. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu/gmc10: add navy_flounder supportJiansong Chen1-0/+3
Same as navi10. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu/gfx10: add support for navy_flounder firmwareJiansong Chen1-0/+10
Declare the gfx/compute firmwares. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: set asic family and ip blocks for navy_flounderJiansong Chen1-0/+1
Add the asic family and IP blocks for navy flounder. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: set fw load type for navy_flounderJiansong Chen1-1/+2
Currently navy_flounder only supports backdoor loading type. Will switch to psp load type when psp is ready. Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add navy_flounder gpu info firmwareJiansong Chen1-0/+4
Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add navy_flounder asic typeJiansong Chen1-0/+1
Signed-off-by: Jiansong Chen <[email protected]> Reviewed-by: Tao Zhou <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: expand to add multiple trap event irq idHuang Rui1-26/+41
Sienna_cichlid has four sdma instances, but other chips don't. So we need expand to add multiple trap event irq id in sdma v5.2. Signed-off-by: Huang Rui <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/sriov skip vcn powergating and dec_ring_testJack Zhang2-5/+20
1.Skip decode_ring test in VF, because VCN in SRIOV does not support direct register read/write. 2.Skip powergating configuration in hw fini because VCN3.0 SRIOV doesn't support powergating. V2: delete unneccessary white lines and refine implementation. Signed-off-by: Jack Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: correct ta header v2 ucode init start addressJohn Clements1-1/+3
resolve bug calculating fw start address within binary Reviewed-by: Guchun Chen <[email protected]> Signed-off-by: John Clements <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/sriov porting sriov cap to vcn3.0Jack Zhang1-32/+318
1.In early_init and for sriov, hardcode harvest_config=0, enc_num=1 2.sw_init/fini alloc & free mm_table for sriov doorbell setting for sriov 3.hw_init/fini Under sriov, add start_sriov to config mmsch Skip ring_test to avoid mmio in VF, but need to initialize wptr for vcn rings. 4.Implementation for vcn_v3_0_start_sriov V2:Clean-up some uneccessary funciton declaration. Signed-off-by: Jack Zhang <[email protected]> Reviewed-by: Leo Liu <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/sriov add mmsch_v3 interfaceJack Zhang1-0/+130
For VCN3.0 SRIOV, Guest driver needs to communicate with mmsch to set the World Switch for MM appropriately. This patch add the interface for mmsch_v3.0. Signed-off-by: Jack Zhang <[email protected]> Reviewed-by: Dennis Li <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: optimize rlcg write for gfx_v10Jack Zhang1-7/+19
For gfx10 boards, except for nv12, other boards take mmio write rather than rlcg write Signed-off-by: Jack Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/sriov skip jped ip block and close pgcg flagsJack Zhang1-1/+8
For SIENNA_CICHLID SRIOV, jpeg and pgcp is not supported. Signed-off-by: Jack Zhang <[email protected]> Acked-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: drop unused APIs and parametersEvan Quan1-6/+6
Leftover of previous performance level setting cleanups. Signed-off-by: Evan Quan <[email protected]> Reviewed-by: Alex Deucher <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: add module parameter choose reset modeWenhui Sheng7-0/+47
Default value is auto, doesn't change original reset method logic. v2: change to use parameter reset_method v3: add warn msg if specified mode isn't supported Signed-off-by: Likun Gao <[email protected]> Signed-off-by: Wenhui Sheng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: enable mode1 resetWenhui Sheng1-7/+12
For sienna cichlid, add mode1 reset path for sGPU. v2: hiding MP0/MP1 mode1 reset under AMD_RESET_METHOD_MODE1 v3: split emergency restart logic to a new patch Signed-off-by: Likun Gao <[email protected]> Signed-off-by: Wenhui Sheng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amdgpu: RAS emergency restart logic refineWenhui Sheng3-11/+24
If we are in RAS triggered situation and BACO isn't support, emergency restart is needed, and this code is only needed for some specific cases(vega20 with given smu fw version). After we add smu mode1 reset for sienna cichlid, we need to share AMD_RESET_METHOD_MODE1 with psp mode1 reset, so in amdgpu_device_gpu_recover, we need differentiate which mode1 reset we are using, then decide if it's a full reset and then decide if emergency restart is needed, the logic will become much more complex. After discussion with Hawking, move emergency restart logic to an independent function. Signed-off-by: Likun Gao <[email protected]> Signed-off-by: Wenhui Sheng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-15drm/amd/powerplay: add SMU mode1 resetWenhui Sheng2-0/+23
From PM FW 58.26.0 for sienna cichlid, SMU mode1 reset is support, driver sends PPSMC_MSG_Mode1Reset message to PM FW could trigger this reset. v2: add mode1 reset dpm interface v3: change maro name Signed-off-by: Likun Gao <[email protected]> Signed-off-by: Wenhui Sheng <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-14drm/amdgpu/sdma5: fix wptr overwritten in ->get_wptr()Xiaojie Yuan1-18/+8
"u64 *wptr" points to the the wptr value in write back buffer and "*wptr = (*wptr) >> 2;" results in the value being overwritten each time when ->get_wptr() is called. umr uses /sys/kernel/debug/dri/0/amdgpu_ring_sdma0 to get rptr/wptr and decode ring content and it is affected by this issue. fix and simplify the logic similar as sdma_v4_0_ring_get_wptr(). v2: fix for sdma5.2 as well v3: drop sdma 5.2 changes for 5.8 and stable Suggested-by: Le Ma <[email protected]> Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]> Cc: [email protected]
2020-07-14drm/amdgpu: fix preemption unit testJack Xiao1-5/+15
Remove signaled jobs from job list and ensure the job was indeed preempted. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-14drm/amdgpu/gfx10: fix race condition for kiqJack Xiao1-1/+8
During preemption test for gfx10, it uses kiq to trigger gfx preemption, which would result in race condition with flushing TLB for kiq. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Acked-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-14drm/amdgpu/sdma5: fix wptr overwritten in ->get_wptr()Xiaojie Yuan2-36/+16
"u64 *wptr" points to the the wptr value in write back buffer and "*wptr = (*wptr) >> 2;" results in the value being overwritten each time when ->get_wptr() is called. umr uses /sys/kernel/debug/dri/0/amdgpu_ring_sdma0 to get rptr/wptr and decode ring content and it is affected by this issue. fix and simplify the logic similar as sdma_v4_0_ring_get_wptr(). v2: fix for sdma5.2 as well Suggested-by: Le Ma <[email protected]> Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Christian König <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-14drm/amdgpu: use ARRAY_SIZE() to add amdgpu debugfs filesXiaojie Yuan3-4/+8
to easily add new debugfs file w/o changing the hardcoded list count. Signed-off-by: Xiaojie Yuan <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-13drm/amdgpu: stop allocating dummy GTT nodesChristian König2-80/+42
Now that TTM is fixed up we can finally stop that nonsense. Signed-off-by: Christian König <[email protected]> Reviewed-by: Madhav Chauhan <[email protected]> Link: https://patchwork.freedesktop.org/patch/375620
2020-07-13drm: amdgpu: fix common struct sg_table related issuesMarek Szyprowski3-13/+10
The Documentation/DMA-API-HOWTO.txt states that the dma_map_sg() function returns the number of the created entries in the DMA address space. However the subsequent calls to the dma_sync_sg_for_{device,cpu}() and dma_unmap_sg must be called with the original number of the entries passed to the dma_map_sg(). struct sg_table is a common structure used for describing a non-contiguous memory buffer, used commonly in the DRM and graphics subsystems. It consists of a scatterlist with memory pages and DMA addresses (sgl entry), as well as the number of scatterlist entries: CPU pages (orig_nents entry) and DMA mapped pages (nents entry). It turned out that it was a common mistake to misuse nents and orig_nents entries, calling DMA-mapping functions with a wrong number of entries or ignoring the number of mapped entries returned by the dma_map_sg() function. To avoid such issues, lets use a common dma-mapping wrappers operating directly on the struct sg_table objects and use scatterlist page iterators where possible. This, almost always, hides references to the nents and orig_nents entries, making the code robust, easier to follow and copy/paste safe. Signed-off-by: Marek Szyprowski <[email protected]> Reviewed-by: Christian König <[email protected]> Link: https://patchwork.freedesktop.org/patch/371142/ Signed-off-by: Christian König <[email protected]>
2020-07-10drm/amdgpu: fix spelling mistake "Falied" -> "Failed"Colin Ian King1-1/+1
There is a spelling mistake in a DRM_ERROR error message. Fix it. Signed-off-by: Colin Ian King <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
2020-07-10drm/amdgpu: fix preemption unit testJack Xiao1-5/+15
Remove signaled jobs from job list and ensure the job was indeed preempted. Signed-off-by: Jack Xiao <[email protected]> Reviewed-by: Hawking Zhang <[email protected]> Signed-off-by: Alex Deucher <[email protected]>
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